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cfif 2025-09-23 13:35:15 +03:00
commit 5774b88dd2
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157
APP/Clock.c Normal file
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#include "Clock.h"
/* ################################################################################## */
/* ################################### Type define ################################## */
/* PCBA external oscillator value, these macro is user defined. */
/* FOSC/SOSC clock need to manually configuration according to PCBA XTAL value
* in SOSC/FOSc configuration.
* Current default value is the XTAL value on EVB board. */
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
static void Bsp_SCG_Init(void);
static void Bsp_PCC_Init(void);
/* ################################################################################## */
/* ################################ Local Functions ################################# */
/**
* @brief Local SCG initial
*
*/
static void Bsp_SCG_Init(void)
{
/* Enable FOSC, frequency is 24M, DIVH=DIV1(24M), DIVM=DIV1(24M), DIVL=DIV2(12M)*/
SCG_FoscType tFoscStruct =
{
.bLock = false,
.bCm = false,
.bCmre = false,
.bSten = false,
.bBypass = false,
.eDivH = SCG_ASYNCCLOCKDIV_BY1,
.eDivM = SCG_ASYNCCLOCKDIV_BY1,
.eDivL = SCG_ASYNCCLOCKDIV_BY2,
};
SCG_EnableFOSC(&tFoscStruct);
/* Enable PLL0, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/
/* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/
SCG_PllType tPll0Struct =
{
.bLock = false,
.bCm = false,
.bCmre = false,
.bSten = false,
.eDivH = SCG_ASYNCCLOCKDIV_BY2,
.eDivM = SCG_ASYNCCLOCKDIV_BY2,
.eDivL = SCG_ASYNCCLOCKDIV_BY4,
.u8Prediv = 11U,
.ePstDiv = SCG_PLLPSTDIV_BY2,
.u16Mult = 239U,
.eSrc = SCG_PLLSOURCE_FOSC
};
SCG_EnablePLL(SCG_PLL0, &tPll0Struct);
/* Enable PLL1, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/
/* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/
SCG_PllType tPll1Struct =
{
.bLock = false,
.bCm = false,
.bCmre = false,
.bSten = false,
.eDivH = SCG_ASYNCCLOCKDIV_BY2,
.eDivM = SCG_ASYNCCLOCKDIV_BY2,
.eDivL = SCG_ASYNCCLOCKDIV_BY4,
.u8Prediv = 11U,
.ePstDiv = SCG_PLLPSTDIV_BY2,
.u16Mult = 239U,
.eSrc = SCG_PLLSOURCE_FOSC
};
SCG_EnablePLL(SCG_PLL1, &tPll1Struct);
/* Enable SIRC DIV, DIVH=DIV1(12M), DIVM=DIV1(12M), DIVL=DIV2(6M) */
SCG_SircType tSircStruct =
{
.bLock = false,
.bCm = false,
.bTrEn = false,
.bLpen = false,
.bSten = false,
.eDivH = SCG_ASYNCCLOCKDIV_BY1,
.eDivM = SCG_ASYNCCLOCKDIV_BY1,
.eDivL = SCG_ASYNCCLOCKDIV_BY2,
.u8TrimSrc = 0U
};
SCG_SetSIRC(&tSircStruct);
/* Set core clock source from PLL0, DIV_CORE=DIV1(240M), DIV_BUS=DIV2(120M), DIV_SLOW=DIV4(60M)*/
SCG_ClockCtrlType tClockStruct =
{
.bSysClkMonitor = false,
.eSrc = SCG_CLOCK_SRC_PLL0,
.eDivSlow = SCG_CLOCK_DIV_BY2,
.eDivBus = SCG_CLOCK_DIV_BY2,
.eDivCore = SCG_CLOCK_DIV_BY1
};
SCG_SetClkCtrl(&tClockStruct);
}
/**
* @brief Local PCC Initial
*
*/
static void Bsp_PCC_Init(void)
{
PCC_CtrlType bSP_PCC_Config;
#if UART_USED_INSTANCE2 == STD_ON
/* UART 2 */
bSP_PCC_Config.eClockName = PCC_CLK_FCUART2;
bSP_PCC_Config.bEn = true;
bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
PCC_SetPcc(&bSP_PCC_Config);
#endif /* end for UART_USED_INSTANCE2 == STD_ON */
/* DMA 0 */
bSP_PCC_Config.eClockName = PCC_CLK_DMA0;
bSP_PCC_Config.bEn = true;
bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
PCC_SetPcc(&bSP_PCC_Config);
/* DMAMUX 0 */
bSP_PCC_Config.eClockName = PCC_CLK_DMAMUX0;
bSP_PCC_Config.bEn = true;
bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
PCC_SetPcc(&bSP_PCC_Config);
}
/* ################################################################################## */
/* ################################# Global Functions ############################### */
/**
* @brief General Clock Initial
*
*/
void Bsp_CLOCK_Init(void)
{
SCG_Deinit();
Bsp_SCG_Init();
Bsp_PCC_Init();
}

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#ifndef INCLUDE_BSP_CLOCK_H_
#define INCLUDE_BSP_CLOCK_H_
#include "_driver_header.h"
/**
* @brief General Clock Initial
*
*/
void Bsp_CLOCK_Init(void);
#endif /* INCLUDE_BSP_CLOCK_H_ */

129
APP/FC7240_flash.ld Normal file
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/* Entry Point */
ENTRY(Reset_Handler)
M_VECTOR_RAM_SIZE = 0x0400;
/* Specify the memory areas */
MEMORY
{
ITCM (RW) : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */
SRAM0 (RW) : ORIGIN = 0x21000000, LENGTH = 0x00010000 /* 64KB */
SRAM1 (RW) : ORIGIN = 0x21010000, LENGTH = 0x00008000 /* 32KB */
PFLASH (RW) : ORIGIN = 0x01000000, LENGTH = 0x00200000 /* 2MB */
DFLASH (RW) : ORIGIN = 0x04000000, LENGTH = 0x00020000 /* 128KB */
NVR0 (RW) : ORIGIN = 0x04400000, LENGTH = 0x00004000 /* 16KB */
NVR1 (RW) : ORIGIN = 0x04408000, LENGTH = 0x00004000 /* 16KB */
NVR2 (RW) : ORIGIN = 0x04410000, LENGTH = 0x00002000 /* 8KB */
/* DTCM */
DTCM (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001FA00 /* 128K - 0x600 */
DTCM_STACK (RW) : ORIGIN = 0x2001FA00, LENGTH = 0x00000600 /* 0x600 */
}
/* Define output sections */
SECTIONS
{
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(1024); /* VTOR must be align to 1K */
__vector_table = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector))
__interrupts_end__ = .;
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.init) /* section used in crti.o files */
*(.fini) /* section used in crti.o files */
*(.eh_frame) /* section used in crtbegin.o files */
. = ALIGN(4);
} > PFLASH
.data :
{
__ram_data_start = .;
. = ALIGN(4);
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__ram_data_end = .;
} > DTCM AT > PFLASH
/* Non-cache RAM section with data initialization */
.ncache_data :
{
. = ALIGN(4);
__ram_ncache_data_start = .;
*(.nocacheable_data*)
__ram_ncache_data_end = .;
. = ALIGN(4);
} > SRAM1 AT > PFLASH
.bss(NOLOAD) :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
*(COMMON)
__bss_end = .;
. = ALIGN(4);
} > DTCM
/* Non-cache RAM section with no initialization */
.ncache_bss(NOLOAD) :
{
. = ALIGN(4);
__ncache_bss_start = .;
*(.nocacheable_bss*)
__ncache_bss_end = .;
. = ALIGN(4);
} > SRAM1
__HeapBegin = ORIGIN(DTCM_STACK);
__HeapLimit = ORIGIN(DTCM_STACK) + 0x200 - 8;
__StackLimit = ORIGIN(DTCM_STACK)+0x200;
__StackTop = ORIGIN(DTCM_STACK) + LENGTH(DTCM_STACK) - 8;
__rom_data_start = LOADADDR(.data);
__rom_ncache_data_start = LOADADDR(.ncache_data);
}

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/* USER CODE BEGIN Header */
/*
* FreeRTOS Kernel V10.3.1
* Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
* Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* USER CODE END Header */
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* These parameters and more are described within the 'configuration' section of the
* FreeRTOS API documentation available on the FreeRTOS.org web site.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* Section where include file can be added */
/* USER CODE END Includes */
/* Ensure definitions are only used by the compiler, and not by the assembler. */
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
//#ifndef CMSIS_device_header
//#define CMSIS_device_header "niietcm4.h"
//#define CMSIS_device_header "at32f435_437.h"
//#endif /* CMSIS_device_header */
//#include "niietcm4.h"
//#include "at32f435_437.h"
#define configCHECK_FOR_STACK_OVERFLOW 1
#define configENABLE_FPU 1
#define configENABLE_MPU 0
#define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( 1000 )
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 56 )
#define configMINIMAL_STACK_SIZE ((uint16_t)64)
#define configTOTAL_HEAP_SIZE ((size_t)52000)
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed
if lengths will always be less than the number of bytes in a size_t. */
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH 128
/* CMSIS-RTOS V2 flags */
#define configUSE_OS2_THREAD_SUSPEND_RESUME 1
#define configUSE_OS2_THREAD_ENUMERATE 1
#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1
#define configUSE_OS2_THREAD_FLAGS 1
#define configUSE_OS2_TIMER 1
#define configUSE_OS2_MUTEX 1
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xQueueGetMutexHolder 1
#define INCLUDE_uxTaskGetStackHighWaterMark 1
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_eTaskGetState 1
/*
* The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
* by the application thus the correct define need to be enabled below
*/
#define USE_FreeRTOS_HEAP_4
/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4
#endif
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
/* USER CODE BEGIN 1 */
//#define configASSERT(x) if ((x) == 0) {nvic_system_reset();}
#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
/* USER CODE END 1 */
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
standard names. */
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */
#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
#endif /* FREERTOS_CONFIG_H */

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#ifndef INCLUDE_DRIVER_HEADER_H_
#define INCLUDE_DRIVER_HEADER_H_
#include "fc7xxx_driver_fcuart.h"
#include "fc7xxx_driver_pcc.h"
#include "fc7xxx_driver_port.h"
#include "fc7xxx_driver_scg.h"
#include "fc7xxx_driver_gpio.h"
#include "fc7xxx_driver_dma.h"
#include "interrupt_manager.h"
/* peripheral instance define */
/* UART */
#define UART_USED_INSTANCE2 STD_ON
#define UART_MAX_NUM FCUART_INSTANCE_COUNT
#define UART_RXBUF_SIZE 256U
/* FCUART0 ~ FCUART7 can be used in FC7240, just demo FCUART2 in FC7240-EVB */
#define UART_ACTIVE_INDEX 2
#if UART_ACTIVE_INDEX == 2
#undef UART_USED_INSTANCE2
#define UART_USED_INSTANCE2 STD_ON
#define UART_ACTIVE_INSTANCE UART_INSTANCE_2
/* if use other uart instance in your board,delete follows code */
#else
#error Instance invalid, please select correct index
#endif
#define PCC_CLK_FCUARTn(x) PCC_CLK_FCUART##x
#define _PCC_CLK_FCUART(x) PCC_CLK_FCUARTn(x)
#define PCC_CLK_FCUART _PCC_CLK_FCUART(UART_ACTIVE_INDEX)
#define FCUART_IRQn_HANDLER(x) FCUART##x##_RxTx_IRQHandler
#define _FCUART_IRQ_HANDLER(x) FCUART_IRQn_HANDLER(x)
#define FCUART_IRQ_HANDLER _FCUART_IRQ_HANDLER(UART_ACTIVE_INDEX)
#define FCUART_IRQn_INDEX(x) FCUART##x##_IRQn
#define _FCUART_IRQ_INDEX(x) FCUART_IRQn_INDEX(x)
#define FCUART_IRQ_INDEX _FCUART_IRQ_INDEX(UART_ACTIVE_INDEX)
#endif /* INCLUDE_DRIVER_HEADER_H_ */

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//
// Created by cfif on 22.09.2025.
//
#include "Clock.h"
#include "cmsis_os.h"
_Noreturn void stop() {
while (1) {
asm("nop");
}
}
#define STOP stop();
#if (configCHECK_FOR_STACK_OVERFLOW > 0)
void vApplicationStackOverflowHook(TaskHandle_t xTask, const char *pcTaskName) {
PROCESS_UNUSED_VAR(xTask);
PROCESS_UNUSED_VAR(pcTaskName);
STOP
}
#endif
int main(void)
{
Bsp_CLOCK_Init();
osKernelInitialize();
osKernelStart();
STOP
}

15
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{
"cmake": {
"inc_dirs": [
"./",
"./clock",
"./int"
],
"srcs": [
"./**.c",
"./clock/**.c",
"./int/**.c",
"./**.s"
]
}
}

480
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/* ================================================================================================== */
/* BRIEF : Startup - Startup file for FC7240 */
/* PERIPHERAL : N/A */
/* PLATFORM : Flagchip FC7240 */
/* SOFTWARE VERSION : 0.1.0 */
/* VENDOR : Flagchip */
/* Copyright 2024 Flagchip Semiconductors Co., Ltd. */
/* All Rights Reserved. */
/* ================================================================================================== */
/* ================================================================================================== */
/* Revision History */
/* Version Date Initials CR# Descriptions */
/* --------- ---------- ------------- ---------- --------------- */
/* 0.1.0 2024-01-12 qxw0030 N/A Initial version */
/* ================================================================================================== */
.syntax unified
.arch armv7-m
.extern __StackTop
.extern __StackLimit
/* ================================================================================================== */
/* Set vector table */
/* ================================================================================================== */
.section .isr_vector
.align 2
.globl __isr_vector
/* vector table */
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
.long DMA4_IRQHandler /* DMA channel 4 transfer complete */
.long DMA5_IRQHandler /* DMA channel 5 transfer complete */
.long DMA6_IRQHandler /* DMA channel 6 transfer complete */
.long DMA7_IRQHandler /* DMA channel 7 transfer complete */
.long DMA8_IRQHandler /* DMA channel 8 transfer complete */
.long DMA9_IRQHandler /* DMA channel 9 transfer complete */
.long DMA10_IRQHandler /* DMA channel 10 transfer complete */
.long DMA11_IRQHandler /* DMA channel 11 transfer complete */
.long DMA12_IRQHandler /* DMA channel 12 transfer complete */
.long DMA13_IRQHandler /* DMA channel 13 transfer complete */
.long DMA14_IRQHandler /* DMA channel 14 transfer complete */
.long DMA15_IRQHandler /* DMA channel 15 transfer complete */
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-31 */
.long CPM_IRQHandler /* FPU etc. interrupt */
.long FC_IRQHandler /* FC Command complete */
.long PMC_IRQHandler /* HVD/LVD etc. interrupt */
.long TMU_IRQHandler /* Temperature Monitor Unit interrupt */
.long WDOG0_IRQHandler /* interrupt request out before wdg reset out */
.long WDOG1_IRQHandler /* interrupt request out before wdg reset out */
.long FCSMU0_IRQHandler /* Fault Control and Safety Manage Unit */
.long STCU0_IRQHandler /* Safety Control Unit interrupt */
.long ERM_fault_IRQHandler /* ERM single/double bit error correction */
.long MAM0_IRQHandler /* Matrix Access Monitor interrupt */
.long RGM_Pre_IRQHandler /* RGM pre-reset Interrupt */
.long INTM0_IRQHandler /* INTM alarm interrupt */
.long ISM0_IRQHandler /* ISM0 interrupt */
.long MB_IRQHandler /* Mail Box interrupt */
.long SCG_IRQHandler /* SCG bus interrupt request */
.long CMU0_IRQHandler /* CMU0 interrupt */
.long CMU1_IRQHandler /* CMU1 interrupt */
.long CMU2_IRQHandler /* CMU2 interrupt */
.long CMU3_IRQHandler /* CMU3 interrupt */
.long CMU4_IRQHandler /* CMU4 interrupt */
.long TSTMP0_IRQHandler /* TimerStamp0 interrupt */
.long TSTMP1_IRQHandler /* TimerStamp1 interrupt */
.long CORDIC_IRQHandler /* CORDIC Accelerator interrupt */
.long HSM0_IRQHandler /* HSM error interrupt */
.long FCPIT0_IRQHandler /* FCPIT0 interrupt */
.long RTC_IRQHandler /* RTC alarm or seconds interrupt */
.long AONTIMER_IRQHandler /* AONTIMER interrupt request */
.long SWI_IRQHandler /* Software interrupt */
.long FREQM_IRQHandler /* FREQM interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt request. */
.long ADC1_IRQHandler /* ADC1 interrupt request. */
.long PTIMER0_IRQHandler /* PTIMER0 interrupt */
.long PTIMER1_IRQHandler /* PTIMER1 interrupt */
.long CAN0_IRQHandler /* CAN0 Interrupt */
.long CAN1_IRQHandler /* CAN1 Interrupt */
.long CAN2_IRQHandler /* CAN2 Interrupt */
.long CAN3_IRQHandler /* CAN3 Interrupt */
.long FCIIC0_IRQHandler /* FCIIC0 Interrupt */
.long FCIIC1_IRQHandler /* FCIIC1 Interrupt */
.long FCSPI0_IRQHandler /* FCSPI0 Interrupt */
.long FCSPI1_IRQHandler /* FCSPI1 Interrupt */
.long FCSPI2_IRQHandler /* FCSPI2 Interrupt */
.long FCSPI3_IRQHandler /* FCSPI3 Interrupt */
.long FCSPI4_IRQHandler /* FCSPI4 Interrupt */
.long FCSPI5_IRQHandler /* FCSPI5 Interrupt */
.long FCUART0_RxTx_IRQHandler /* FCUART0 Transmit / Receive Interrupt */
.long FCUART1_RxTx_IRQHandler /* FCUART1 Transmit / Receive Interrupt */
.long FCUART2_RxTx_IRQHandler /* FCUART2 Transmit / Receive Interrupt */
.long FCUART3_RxTx_IRQHandler /* FCUART3 Transmit / Receive Interrupt */
.long FCUART4_RxTx_IRQHandler /* FCUART4 Transmit / Receive Interrupt */
.long FCUART5_RxTx_IRQHandler /* FCUART5 Transmit / Receive Interrupt */
.long FCUART6_RxTx_IRQHandler /* FCUART6 Transmit / Receive Interrupt */
.long FCUART7_RxTx_IRQHandler /* FCUART7 Transmit / Receive Interrupt */
.long FTU0_IRQHandler /* FTU0 all source interrupt */
.long FTU1_IRQHandler /* FTU1 all source interrupt */
.long FTU2_IRQHandler /* FTU2 all source interrupt */
.long FTU3_IRQHandler /* FTU3 all source interrupt */
.long FTU4_IRQHandler /* FTU4 all source interrupt */
.long FTU5_IRQHandler /* FTU5 all source interrupt */
.long FTU6_IRQHandler /* FTU6 all source interrupt */
.long FTU7_IRQHandler /* FTU7 all source interrupt */
.long CMP0_IRQHandler /* CMP0 interrupt request */
.long CMP1_IRQHandler /* CMP1 interrupt request */
.long PORTA_IRQHandler /* Port A pin detect interrupt */
.long PORTB_IRQHandler /* Port B pin detect interrupt */
.long PORTC_IRQHandler /* Port C pin detect interrupt */
.long PORTD_IRQHandler /* Port D pin detect interrupt */
.long PORTE_IRQHandler /* Port E pin detect interrupt */
.long MSC0_IRQHandler /* MSC interrupt */
.long SENT0_IRQHandler /* SENT all interrupt (fast or slow) */
.long TPU0_CH0_7_IRQHandler /* TPU0 CH0-7 interrupt */
.long TPU0_CH8_15_IRQHandler /* TPU0 CH8-15 interrupt */
.long TPU0_CH16_23_IRQHandler /* TPU0 CH16-23 interrupt */
.long TPU0_CH24_31_IRQHandler /* TPU0 CH24-31 interrupt */
.long HSM0_CRYPTO_IRQHandler /* HSM crypto interrupt */
.long DefaultISR /* 108 */
.long DefaultISR /* 109 */
.long DefaultISR /* 110 */
.long DefaultISR /* 111 */
.long DefaultISR /* 112 */
.long DefaultISR /* 113 */
.long DefaultISR /* 114 */
.long DefaultISR /* 115 */
.long DefaultISR /* 116 */
.long DefaultISR /* 117 */
.long DefaultISR /* 118 */
.long DefaultISR /* 119 */
.long DefaultISR /* 120 */
.long DefaultISR /* 121 */
.long DefaultISR /* 122 */
.long DefaultISR /* 123 */
.long DefaultISR /* 124 */
.long DefaultISR /* 125 */
.long DefaultISR /* 126 */
.long DefaultISR /* 127 */
.long DefaultISR /* 128 */
.long DefaultISR /* 129 */
.long DefaultISR /* 130 */
.long DefaultISR /* 131 */
.long DefaultISR /* 132 */
.long DefaultISR /* 133 */
.long DefaultISR /* 134 */
.long DefaultISR /* 135 */
.long DefaultISR /* 136 */
.long DefaultISR /* 137 */
.long DefaultISR /* 138 */
.long DefaultISR /* 139 */
.long DefaultISR /* 140 */
.long DefaultISR /* 141 */
.long DefaultISR /* 142 */
.long DefaultISR /* 143 */
.long DefaultISR /* 144 */
.long DefaultISR /* 145 */
.long DefaultISR /* 146 */
.long DefaultISR /* 147 */
.long DefaultISR /* 148 */
.long DefaultISR /* 149 */
.long DefaultISR /* 150 */
.long DefaultISR /* 151 */
.long DefaultISR /* 152 */
.long DefaultISR /* 153 */
.long DefaultISR /* 154 */
.long DefaultISR /* 155 */
.long DefaultISR /* 156 */
.long DefaultISR /* 157 */
.long DefaultISR /* 158 */
.long DefaultISR /* 159 */
.long DefaultISR /* 160 */
.long DefaultISR /* 161 */
.long DefaultISR /* 162 */
.long DefaultISR /* 163 */
.long DefaultISR /* 164 */
.long DefaultISR /* 165 */
.long DefaultISR /* 166 */
.long DefaultISR /* 167 */
.long DefaultISR /* 168 */
.long DefaultISR /* 169 */
.long DefaultISR /* 170 */
.long DefaultISR /* 171 */
.long DefaultISR /* 172 */
.long DefaultISR /* 173 */
.long DefaultISR /* 174 */
.long DefaultISR /* 175 */
.long DefaultISR /* 176 */
.long DefaultISR /* 177 */
.long DefaultISR /* 178 */
.long DefaultISR /* 179 */
.long DefaultISR /* 180 */
.long DefaultISR /* 181 */
.long DefaultISR /* 182 */
.long DefaultISR /* 183 */
.long DefaultISR /* 184 */
.long DefaultISR /* 185 */
.long DefaultISR /* 186 */
.long DefaultISR /* 187 */
.long DefaultISR /* 188 */
.long DefaultISR /* 189 */
.long DefaultISR /* 190 */
.long DefaultISR /* 191 */
.long DefaultISR /* 192 */
.long DefaultISR /* 193 */
.long DefaultISR /* 194 */
.long DefaultISR /* 195 */
.long DefaultISR /* 196 */
.long DefaultISR /* 197 */
.long DefaultISR /* 198 */
.long DefaultISR /* 199 */
.long DefaultISR /* 200 */
.long DefaultISR /* 201 */
.long DefaultISR /* 202 */
.long DefaultISR /* 203 */
.long DefaultISR /* 204 */
.long DefaultISR /* 205 */
.long DefaultISR /* 206 */
.long DefaultISR /* 207 */
.long DefaultISR /* 208 */
.long DefaultISR /* 209 */
.long DefaultISR /* 210 */
.long DefaultISR /* 211 */
.long DefaultISR /* 212 */
.long DefaultISR /* 213 */
.long DefaultISR /* 214 */
.long DefaultISR /* 215 */
.long DefaultISR /* 216 */
.long DefaultISR /* 217 */
.long DefaultISR /* 218 */
.long DefaultISR /* 219 */
.long DefaultISR /* 220 */
.long DefaultISR /* 221 */
.long DefaultISR /* 222 */
.long DefaultISR /* 223 */
.long DefaultISR /* 224 */
.long DefaultISR /* 225 */
.long DefaultISR /* 226 */
.long DefaultISR /* 227 */
.long DefaultISR /* 228 */
.long DefaultISR /* 229 */
.long DefaultISR /* 230 */
.long DefaultISR /* 231 */
.long DefaultISR /* 232 */
.long DefaultISR /* 233 */
.long DefaultISR /* 234 */
.long DefaultISR /* 235 */
.long DefaultISR /* 236 */
.long DefaultISR /* 237 */
.long DefaultISR /* 238 */
.long DefaultISR /* 239 */
.long DefaultISR /* 240 */
.long DefaultISR /* 241 */
.long DefaultISR /* 242 */
.long DefaultISR /* 243 */
.long DefaultISR /* 244 */
.long DefaultISR /* 245 */
.long DefaultISR /* 246 */
.long DefaultISR /* 247 */
.long DefaultISR /* 248 */
.long DefaultISR /* 249 */
.long DefaultISR /* 250 */
.long DefaultISR /* 251 */
.long DefaultISR /* 252 */
.long DefaultISR /* 253 */
.long DefaultISR /* 254 */
.long 0xFFFFFFFF /* Reserved for user TRIM value */
.size __isr_vector, . - __isr_vector
/**************************************************************/
/************************ set other ***************************/
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
ldr r4,=0
ldr r5,=0
ldr r6,=0
ldr r7,=0
mov r8,r7
mov r9,r7
mov r10,r7
mov r11,r7
mov r12,r7
ldr r0, =0xE000ED08
ldr r1, =__vector_table
str r1, [r0]
/* Initialize the stack pointer */
ldr r0,=__StackTop
mov sp,r0 ; sp=r13
/* Clear Stack */
ldr r2, =__StackLimit
ldr r4, =__StackTop
movs r3, #0
b LoopFillZero_STACK
FillZero_STACK:
str r3, [r2]
adds r2, r2, #4
LoopFillZero_STACK:
cmp r2, r4
bcc FillZero_STACK
/* System Initialization */
ldr r0,=System_Init
blx r0
/* Initialize .data and .bss sections */
ldr r0,=Data_Init
blx r0
cpsie i /* Unmask interrupts */
bl main
JumpToSelf:
b JumpToSelf
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA4_IRQHandler
def_irq_handler DMA5_IRQHandler
def_irq_handler DMA6_IRQHandler
def_irq_handler DMA7_IRQHandler
def_irq_handler DMA8_IRQHandler
def_irq_handler DMA9_IRQHandler
def_irq_handler DMA10_IRQHandler
def_irq_handler DMA11_IRQHandler
def_irq_handler DMA12_IRQHandler
def_irq_handler DMA13_IRQHandler
def_irq_handler DMA14_IRQHandler
def_irq_handler DMA15_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler CPM_IRQHandler
def_irq_handler FC_IRQHandler
def_irq_handler PMC_IRQHandler
def_irq_handler TMU_IRQHandler
def_irq_handler WDOG0_IRQHandler
def_irq_handler WDOG1_IRQHandler
def_irq_handler FCSMU0_IRQHandler
def_irq_handler STCU0_IRQHandler
def_irq_handler ERM_fault_IRQHandler
def_irq_handler MAM0_IRQHandler
def_irq_handler RGM_Pre_IRQHandler
def_irq_handler INTM0_IRQHandler
def_irq_handler ISM0_IRQHandler
def_irq_handler MB_IRQHandler
def_irq_handler SCG_IRQHandler
def_irq_handler CMU0_IRQHandler
def_irq_handler CMU1_IRQHandler
def_irq_handler CMU2_IRQHandler
def_irq_handler CMU3_IRQHandler
def_irq_handler CMU4_IRQHandler
def_irq_handler TSTMP0_IRQHandler
def_irq_handler TSTMP1_IRQHandler
def_irq_handler CORDIC_IRQHandler
def_irq_handler HSM0_IRQHandler
def_irq_handler FCPIT0_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler AONTIMER_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler FREQM_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler PTIMER0_IRQHandler
def_irq_handler PTIMER1_IRQHandler
def_irq_handler CAN0_IRQHandler
def_irq_handler CAN1_IRQHandler
def_irq_handler CAN2_IRQHandler
def_irq_handler CAN3_IRQHandler
def_irq_handler FCIIC0_IRQHandler
def_irq_handler FCIIC1_IRQHandler
def_irq_handler FCSPI0_IRQHandler
def_irq_handler FCSPI1_IRQHandler
def_irq_handler FCSPI2_IRQHandler
def_irq_handler FCSPI3_IRQHandler
def_irq_handler FCSPI4_IRQHandler
def_irq_handler FCSPI5_IRQHandler
def_irq_handler FCUART0_RxTx_IRQHandler
def_irq_handler FCUART1_RxTx_IRQHandler
def_irq_handler FCUART2_RxTx_IRQHandler
def_irq_handler FCUART3_RxTx_IRQHandler
def_irq_handler FCUART4_RxTx_IRQHandler
def_irq_handler FCUART5_RxTx_IRQHandler
def_irq_handler FCUART6_RxTx_IRQHandler
def_irq_handler FCUART7_RxTx_IRQHandler
def_irq_handler FTU0_IRQHandler
def_irq_handler FTU1_IRQHandler
def_irq_handler FTU2_IRQHandler
def_irq_handler FTU3_IRQHandler
def_irq_handler FTU4_IRQHandler
def_irq_handler FTU5_IRQHandler
def_irq_handler FTU6_IRQHandler
def_irq_handler FTU7_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler CMP1_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler MSC0_IRQHandler
def_irq_handler SENT0_IRQHandler
def_irq_handler TPU0_CH0_7_IRQHandler
def_irq_handler TPU0_CH8_15_IRQHandler
def_irq_handler TPU0_CH16_23_IRQHandler
def_irq_handler TPU0_CH24_31_IRQHandler
def_irq_handler HSM0_CRYPTO_IRQHandler
.end

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/**
* @file system_init.c
* @author Flagchip
* @brief interrupt configuration
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author Descriptions
* --------- ---------- ------------ ---------------
* 0.1.0 2024-01-12 Flagchip038 First version for gcc, iar, keil, ghs data init
******************************************************************************** */
#include "system_init.h"
#include "fc7xxx_driver_fpu.h"
static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr);
static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr);
/**
* \brief System Initialization
*
*/
void System_Init(void)
{
/* disable wdog 0 */
*(volatile uint32 *)0x40022004 = 0x08181982;
while (0U == (0x800u & *(volatile uint32 *)0x40022000));
*(volatile uint32 *)0x40022000 = 0x2920;
*(volatile uint32 *)0x40022008 = 0xF000;
while (0U == (0x400u & *(volatile uint32 *)0x40022000));
/* disable wdog 1 */
*(volatile uint32 *)0x40433004 = 0x08181982;
while (0U == (0x800u & *(volatile uint32 *)0x40433000));
*(volatile uint32 *)0x40433000 = 0x2920;
*(volatile uint32 *)0x40433008 = 0xF000;
while (0U == (0x400u & *(volatile uint32 *)0x40433000));
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
FPU_Enable(); /* Enable FPU */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
}
void Data_Init(void)
{
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
extern uint32_t Load$$RW_m_dtcm$$Base;
extern uint32_t Image$$RW_m_dtcm$$Base;
extern uint32_t Image$$RW_m_dtcm$$Limit;
extern uint32_t Image$$RW_m_dtcm$$ZI$$Limit;
extern uint32_t Image$$RW_m_dtcm$$ZI$$Base;
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base;
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Limit;
/* data/bss/heap clear */
data_clear((uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
data_clear((uint32_t)&Image$$RW_m_dtcm$$ZI$$Base, (uint32_t)&Image$$RW_m_dtcm$$ZI$$Limit);
data_clear((uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Base, (uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Limit);
/* data */
data_copy((uint32_t)&Load$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
#elif defined(__GNUC__) || defined(__ghs__)
extern uint32 __rom_data_start[];
extern uint32 __ram_data_start[];
extern uint32 __ram_data_end[];
extern uint32 __bss_start[];
extern uint32 __bss_end[];
extern uint32 __rom_ncache_data_start[];
extern uint32 __ram_ncache_data_start[];
extern uint32 __ram_ncache_data_end[];
extern uint32 __ncache_bss_start[];
extern uint32 __ncache_bss_end[];
/* data clear */
data_clear((uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
data_clear((uint32_t)__bss_start, (uint32_t)__bss_end);
data_clear((uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
data_clear((uint32_t)__ncache_bss_start, (uint32_t)__ncache_bss_end);
/* data copy */
data_copy((uint32_t)__rom_data_start, (uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
data_copy((uint32_t)__rom_ncache_data_start, (uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
#elif defined(__ICCARM__)
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".ncsram"
#pragma section=".ncsram_init"
#pragma section=".bss"
#pragma section="RAM_VECTOR"
#pragma section=".intvec"
data_clear((uint32_t)__section_begin(".bss"), (uint32_t)__section_end(".bss"));
data_copy((uint32_t)__section_begin(".data_init"), (uint32_t)__section_begin(".data"), (uint32_t)__section_end(".data"));
data_copy((uint32_t)__section_begin(".ncsram_init"), (uint32_t)__section_begin(".ncsram"), (uint32_t)__section_end(".ncsram"));
#endif
}
/* to avoid ecc issue, FC7240 clear ram with 64bits once after power on reset */
static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr)
{
/* 64 bits align */
uint32_t u32AlignStart = u32StartAddr & 0xFFFFFFF8;
uint32_t u32AlignEnd = (u32EndAddr - u32AlignStart);
volatile uint64_t *pData = (uint64_t *)u32AlignStart;
/* 32 word Align */
uint32_t u32LeftCount = u32AlignEnd & 0x1Fu;
u32AlignEnd = u32EndAddr - u32LeftCount;
while ((uint32_t)pData < u32AlignEnd)
{
*pData++ = 0u;
*pData++ = 0u;
*pData++ = 0u;
*pData++ = 0u;
}
while ((uint32_t)pData < u32EndAddr)
{
*pData++ = 0u;
}
}
static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr)
{
uint32_t *pSource = (uint32_t *)u32SourceAddr;
uint32_t *pDest = (uint32_t *)u32DestAddr;
while ((uint32_t)pDest < u32DestEndAddr)
{
*pDest = *pSource;
pDest++;
pSource++;
}
}

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APP/system_init.h Normal file
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/**
* @file system_init.h
* @author Flagchip
* @brief interrupt configuration
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#if !defined(SYSTEM_INIT_H)
#define SYSTEM_INIT_H
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
#include "device_header.h"
void System_Init(void);
void Data_Init(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* SYSTEM_INIT_H */

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CMakeLists.txt Normal file
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@ -0,0 +1,88 @@
#-- Service --------------------------------------------------------------------
SET(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake)
ENABLE_LANGUAGE(ASM)
CMAKE_MINIMUM_REQUIRED(VERSION 3.8.0)
set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0")
set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0")
IF (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_BINARY_DIR})
MESSAGE(
FATAL_ERROR
"In-source builds not allowed.
Please make a new directory (called a build directory) and run CMake from there.
You may need to remove CMakeCache.txt."
)
ENDIF ()
SET(CMAKE_EXPORT_COMPILE_COMMANDS ON)
#-- Project config -------------------------------------------------------------
PROJECT(HVAC) # Project name
SET(HARDWARE_REVISION 1.0.0) #
SET(VERSION \"1.0.0_HVAC\") #
SET(VERSION_INTERFACE \"1.0_INTERFACE\") #
SET(HARDWARE_USER_NAME "HVAC")
#SET(VECT_TAB_OFFSET "0x100000")
SET(VECT_TAB_OFFSET "0x00000")
SET(HEXT_VALUE "8000000")
SET(PLL_NS "125")
#-- Defines --------------------------------------------------------------------
#ADD_DEFINITIONS(-DSET_ACCESS_PROTECTION) # Выставление защиты доступа к памяти
#ADD_DEFINITIONS(-DSET_WDT) # Выставление сторожевого таймера
ADD_DEFINITIONS(-DFIRMWARE_VERSION=${VERSION})
ADD_DEFINITIONS(-DHARDWARE_REVISION=\"${HARDWARE_REVISION}\")
ADD_DEFINITIONS(-DFIRMWARE_INTERFACE_VERSION=${VERSION_INTERFACE})
ADD_DEFINITIONS(-DUSING_OS_FREERTOS)
ADD_DEFINITIONS(-DVECT_TAB_OFFSET=${VECT_TAB_OFFSET})
ADD_DEFINITIONS(-DHEXT_VALUE=${HEXT_VALUE})
ADD_DEFINITIONS(-DCMSIS_device_header="interrupt_manager.h")
ADD_DEFINITIONS(-DFLASH_PAGE_SIZE=2048)
ADD_DEFINITIONS(-DCOM_INT_BIG_BUFFERS)
ADD_DEFINITIONS(-DVARIABLE_TABLE_WITH_ID)
ADD_DEFINITIONS(-DLFS_THREADSAFE=1)
ADD_DEFINITIONS(-DHALF_DUPLEX_NO_DELAY=1)
ADD_DEFINITIONS(-DACCESS_ADC=1)
ADD_DEFINITIONS(-DACCESS_RTC=1)
ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_CLEAR=1)
#ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_WRITE_SECTORS=1) # Включение записи по секторам (Тестово, закоментированно)
#-- Project paths, Include dirs, Sources list ---------------------------------
#ADD_FILES(SOURCES "MODULES/DeviceStartup_ARTERY_AT32F437ZMT7/ld/startup_at32f435_437.s")
include(modular.cmake)
#-- Options --------------------------------------------------------------------
IF (PRINTF_FLOAT STREQUAL "1")
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_printf_float")
ENDIF ()
IF (SCANF_FLOAT STREQUAL "1")
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_scanf_float")
ENDIF ()
#-- Linker script --------------------------------------------------------------
SET(LDSCRIPT ${CMAKE_SOURCE_DIR}/APP/FC7240_flash.ld)
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${LDSCRIPT} -Wl,-Map=${CMAKE_BINARY_DIR}/${PROJECT_NAME}.map -Wl,--print-memory-usage")
#-- Random BuildId Generation ------------------------------------------------------------
SET(RANDOM_BUILD_ID_GEN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake)
add_custom_target(GEN_RANDOM_BUILD_ID)
ADD_CUSTOM_COMMAND(TARGET GEN_RANDOM_BUILD_ID POST_BUILD
COMMAND ${CMAKE_COMMAND} -P ${RANDOM_BUILD_ID_GEN_FILE})
#-- Project linking ------------------------------------------------------------
ADD_EXECUTABLE(${PROJECT_NAME}.elf ${SOURCES})
TARGET_LINK_LIBRARIES(${PROJECT_NAME}.elf)
add_dependencies(${PROJECT_NAME}.elf GEN_RANDOM_BUILD_ID)
#-- Custom commands ------------------------------------------------------------
ADD_CUSTOM_COMMAND(TARGET ${PROJECT_NAME}.elf POST_BUILD
COMMAND ${CMAKE_OBJCOPY} "-Oihex" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.hex
COMMAND ${CMAKE_OBJCOPY} "-Obinary" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin
# COMMAND ${CMAKE_OBJDUMP} "-DS" ${PROJECT_NAME}.elf > ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.dasm
COMMAND ${CMAKE_SIZE} ${PROJECT_NAME}.elf)

65
modular.json Normal file
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@ -0,0 +1,65 @@
{
"dep": [
{
"type": "git",
"provider": "HVAC_M7",
"repo": "CmakeConfig_GCC_CortexM7"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "CmakeConfig_RandomBuildIdGenerator"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "FreeRTOSHeap4_CM7_CMSIS"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "SystemDelay_CMSIS_RTOS"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "SystemSync_CMSIS_RTOS"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "SystemDelayInterface"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "CmsisRtosThreadUtils"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "PeripheralDriver_Flagchip_FC7240"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "Device_Flagchip_FC7240"
},
{
"type": "git",
"provider": "HVAC_M7",
"repo": "HwA_Flagchip_FC7240"
},
{
"type": "local",
"dir": "APP"
}
]
}