Обновление после командировки 29.06.2026
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@ -238,13 +238,14 @@ static void Bsp_PCC_Init(void) {
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PCC_SetPcc(&bSP_PCC_Config);
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// CRC
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bSP_PCC_Config.eClockName = PCC_CLK_CRC0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_PLL0DIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// PCC_CLK_WKU0
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bSP_PCC_Config.eClockName = PCC_CLK_WKU0;
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bSP_PCC_Config.bEn = true;
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@ -76,7 +76,7 @@ extern uint32_t SystemCoreClock;
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#define configTICK_RATE_HZ ((TickType_t)1000)
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#define configMAX_PRIORITIES ( 56 )
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#define configMINIMAL_STACK_SIZE ((uint16_t)64)
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#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024)
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#define configTOTAL_HEAP_SIZE ((size_t)20 * 1024)
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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@ -44,7 +44,7 @@ int printf(const char *format, ...) {
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// buffer_printf[ret - 1] = ' ';
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// }
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LoggerCnInfo(LOGGER, LOG_SIGN, buffer_printf, ret)
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// LoggerCnInfo(LOGGER, LOG_SIGN, buffer_printf, ret)
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}
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return ret;
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@ -24,71 +24,20 @@
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static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr);
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static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr);
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#define REG_VAL(addr) (*(volatile uint32 *)(addr))
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#define REG_VAL_OFF(addr,offset) (*(volatile uint32 *)((addr)+(offset)))
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#define WDOG0_BASE_ADDR 0x40022000U
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#define WDOG1_BASE_ADDR 0x40433000U
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#define SMC_STANDBY_CFG_ADDR 0x40045010U
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#define SCM_BASE_ADDR 0x40072000U
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#define RGM_BASE_ADDR 0x40046000U
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#define PCC_STCU_ADDR 0x400241FCU
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#define STCU_BASE_ADDR 0x4007F000U
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#define DWT_CYCCNT_ADDR 0xE0001004U
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#define DEMCR_ADDR 0xE000EDFCU
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#define CPACR_ADDR 0xE000ED88U
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static void wdog_disable(uint32 wdog_base)
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{
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uint32 u32ttt = 128;
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uint32 u32First = 1;
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/* if it is not first time configure wdog, unlock status only pending for 128 bus clock */
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do {
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/* check unlock active */
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if (0U == (0x800u & REG_VAL(wdog_base)))
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{
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/* if unlock statue turn to 0, means not first time configuring wdog */
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u32First = 0;
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break;
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}
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} while (u32ttt--);
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if (u32First == 0U)
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{
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/* only unlock=0, reconfig=1, can unlock wdog*/
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/* waiting reconfiguration successful */
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while (0U == (0x400u & REG_VAL(wdog_base)));
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/* unlock wdog */
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REG_VAL_OFF(wdog_base, 4) = 0x08181982;
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/* waiting unlock active */
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while (0U == (0x800u & REG_VAL(wdog_base)));
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}
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REG_VAL(wdog_base) = 0x2920;
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REG_VAL_OFF(wdog_base, 8) = 0xF000;
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/* waiting reconfiguration successful */
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while (0U == (0x400u & REG_VAL(wdog_base)));
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}
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/**
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* \brief System Initialization
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*
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*/
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void System_Init(void)
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{
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// disable wdog 0
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/* disable wdog 0 */
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*(volatile uint32 *)0x40022004 = 0x08181982;
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while (0U == (0x800u & *(volatile uint32 *)0x40022000));
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*(volatile uint32 *)0x40022000 = 0x2920;
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*(volatile uint32 *)0x40022008 = 0xF000;
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while (0U == (0x400u & *(volatile uint32 *)0x40022000));
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// disable wdog 1
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/* disable wdog 1 */
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*(volatile uint32 *)0x40433004 = 0x08181982;
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while (0U == (0x800u & *(volatile uint32 *)0x40433000));
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*(volatile uint32 *)0x40433000 = 0x2920;
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@ -96,9 +45,8 @@ void System_Init(void)
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while (0U == (0x400u & *(volatile uint32 *)0x40433000));
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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FPU_Enable(); // Enable FPU
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#endif
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FPU_Enable(); /* Enable FPU */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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}
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