133 lines
4.0 KiB
C
133 lines
4.0 KiB
C
//
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// Created by cfif on 22.09.2025.
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//
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#include "Clock.h"
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#include "fc7xxx_driver_fmc.h"
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#include "InternalFlashPage.h"
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#include "memory.h"
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#define _BootloaderSize (64 * 1024)
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#define _BootloaderBegin 0x01000000
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#define _FirmwareMainBegin (_BootloaderBegin + _BootloaderSize)
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/*
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static void swap_bank(uint8_t eBank)
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{
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uint32_t u32RegVal = FMC1->OTA_CTRL[1];
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if (u32RegVal == 0U) { // Аппаратный OTA не включен
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// 1. Снимаем блокировку OTA (бит 6 = 0)
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u32RegVal &= ~(1u << 6u);
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// 2. Устанавливаем активный банк (бит 5)
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if (0 == eBank) {
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u32RegVal &= ~(1u << 5u); // Банк 0
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} else {
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u32RegVal |= (1u << 5u); // Банк 1
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}
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// 3. Устанавливаем OTA_EN = 0xA (биты 4-0)
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// НЕЛЬЗЯ использовать & ~0x1F, потому что это сбросит бит 5!
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u32RegVal = (u32RegVal & ~0x1F) | 0xA; // ← ОСТАВЛЯЕМ БИТ 5
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// 4. Записываем обратно
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FMC1->OTA_CTRL[1] = u32RegVal;
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}
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}
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*/
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#define FMC_FB_FPELCK_COUNT_V2 3
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#define FMC_FB_CPELCK_COUNT_V2 2
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#define FMC_OTA_VER_LOC_COUNT_V2 2
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#define FMC_OTA_ACT_VER_COUNT_V2 2
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typedef struct {
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__IO uint32_t FAPC0 ; /* Flash Access Port Control Register0, offset: 0x0 */
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__IO uint32_t FAPC1 ; /* Flash Access Port Control Register1, offset: 0x4 */
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uint8_t RESERVED_0[8];
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__IO uint32_t FEEC ; /* Flash ECC Error Control Register, offset: 0x10 */
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uint8_t RESERVED_1[748];
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__IO uint32_t FPESA_L ; /* Flash Program Erase Start Address Logical Register, offset: 0x300 */
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__I uint32_t FPESA_P ; /* Flash Program Erase Start Address Physical Register, offset: 0x304 */
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uint8_t RESERVED_2[56];
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__IO uint32_t FB_FPELCK[FMC_FB_FPELCK_COUNT_V2]; /* Flash Block n Fine Program Erase Lock Register, offset: 0x340 */
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uint8_t RESERVED_3[12];
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__IO uint32_t FN_FPELCK ; /* Flash NVR Fine Program Erase Lock Register, offset: 0x358 */
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__IO uint32_t FB_CPELCK[FMC_FB_CPELCK_COUNT_V2]; /* Flash Block n Coarse Program Erase Lock Register, offset: 0x35c */
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uint8_t RESERVED_4[412];
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__IO uint32_t OTA_CTRL ; /* OTA Control Register, offset: 0x500 */
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uint8_t RESERVED_5[4];
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__I uint32_t OTA_VER_LOC[FMC_OTA_VER_LOC_COUNT_V2]; /* OTA Version Location Register, offset: 0x508 */
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__I uint32_t OTA_ACT_VER[FMC_OTA_ACT_VER_COUNT_V2]; /* OTA Active Version Register, offset: 0x510 */
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} FMC_Type_V2;
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#define FMC0_BASE_V2 (0x4001e000u)
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#define FMC0_V2 ((FMC_Type_V2 *)FMC0_BASE_V2)
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static void swap_bank(uint8_t eBank)
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{
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if (0U == (FMC0_V2->OTA_CTRL))
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{
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if (0 == eBank)
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{
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FMC0_V2->OTA_CTRL &= (~(1u << 5u));
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}
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else
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{
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FMC0_V2->OTA_CTRL |= (1u << 5u);
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}
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FMC0_V2->OTA_CTRL |= 0xA;
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}
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}
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void DefaultISR(void) {
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}
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static void Boot2App(void)
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{
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uint32_t u32StackAddr = *((uint32_t*)((uint32_t)_FirmwareMainBegin));
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uint32_t u32ResetAddr = *((uint32_t*)(((uint32_t)_FirmwareMainBegin) + 4U));
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SCB->VTOR = (uint32_t)_FirmwareMainBegin;
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__asm volatile("MOV R0, %0\n"
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"MOV SP, R0\n"
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"MOV R0, %1\n"
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"MOV PC, R0"
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:
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: "r"(u32StackAddr), "r"(u32ResetAddr)
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: "memory", "r0"
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);
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}
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uint64_t NumberBank = 0;
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int main(void) {
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Bsp_CLOCK_Init();
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D_sInternalFlashPage_Read(0x04000000, 0, (uint8_t *)&NumberBank, 8);
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/*
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uint8_t ver0[30];
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uint8_t ver1[30];
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memcpy(ver0, (uint8_t *)(0x01000000 + 0xFF00), 30);
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swap_bank(1);
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memcpy(ver1, (uint8_t *)(0x01000000 + 0xFF00), 30);
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*/
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if (NumberBank == 1) {
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swap_bank(0);
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} else {
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swap_bank(0);
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}
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Boot2App();
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}
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