213 lines
6.8 KiB
C
213 lines
6.8 KiB
C
/**
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* @file system_init.c
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* @author Flagchip
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* @brief interrupt configuration
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Author Descriptions
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* --------- ---------- ------------ ---------------
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* 0.1.0 2024-01-12 Flagchip038 First version for gcc, iar, keil, ghs data init
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******************************************************************************** */
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#include "system_init.h"
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#include "fc7xxx_driver_fpu.h"
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static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr);
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static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr);
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#define REG_VAL(addr) (*(volatile uint32 *)(addr))
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#define REG_VAL_OFF(addr,offset) (*(volatile uint32 *)((addr)+(offset)))
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#define WDOG0_BASE_ADDR 0x40022000U
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#define WDOG1_BASE_ADDR 0x40433000U
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#define SMC_STANDBY_CFG_ADDR 0x40045010U
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#define SCM_BASE_ADDR 0x40072000U
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#define RGM_BASE_ADDR 0x40046000U
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#define PCC_STCU_ADDR 0x400241FCU
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#define STCU_BASE_ADDR 0x4007F000U
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#define DWT_CYCCNT_ADDR 0xE0001004U
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#define DEMCR_ADDR 0xE000EDFCU
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#define CPACR_ADDR 0xE000ED88U
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static void wdog_disable(uint32 wdog_base)
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{
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uint32 u32ttt = 128;
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uint32 u32First = 1;
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/* if it is not first time configure wdog, unlock status only pending for 128 bus clock */
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do {
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/* check unlock active */
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if (0U == (0x800u & REG_VAL(wdog_base)))
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{
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/* if unlock statue turn to 0, means not first time configuring wdog */
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u32First = 0;
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break;
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}
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} while (u32ttt--);
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if (u32First == 0U)
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{
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/* only unlock=0, reconfig=1, can unlock wdog*/
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/* waiting reconfiguration successful */
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while (0U == (0x400u & REG_VAL(wdog_base)));
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/* unlock wdog */
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REG_VAL_OFF(wdog_base, 4) = 0x08181982;
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/* waiting unlock active */
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while (0U == (0x800u & REG_VAL(wdog_base)));
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}
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REG_VAL(wdog_base) = 0x2920;
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REG_VAL_OFF(wdog_base, 8) = 0xF000;
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/* waiting reconfiguration successful */
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while (0U == (0x400u & REG_VAL(wdog_base)));
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}
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/**
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* \brief System Initialization
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*
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*/
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void System_Init(void)
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{
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// disable wdog 0
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*(volatile uint32 *)0x40022004 = 0x08181982;
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while (0U == (0x800u & *(volatile uint32 *)0x40022000));
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*(volatile uint32 *)0x40022000 = 0x2920;
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*(volatile uint32 *)0x40022008 = 0xF000;
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while (0U == (0x400u & *(volatile uint32 *)0x40022000));
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// disable wdog 1
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*(volatile uint32 *)0x40433004 = 0x08181982;
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while (0U == (0x800u & *(volatile uint32 *)0x40433000));
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*(volatile uint32 *)0x40433000 = 0x2920;
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*(volatile uint32 *)0x40433008 = 0xF000;
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while (0U == (0x400u & *(volatile uint32 *)0x40433000));
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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FPU_Enable(); // Enable FPU
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#endif
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}
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void Data_Init(void)
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{
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#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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extern uint32_t Load$$RW_m_dtcm$$Base;
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extern uint32_t Image$$RW_m_dtcm$$Base;
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extern uint32_t Image$$RW_m_dtcm$$Limit;
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extern uint32_t Image$$RW_m_dtcm$$ZI$$Limit;
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extern uint32_t Image$$RW_m_dtcm$$ZI$$Base;
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extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base;
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extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Limit;
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/* data/bss/heap clear */
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data_clear((uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
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data_clear((uint32_t)&Image$$RW_m_dtcm$$ZI$$Base, (uint32_t)&Image$$RW_m_dtcm$$ZI$$Limit);
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data_clear((uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Base, (uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Limit);
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/* data */
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data_copy((uint32_t)&Load$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
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#elif defined(__GNUC__) || defined(__ghs__)
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extern uint32 __rom_data_start[];
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extern uint32 __ram_data_start[];
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extern uint32 __ram_data_end[];
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extern uint32 __bss_start[];
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extern uint32 __bss_end[];
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extern uint32 __rom_ncache_data_start[];
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extern uint32 __ram_ncache_data_start[];
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extern uint32 __ram_ncache_data_end[];
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extern uint32 __ncache_bss_start[];
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extern uint32 __ncache_bss_end[];
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extern uint32_t __itcm_start[];
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extern uint32_t __itcm_end[];
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extern uint32_t __xcp_start[];
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extern uint32_t __xcp_end[];
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/* data clear */
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data_clear((uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
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data_clear((uint32_t)__bss_start, (uint32_t)__bss_end);
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data_clear((uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
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data_clear((uint32_t)__ncache_bss_start, (uint32_t)__ncache_bss_end);
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data_clear((uint32_t)__itcm_start, (uint32_t)__itcm_end);
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data_clear((uint32_t)__xcp_start, (uint32_t)__xcp_end);
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/* data copy */
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data_copy((uint32_t)__rom_data_start, (uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
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data_copy((uint32_t)__rom_ncache_data_start, (uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
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#elif defined(__ICCARM__)
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#pragma section=".data"
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#pragma section=".data_init"
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#pragma section=".ncsram"
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#pragma section=".ncsram_init"
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#pragma section=".bss"
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#pragma section="RAM_VECTOR"
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#pragma section=".intvec"
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data_clear((uint32_t)__section_begin(".bss"), (uint32_t)__section_end(".bss"));
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data_copy((uint32_t)__section_begin(".data_init"), (uint32_t)__section_begin(".data"), (uint32_t)__section_end(".data"));
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data_copy((uint32_t)__section_begin(".ncsram_init"), (uint32_t)__section_begin(".ncsram"), (uint32_t)__section_end(".ncsram"));
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#endif
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}
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/* to avoid ecc issue, FC7240 clear ram with 64bits once after power on reset */
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static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr)
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{
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/* 64 bits align */
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uint32_t u32AlignStart = u32StartAddr & 0xFFFFFFF8;
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uint32_t u32AlignEnd = (u32EndAddr - u32AlignStart);
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volatile uint64_t *pData = (uint64_t *)u32AlignStart;
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/* 32 word Align */
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uint32_t u32LeftCount = u32AlignEnd & 0x1Fu;
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u32AlignEnd = u32EndAddr - u32LeftCount;
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while ((uint32_t)pData < u32AlignEnd)
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{
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*pData++ = 0u;
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*pData++ = 0u;
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*pData++ = 0u;
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*pData++ = 0u;
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}
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while ((uint32_t)pData < u32EndAddr)
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{
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*pData++ = 0u;
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}
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}
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static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr)
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{
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uint32_t *pSource = (uint32_t *)u32SourceAddr;
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uint32_t *pDest = (uint32_t *)u32DestAddr;
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while ((uint32_t)pDest < u32DestEndAddr)
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{
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*pDest = *pSource;
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pDest++;
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pSource++;
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}
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}
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