HVAC_M7
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HVAC_BOOT_OTA_M7
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Обновление

This commit is contained in:
cfif 2026-06-20 17:39:17 +03:00
parent 53885de2bc
commit eba38904bf
1 changed files with 0 additions and 60 deletions
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60
APP/system_init.c
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@ -80,65 +80,6 @@ static void wdog_disable(uint32 wdog_base)
*/ */
void System_Init(void) void System_Init(void)
{ {
/* only errata in debug mode */
/* if (0 != (0x01 & REG_VAL(0xE000EDF0))) */
{
/* --------------- Errata MCU debug Issue 1 lockstep lost start -------------- */
/* clear dwt counter to handle cpu0 lockstep error under debug */
REG_VAL(DEMCR_ADDR) = 0x01000000u; /* open TRCENA */
REG_VAL(DWT_CYCCNT_ADDR) = 0x0u; /* Clear DWT_CYCCNT */
/* ----------------- Errata MCU debug Issue 1 lockstep lost end -------------- */
}
uint32 u32ResetType = (REG_VAL_OFF(RGM_BASE_ADDR, 8));
/* external and power domain reset like bist/pin/por/jtag/sysap need to clear all ram */
if (0U != (u32ResetType & 0x89C3))
{
/* --------- Errata MCU debug Issue 2 for ITCM error hardfault start --------- */
/* ------------------ NVR must set ITCM initial auto enable ------------------ */
/* disable AXBS/CPU0 ECC */
REG_VAL_OFF(SCM_BASE_ADDR, 0x20) = 0x02AA8A2A;
REG_VAL_OFF(SCM_BASE_ADDR, 0x24) = 0x00002822;
REG_VAL_OFF(SCM_BASE_ADDR, 0x28) = 0x00000AAA;
/* STCU PCC Enable*/
REG_VAL(PCC_STCU_ADDR) = 0x00800000;
/* clear all itcm dtcm sram*/
REG_VAL_OFF(STCU_BASE_ADDR, 0x50) = 0xFFFFFFFF; /* reserved bit write non-effect */
if (0x01U == (u32ResetType & 0x01U)) /* only skip ram for standby wakeup */
{
/* Get SMC standby mode */
uint32 standbymode = REG_VAL(SMC_STANDBY_CFG_ADDR) & 0x03U;
/* config skip ram for special standby */
REG_VAL_OFF(STCU_BASE_ADDR, 0x48) = 1u | (standbymode << 16);
}
else
{
REG_VAL_OFF(STCU_BASE_ADDR, 0x48) = 1u;
}
while (0 == ((REG_VAL_OFF(STCU_BASE_ADDR, 0x4C)) & 2u)); /* wait busy */
while (0 == ((REG_VAL_OFF(STCU_BASE_ADDR, 0x4C)) & 1u)); /* wait done */
}
/* enable AXBS/CPU0 ECC after every reset */
REG_VAL_OFF(SCM_BASE_ADDR, 0x20) = 0x03FFCF3F;
REG_VAL_OFF(SCM_BASE_ADDR, 0x24) = 0x00003D33;
REG_VAL_OFF(SCM_BASE_ADDR, 0x28) = 0x00000FFF;
/* disable wdog 0 */
wdog_disable(WDOG0_BASE_ADDR);
/* disable wdog 1 */
wdog_disable(WDOG1_BASE_ADDR);
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
REG_VAL(CPACR_ADDR) = 0x00F00000u; /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
/*
// disable wdog 0 // disable wdog 0
*(volatile uint32 *)0x40022004 = 0x08181982; *(volatile uint32 *)0x40022004 = 0x08181982;
while (0U == (0x800u & *(volatile uint32 *)0x40022000)); while (0U == (0x800u & *(volatile uint32 *)0x40022000));
@ -156,7 +97,6 @@ void System_Init(void)
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
FPU_Enable(); // Enable FPU FPU_Enable(); // Enable FPU
#endif #endif
*/
} }
void Data_Init(void) void Data_Init(void)