diff --git a/APP/main.c b/APP/main.c
index 6b4d962..91b12f4 100644
--- a/APP/main.c
+++ b/APP/main.c
@@ -47,39 +47,34 @@ static void swap_bank(uint8_t eBank)
 
 typedef struct {
 
-    __IO uint32_t FAPC0                         ; /* Flash Access Port Control Register0, offset: 0x0 */
-    __IO uint32_t FAPC1                         ; /* Flash Access Port Control Register1, offset: 0x4 */
-    uint8_t  RESERVED_0[8];
-    __IO uint32_t FEEC                          ; /* Flash ECC Error Control Register, offset: 0x10 */
-    uint8_t  RESERVED_1[748];
-    __IO uint32_t FPESA_L                       ; /* Flash Program Erase Start Address Logical Register, offset: 0x300 */
-    __I  uint32_t FPESA_P                       ; /* Flash Program Erase Start Address Physical Register, offset: 0x304 */
-    uint8_t  RESERVED_2[56];
+    __IO uint32_t FAPC0; /* Flash Access Port Control Register0, offset: 0x0 */
+    __IO uint32_t FAPC1; /* Flash Access Port Control Register1, offset: 0x4 */
+    uint8_t RESERVED_0[8];
+    __IO uint32_t FEEC; /* Flash ECC Error Control Register, offset: 0x10 */
+    uint8_t RESERVED_1[748];
+    __IO uint32_t FPESA_L; /* Flash Program Erase Start Address Logical Register, offset: 0x300 */
+    __I uint32_t FPESA_P; /* Flash Program Erase Start Address Physical Register, offset: 0x304 */
+    uint8_t RESERVED_2[56];
     __IO uint32_t FB_FPELCK[FMC_FB_FPELCK_COUNT_V2]; /* Flash Block n Fine Program Erase Lock Register, offset: 0x340 */
-    uint8_t  RESERVED_3[12];
-    __IO uint32_t FN_FPELCK                     ; /* Flash NVR Fine Program Erase Lock Register, offset: 0x358 */
+    uint8_t RESERVED_3[12];
+    __IO uint32_t FN_FPELCK; /* Flash NVR Fine Program Erase Lock Register, offset: 0x358 */
     __IO uint32_t FB_CPELCK[FMC_FB_CPELCK_COUNT_V2]; /* Flash Block n Coarse Program Erase Lock Register, offset: 0x35c */
-    uint8_t  RESERVED_4[412];
-    __IO uint32_t OTA_CTRL                      ; /* OTA Control Register, offset: 0x500 */
-    uint8_t  RESERVED_5[4];
-    __I  uint32_t OTA_VER_LOC[FMC_OTA_VER_LOC_COUNT_V2]; /* OTA Version Location Register, offset: 0x508 */
-    __I  uint32_t OTA_ACT_VER[FMC_OTA_ACT_VER_COUNT_V2]; /* OTA Active Version Register, offset: 0x510 */
+    uint8_t RESERVED_4[412];
+    __IO uint32_t OTA_CTRL; /* OTA Control Register, offset: 0x500 */
+    uint8_t RESERVED_5[4];
+    __I uint32_t OTA_VER_LOC[FMC_OTA_VER_LOC_COUNT_V2]; /* OTA Version Location Register, offset: 0x508 */
+    __I uint32_t OTA_ACT_VER[FMC_OTA_ACT_VER_COUNT_V2]; /* OTA Active Version Register, offset: 0x510 */
 
 } FMC_Type_V2;
 
 #define FMC0_BASE_V2                                 (0x4001e000u)
 #define FMC0_V2                                      ((FMC_Type_V2 *)FMC0_BASE_V2)
 
-static void swap_bank(uint8_t eBank)
-{
-    if (0U == (FMC0_V2->OTA_CTRL))
-    {
-        if (0 == eBank)
-        {
+static void swap_bank(uint8_t eBank) {
+    if (0U == (FMC0_V2->OTA_CTRL)) {
+        if (0 == eBank) {
             FMC0_V2->OTA_CTRL &= (~(1u << 5u));
-        }
-        else
-        {
+        } else {
             FMC0_V2->OTA_CTRL |= (1u << 5u);
         }
         FMC0_V2->OTA_CTRL |= 0xA;
@@ -87,9 +82,8 @@ static void swap_bank(uint8_t eBank)
 }
 
 
-
 void DefaultISR(void) {
-    *((volatile unsigned int *)(0x40014030)) = 0x00000A55;
+//    *((volatile unsigned int *)(0x40014030)) = 0x00000A55;
 }
 
 
@@ -99,11 +93,10 @@ void DefaultISR(void) {
 //void xPortPendSVHandler(void) __attribute__((naked));
 //void vPortSVCHandler(void) __attribute__((naked));
 
-static void Boot2App(void)
-{
-    uint32_t u32StackAddr = *((uint32_t*)((uint32_t)_FirmwareMainBegin));
-    uint32_t u32ResetAddr = *((uint32_t*)(((uint32_t)_FirmwareMainBegin) + 4U));
-    SCB->VTOR = (uint32_t)_FirmwareMainBegin;
+static void Boot2App(void) {
+    uint32_t u32StackAddr = *((uint32_t *) ((uint32_t) _FirmwareMainBegin));
+    uint32_t u32ResetAddr = *((uint32_t *) (((uint32_t) _FirmwareMainBegin) + 4U));
+    SCB->VTOR = (uint32_t) _FirmwareMainBegin;
     __asm volatile("MOV     R0, %0\n"
                    "MOV     SP, R0\n"
                    "MOV     R0, %1\n"
@@ -114,41 +107,33 @@ static void Boot2App(void)
             );
 }
 
+
+bool is_jtag_debug_active(void) {
+    // Проверяем, включена ли отладка
+    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) != 0;
+}
+
 uint64_t NumberBank = 0;
 
 int main(void) {
     Bsp_CLOCK_Init();
 
-
-//    RGM_ResetEventType eReset  = RGM_HWA_ReadAllResetFlagBeforePOR();
-
-
-/*
-    if (RGM_SRS_JTAG_MASK == (RGM->SRS & RGM_SRS_JTAG_MASK)) {
-        D_bInternalFlashPage_Clear(0x04000000, NULL,  NULL);
-        NumberBank = 0;
-    } else {
-        D_sInternalFlashPage_Read(0x04000000, 0, (uint8_t * ) & NumberBank, 8);
+    if (is_jtag_debug_active()) {
+        D_bInternalFlashPage_Clear(0x04000000, NULL, NULL);
     }
-*/
-/*
-    uint8_t ver0[30];
-    uint8_t ver1[30];
 
-    memcpy(ver0, (uint8_t *)(0x01000000 + 0xFF00), 30);
-    swap_bank(1);
-    memcpy(ver1, (uint8_t *)(0x01000000 + 0xFF00), 30);
-*/
-    D_sInternalFlashPage_Read(0x04000000, 0, (uint8_t * ) & NumberBank, 8);
+    NumberBank = (*(__IO uint64_t *) (0x04000000));
 
-    if (NumberBank == 1) {
+    if (NumberBank == 0x1122334455667788) {
         swap_bank(1);
     } else {
         swap_bank(0);
     }
+//    swap_bank(0);
 
 
-    BootFastJumpToAddress(_FirmwareMainBegin);
-//    Boot2App();
+//    BootJumpToAddress(_FirmwareMainBegin);
+//    BootFastJumpToAddress(_FirmwareMainBegin);
+    Boot2App();
 
 }
diff --git a/CMakeLists.txt b/CMakeLists.txt
index f56a7c1..38fba86 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -3,8 +3,8 @@ SET(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_GCC_CortexM7/gc
 ENABLE_LANGUAGE(ASM)
 CMAKE_MINIMUM_REQUIRED(VERSION 3.8.0)
 
-set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O2")
-set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O2")
+set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0")
+set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0")
 
 IF (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_BINARY_DIR})
     MESSAGE(