481 lines
27 KiB
ArmAsm
481 lines
27 KiB
ArmAsm
/* ================================================================================================== */
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/* BRIEF : Startup - Startup file for FC7240 */
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/* PERIPHERAL : N/A */
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/* PLATFORM : Flagchip FC7240 */
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/* SOFTWARE VERSION : 0.1.0 */
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/* VENDOR : Flagchip */
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/* Copyright 2024 Flagchip Semiconductors Co., Ltd. */
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/* All Rights Reserved. */
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/* ================================================================================================== */
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/* ================================================================================================== */
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/* Revision History */
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/* Version Date Initials CR# Descriptions */
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/* --------- ---------- ------------- ---------- --------------- */
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/* 0.1.0 2024-01-12 qxw0030 N/A Initial version */
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/* ================================================================================================== */
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.syntax unified
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.arch armv7-m
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.extern __StackTop
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.extern __StackLimit
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/* ================================================================================================== */
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/* Set vector table */
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/* ================================================================================================== */
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.section .isr_vector
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.align 2
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.globl __isr_vector
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/* vector table */
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External Interrupts*/
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.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
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.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
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.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
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.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
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.long DMA4_IRQHandler /* DMA channel 4 transfer complete */
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.long DMA5_IRQHandler /* DMA channel 5 transfer complete */
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.long DMA6_IRQHandler /* DMA channel 6 transfer complete */
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.long DMA7_IRQHandler /* DMA channel 7 transfer complete */
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.long DMA8_IRQHandler /* DMA channel 8 transfer complete */
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.long DMA9_IRQHandler /* DMA channel 9 transfer complete */
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.long DMA10_IRQHandler /* DMA channel 10 transfer complete */
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.long DMA11_IRQHandler /* DMA channel 11 transfer complete */
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.long DMA12_IRQHandler /* DMA channel 12 transfer complete */
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.long DMA13_IRQHandler /* DMA channel 13 transfer complete */
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.long DMA14_IRQHandler /* DMA channel 14 transfer complete */
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.long DMA15_IRQHandler /* DMA channel 15 transfer complete */
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.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-31 */
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.long CPM_IRQHandler /* FPU etc. interrupt */
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.long FC_IRQHandler /* FC Command complete */
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.long PMC_IRQHandler /* HVD/LVD etc. interrupt */
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.long TMU_IRQHandler /* Temperature Monitor Unit interrupt */
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.long WDOG0_IRQHandler /* interrupt request out before wdg reset out */
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.long WDOG1_IRQHandler /* interrupt request out before wdg reset out */
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.long FCSMU0_IRQHandler /* Fault Control and Safety Manage Unit */
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.long STCU0_IRQHandler /* Safety Control Unit interrupt */
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.long ERM_fault_IRQHandler /* ERM single/double bit error correction */
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.long MAM0_IRQHandler /* Matrix Access Monitor interrupt */
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.long RGM_Pre_IRQHandler /* RGM pre-reset Interrupt */
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.long INTM0_IRQHandler /* INTM alarm interrupt */
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.long ISM0_IRQHandler /* ISM0 interrupt */
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.long MB_IRQHandler /* Mail Box interrupt */
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.long SCG_IRQHandler /* SCG bus interrupt request */
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.long CMU0_IRQHandler /* CMU0 interrupt */
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.long CMU1_IRQHandler /* CMU1 interrupt */
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.long CMU2_IRQHandler /* CMU2 interrupt */
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.long CMU3_IRQHandler /* CMU3 interrupt */
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.long CMU4_IRQHandler /* CMU4 interrupt */
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.long TSTMP0_IRQHandler /* TimerStamp0 interrupt */
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.long TSTMP1_IRQHandler /* TimerStamp1 interrupt */
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.long CORDIC_IRQHandler /* CORDIC Accelerator interrupt */
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.long HSM0_IRQHandler /* HSM error interrupt */
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.long FCPIT0_IRQHandler /* FCPIT0 interrupt */
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.long RTC_IRQHandler /* RTC alarm or seconds interrupt */
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.long AONTIMER_IRQHandler /* AONTIMER interrupt request */
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.long SWI_IRQHandler /* Software interrupt */
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.long FREQM_IRQHandler /* FREQM interrupt */
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.long ADC0_IRQHandler /* ADC0 interrupt request. */
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.long ADC1_IRQHandler /* ADC1 interrupt request. */
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.long PTIMER0_IRQHandler /* PTIMER0 interrupt */
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.long PTIMER1_IRQHandler /* PTIMER1 interrupt */
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.long CAN0_IRQHandler /* CAN0 Interrupt */
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.long CAN1_IRQHandler /* CAN1 Interrupt */
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.long CAN2_IRQHandler /* CAN2 Interrupt */
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.long CAN3_IRQHandler /* CAN3 Interrupt */
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.long FCIIC0_IRQHandler /* FCIIC0 Interrupt */
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.long FCIIC1_IRQHandler /* FCIIC1 Interrupt */
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.long FCSPI0_IRQHandler /* FCSPI0 Interrupt */
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.long FCSPI1_IRQHandler /* FCSPI1 Interrupt */
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.long FCSPI2_IRQHandler /* FCSPI2 Interrupt */
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.long FCSPI3_IRQHandler /* FCSPI3 Interrupt */
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.long FCSPI4_IRQHandler /* FCSPI4 Interrupt */
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.long FCSPI5_IRQHandler /* FCSPI5 Interrupt */
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.long FCUART0_RxTx_IRQHandler /* FCUART0 Transmit / Receive Interrupt */
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.long FCUART1_RxTx_IRQHandler /* FCUART1 Transmit / Receive Interrupt */
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.long FCUART2_RxTx_IRQHandler /* FCUART2 Transmit / Receive Interrupt */
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.long FCUART3_RxTx_IRQHandler /* FCUART3 Transmit / Receive Interrupt */
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.long FCUART4_RxTx_IRQHandler /* FCUART4 Transmit / Receive Interrupt */
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.long FCUART5_RxTx_IRQHandler /* FCUART5 Transmit / Receive Interrupt */
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.long FCUART6_RxTx_IRQHandler /* FCUART6 Transmit / Receive Interrupt */
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.long FCUART7_RxTx_IRQHandler /* FCUART7 Transmit / Receive Interrupt */
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.long FTU0_IRQHandler /* FTU0 all source interrupt */
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.long FTU1_IRQHandler /* FTU1 all source interrupt */
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.long FTU2_IRQHandler /* FTU2 all source interrupt */
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.long FTU3_IRQHandler /* FTU3 all source interrupt */
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.long FTU4_IRQHandler /* FTU4 all source interrupt */
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.long FTU5_IRQHandler /* FTU5 all source interrupt */
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.long FTU6_IRQHandler /* FTU6 all source interrupt */
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.long FTU7_IRQHandler /* FTU7 all source interrupt */
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.long CMP0_IRQHandler /* CMP0 interrupt request */
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.long CMP1_IRQHandler /* CMP1 interrupt request */
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.long PORTA_IRQHandler /* Port A pin detect interrupt */
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.long PORTB_IRQHandler /* Port B pin detect interrupt */
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.long PORTC_IRQHandler /* Port C pin detect interrupt */
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.long PORTD_IRQHandler /* Port D pin detect interrupt */
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.long PORTE_IRQHandler /* Port E pin detect interrupt */
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.long MSC0_IRQHandler /* MSC interrupt */
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.long SENT0_IRQHandler /* SENT all interrupt (fast or slow) */
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.long TPU0_CH0_7_IRQHandler /* TPU0 CH0-7 interrupt */
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.long TPU0_CH8_15_IRQHandler /* TPU0 CH8-15 interrupt */
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.long TPU0_CH16_23_IRQHandler /* TPU0 CH16-23 interrupt */
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.long TPU0_CH24_31_IRQHandler /* TPU0 CH24-31 interrupt */
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.long HSM0_CRYPTO_IRQHandler /* HSM crypto interrupt */
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.long DefaultISR /* 108 */
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.long DefaultISR /* 109 */
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.long DefaultISR /* 110 */
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.long DefaultISR /* 111 */
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.long DefaultISR /* 112 */
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.long DefaultISR /* 113 */
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.long DefaultISR /* 114 */
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.long DefaultISR /* 115 */
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.long DefaultISR /* 116 */
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.long DefaultISR /* 117 */
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.long DefaultISR /* 118 */
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.long DefaultISR /* 119 */
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.long DefaultISR /* 120 */
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.long DefaultISR /* 121 */
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.long DefaultISR /* 122 */
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.long DefaultISR /* 123 */
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.long DefaultISR /* 124 */
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.long DefaultISR /* 125 */
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.long DefaultISR /* 126 */
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.long DefaultISR /* 127 */
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.long DefaultISR /* 128 */
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.long DefaultISR /* 129 */
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.long DefaultISR /* 130 */
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.long DefaultISR /* 131 */
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.long DefaultISR /* 132 */
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.long DefaultISR /* 133 */
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.long DefaultISR /* 134 */
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.long DefaultISR /* 135 */
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.long DefaultISR /* 136 */
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.long DefaultISR /* 137 */
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.long DefaultISR /* 138 */
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.long DefaultISR /* 139 */
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.long DefaultISR /* 140 */
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.long DefaultISR /* 141 */
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.long DefaultISR /* 142 */
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.long DefaultISR /* 143 */
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.long DefaultISR /* 144 */
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.long DefaultISR /* 145 */
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.long DefaultISR /* 146 */
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.long DefaultISR /* 147 */
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.long DefaultISR /* 148 */
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.long DefaultISR /* 149 */
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.long DefaultISR /* 150 */
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.long DefaultISR /* 151 */
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.long DefaultISR /* 152 */
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.long DefaultISR /* 153 */
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.long DefaultISR /* 154 */
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.long DefaultISR /* 155 */
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.long DefaultISR /* 156 */
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.long DefaultISR /* 157 */
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.long DefaultISR /* 158 */
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.long DefaultISR /* 159 */
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.long DefaultISR /* 160 */
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.long DefaultISR /* 161 */
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.long DefaultISR /* 162 */
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.long DefaultISR /* 163 */
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.long DefaultISR /* 164 */
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.long DefaultISR /* 165 */
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.long DefaultISR /* 166 */
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.long DefaultISR /* 167 */
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.long DefaultISR /* 168 */
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.long DefaultISR /* 169 */
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.long DefaultISR /* 170 */
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.long DefaultISR /* 171 */
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.long DefaultISR /* 172 */
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.long DefaultISR /* 173 */
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.long DefaultISR /* 174 */
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.long DefaultISR /* 175 */
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.long DefaultISR /* 176 */
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.long DefaultISR /* 177 */
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.long DefaultISR /* 178 */
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.long DefaultISR /* 179 */
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.long DefaultISR /* 180 */
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.long DefaultISR /* 181 */
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.long DefaultISR /* 182 */
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.long DefaultISR /* 183 */
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.long DefaultISR /* 184 */
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.long DefaultISR /* 185 */
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.long DefaultISR /* 186 */
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.long DefaultISR /* 187 */
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.long DefaultISR /* 188 */
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.long DefaultISR /* 189 */
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.long DefaultISR /* 190 */
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.long DefaultISR /* 191 */
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.long DefaultISR /* 192 */
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.long DefaultISR /* 193 */
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.long DefaultISR /* 194 */
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.long DefaultISR /* 195 */
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.long DefaultISR /* 196 */
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.long DefaultISR /* 197 */
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.long DefaultISR /* 198 */
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.long DefaultISR /* 199 */
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.long DefaultISR /* 200 */
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.long DefaultISR /* 201 */
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.long DefaultISR /* 202 */
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.long DefaultISR /* 203 */
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.long DefaultISR /* 204 */
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.long DefaultISR /* 205 */
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.long DefaultISR /* 206 */
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.long DefaultISR /* 207 */
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.long DefaultISR /* 208 */
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.long DefaultISR /* 209 */
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.long DefaultISR /* 210 */
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.long DefaultISR /* 211 */
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.long DefaultISR /* 212 */
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.long DefaultISR /* 213 */
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.long DefaultISR /* 214 */
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.long DefaultISR /* 215 */
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.long DefaultISR /* 216 */
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.long DefaultISR /* 217 */
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.long DefaultISR /* 218 */
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.long DefaultISR /* 219 */
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.long DefaultISR /* 220 */
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.long DefaultISR /* 221 */
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.long DefaultISR /* 222 */
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.long DefaultISR /* 223 */
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.long DefaultISR /* 224 */
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.long DefaultISR /* 225 */
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.long DefaultISR /* 226 */
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.long DefaultISR /* 227 */
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.long DefaultISR /* 228 */
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.long DefaultISR /* 229 */
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.long DefaultISR /* 230 */
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.long DefaultISR /* 231 */
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.long DefaultISR /* 232 */
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.long DefaultISR /* 233 */
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.long DefaultISR /* 234 */
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.long DefaultISR /* 235 */
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.long DefaultISR /* 236 */
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.long DefaultISR /* 237 */
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.long DefaultISR /* 238 */
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.long DefaultISR /* 239 */
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.long DefaultISR /* 240 */
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.long DefaultISR /* 241 */
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.long DefaultISR /* 242 */
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.long DefaultISR /* 243 */
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.long DefaultISR /* 244 */
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.long DefaultISR /* 245 */
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.long DefaultISR /* 246 */
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.long DefaultISR /* 247 */
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.long DefaultISR /* 248 */
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.long DefaultISR /* 249 */
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.long DefaultISR /* 250 */
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.long DefaultISR /* 251 */
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.long DefaultISR /* 252 */
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.long DefaultISR /* 253 */
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.long DefaultISR /* 254 */
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.long 0xFFFFFFFF /* Reserved for user TRIM value */
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.size __isr_vector, . - __isr_vector
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/**************************************************************/
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/************************ set other ***************************/
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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/* Init the rest of the registers */
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ldr r1,=0
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ldr r2,=0
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ldr r3,=0
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ldr r4,=0
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ldr r5,=0
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ldr r6,=0
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ldr r7,=0
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mov r8,r7
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mov r9,r7
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mov r10,r7
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mov r11,r7
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mov r12,r7
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ldr r0, =0xE000ED08
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ldr r1, =__vector_table
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str r1, [r0]
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/* Initialize the stack pointer */
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ldr r0,=__StackTop
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mov sp,r0 ; sp=r13
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/* Clear Stack */
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ldr r2, =__StackLimit
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ldr r4, =__StackTop
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movs r3, #0
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b LoopFillZero_STACK
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FillZero_STACK:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZero_STACK:
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cmp r2, r4
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bcc FillZero_STACK
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/* System Initialization */
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ldr r0,=System_Init
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blx r0
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/* Initialize .data and .bss sections */
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ldr r0,=Data_Init
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blx r0
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cpsie i /* Unmask interrupts */
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bl main
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JumpToSelf:
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b JumpToSelf
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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b DefaultISR
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.size DefaultISR, . - DefaultISR
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, DefaultISR
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.endm
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/* Exception Handlers */
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler DMA0_IRQHandler
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def_irq_handler DMA1_IRQHandler
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def_irq_handler DMA2_IRQHandler
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def_irq_handler DMA3_IRQHandler
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def_irq_handler DMA4_IRQHandler
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def_irq_handler DMA5_IRQHandler
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def_irq_handler DMA6_IRQHandler
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def_irq_handler DMA7_IRQHandler
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def_irq_handler DMA8_IRQHandler
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def_irq_handler DMA9_IRQHandler
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def_irq_handler DMA10_IRQHandler
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def_irq_handler DMA11_IRQHandler
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def_irq_handler DMA12_IRQHandler
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def_irq_handler DMA13_IRQHandler
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def_irq_handler DMA14_IRQHandler
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def_irq_handler DMA15_IRQHandler
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def_irq_handler DMA_Error_IRQHandler
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def_irq_handler CPM_IRQHandler
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def_irq_handler FC_IRQHandler
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def_irq_handler PMC_IRQHandler
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def_irq_handler TMU_IRQHandler
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def_irq_handler WDOG0_IRQHandler
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def_irq_handler WDOG1_IRQHandler
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def_irq_handler FCSMU0_IRQHandler
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def_irq_handler STCU0_IRQHandler
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def_irq_handler ERM_fault_IRQHandler
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def_irq_handler MAM0_IRQHandler
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def_irq_handler RGM_Pre_IRQHandler
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def_irq_handler INTM0_IRQHandler
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def_irq_handler ISM0_IRQHandler
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def_irq_handler MB_IRQHandler
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def_irq_handler SCG_IRQHandler
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def_irq_handler CMU0_IRQHandler
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def_irq_handler CMU1_IRQHandler
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def_irq_handler CMU2_IRQHandler
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def_irq_handler CMU3_IRQHandler
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def_irq_handler CMU4_IRQHandler
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def_irq_handler TSTMP0_IRQHandler
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def_irq_handler TSTMP1_IRQHandler
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def_irq_handler CORDIC_IRQHandler
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def_irq_handler HSM0_IRQHandler
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def_irq_handler FCPIT0_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler AONTIMER_IRQHandler
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def_irq_handler SWI_IRQHandler
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def_irq_handler FREQM_IRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler ADC1_IRQHandler
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def_irq_handler PTIMER0_IRQHandler
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def_irq_handler PTIMER1_IRQHandler
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def_irq_handler CAN0_IRQHandler
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def_irq_handler CAN1_IRQHandler
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def_irq_handler CAN2_IRQHandler
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def_irq_handler CAN3_IRQHandler
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def_irq_handler FCIIC0_IRQHandler
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def_irq_handler FCIIC1_IRQHandler
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def_irq_handler FCSPI0_IRQHandler
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def_irq_handler FCSPI1_IRQHandler
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def_irq_handler FCSPI2_IRQHandler
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def_irq_handler FCSPI3_IRQHandler
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def_irq_handler FCSPI4_IRQHandler
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def_irq_handler FCSPI5_IRQHandler
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def_irq_handler FCUART0_RxTx_IRQHandler
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def_irq_handler FCUART1_RxTx_IRQHandler
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def_irq_handler FCUART2_RxTx_IRQHandler
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def_irq_handler FCUART3_RxTx_IRQHandler
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def_irq_handler FCUART4_RxTx_IRQHandler
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def_irq_handler FCUART5_RxTx_IRQHandler
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def_irq_handler FCUART6_RxTx_IRQHandler
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def_irq_handler FCUART7_RxTx_IRQHandler
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def_irq_handler FTU0_IRQHandler
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def_irq_handler FTU1_IRQHandler
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def_irq_handler FTU2_IRQHandler
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def_irq_handler FTU3_IRQHandler
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def_irq_handler FTU4_IRQHandler
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def_irq_handler FTU5_IRQHandler
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def_irq_handler FTU6_IRQHandler
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def_irq_handler FTU7_IRQHandler
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def_irq_handler CMP0_IRQHandler
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def_irq_handler CMP1_IRQHandler
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def_irq_handler PORTA_IRQHandler
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def_irq_handler PORTB_IRQHandler
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def_irq_handler PORTC_IRQHandler
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def_irq_handler PORTD_IRQHandler
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def_irq_handler PORTE_IRQHandler
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def_irq_handler MSC0_IRQHandler
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def_irq_handler SENT0_IRQHandler
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def_irq_handler TPU0_CH0_7_IRQHandler
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def_irq_handler TPU0_CH8_15_IRQHandler
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def_irq_handler TPU0_CH16_23_IRQHandler
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def_irq_handler TPU0_CH24_31_IRQHandler
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def_irq_handler HSM0_CRYPTO_IRQHandler
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.end
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