#ifndef _MODULE_STCU_gmbhdijq151_REGS_H_STCU_H_
#define _MODULE_STCU_gmbhdijq151_REGS_H_STCU_H_

/* ----------------------------------------------------------------------------
   -- STCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup STCU_Peripheral_Access_Layer STCU Peripheral Access Layer
 * @{
 */

/** STCU - Size of Registers Arrays */

/** STCU - Register Layout Typedef */

typedef struct {

  __IO uint32_t SELF_TEST_KEY                 ; /* Self Test Key Register, offset: 0x0 */
  __IO uint32_t SELF_TEST_CTRL                ; /* Self Test Control Register, offset: 0x4 */
  __IO uint32_t SELF_TEST_STATUS              ; /* Self Test Status Register, offset: 0x8 */
  __IO uint32_t SELF_TEST_TRIG_A              ; /* Self Test Trigger A Register, offset: 0xC */
  __IO uint32_t SELF_TEST_TRIG_B              ; /* Self Test Trigger B Register, offset: 0x10 */
  __IO uint32_t SELF_TEST_RESET               ; /* Self Test Reset Register, offset: 0x14 */
  __IO uint32_t LBIST_PAT_CTRL                ; /* LBIST Pattern Control Register, offset: 0x18 */
       uint8_t  RESERVED_0[4];
  __IO uint32_t LBIST_EXP_MISR                ; /* LBIST Expected MISR Register, offset: 0x20 */
  __I  uint32_t LBIST_ACT_MISR                ; /* LBIST Actual MISR Register, offset: 0x24 */
  __IO uint32_t LBIST_STATUS                  ; /* LBIST Status Register, offset: 0x28 */
       uint8_t  RESERVED_1[8];
  __IO uint32_t MBIST_SEL                     ; /* MBIST Select Register, offset: 0x34 */
  __IO uint32_t MBIST_ALG                     ; /* MBIST Algorithm Register, offset: 0x38 */
  __IO uint32_t MBIST_DONE_STATUS             ; /* MBIST Done Status Register, offset: 0x3C */
  __IO uint32_t MBIST_FAIL_STATUS             ; /* MBIST Fail Status Register, offset: 0x40 */
       uint8_t  RESERVED_2[4];
  __IO uint32_t SRAM_INI_CTRL                 ; /* SRAM Initialization Control Register, offset: 0x48 */
  __IO uint32_t SRAM_INI_STATUS               ; /* SRAM Initialization Status Register, offset: 0x4C */
  __IO uint32_t SRAM_INI_SEL                  ; /* SRAM Initialization Select Register, offset: 0x50 */
  __IO uint32_t SRAM_INI_DONE_STATUS          ; /* SRAM Initialization Done Status Register, offset: 0x54 */
  __IO uint32_t IRQ                           ; /* Interrupt Request Register, offset: 0x58 */

} STCU_Type, *STCU_MemMapPtr;


/* STCU - Peripheral instance base addresses */
/** Peripheral STCU base address */
#define STCU_BASE                                (0x4007f000u)
/** Peripheral STCU base pointer */
#define STCU                                     ((STCU_Type *)STCU_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the STCU module. */
//#define STCU_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the STCU module. */
//#define STCU_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the STCU peripheral type */
//#define STCU_IRQS                                {STCU_IRQn}


/* ----------------------------------------------------------------------------
   -- STCU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup STCU_Register_Masks STCU Register Masks
 * @{
 */

/* SELF_TEST_KEY Bit Fields */
#define STCU_SELF_TEST_KEY_KEY_MASK    0xFFFFFFFFu
#define STCU_SELF_TEST_KEY_KEY_SHIFT   0u
#define STCU_SELF_TEST_KEY_KEY_WIDTH   32u
#define STCU_SELF_TEST_KEY_KEY(x)      (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_KEY_KEY_SHIFT))&STCU_SELF_TEST_KEY_KEY_MASK)
/* SELF_TEST_KEY Reg Mask */
#define STCU_SELF_TEST_KEY_MASK        0xFFFFFFFFu

/* SELF_TEST_CTRL Bit Fields */
#define STCU_SELF_TEST_CTRL_LBIST_CLKDIV_MASK 0xC0000000u
#define STCU_SELF_TEST_CTRL_LBIST_CLKDIV_SHIFT 30u
#define STCU_SELF_TEST_CTRL_LBIST_CLKDIV_WIDTH 2u
#define STCU_SELF_TEST_CTRL_LBIST_CLKDIV(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_LBIST_CLKDIV_SHIFT))&STCU_SELF_TEST_CTRL_LBIST_CLKDIV_MASK)
#define STCU_SELF_TEST_CTRL_LBIST_NVR_MASK 0x20000000u
#define STCU_SELF_TEST_CTRL_LBIST_NVR_SHIFT 29u
#define STCU_SELF_TEST_CTRL_LBIST_NVR_WIDTH 1u
#define STCU_SELF_TEST_CTRL_LBIST_NVR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_LBIST_NVR_SHIFT))&STCU_SELF_TEST_CTRL_LBIST_NVR_MASK)
#define STCU_SELF_TEST_CTRL_LBIST_EN_MASK 0x10000000u
#define STCU_SELF_TEST_CTRL_LBIST_EN_SHIFT 28u
#define STCU_SELF_TEST_CTRL_LBIST_EN_WIDTH 1u
#define STCU_SELF_TEST_CTRL_LBIST_EN(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_LBIST_EN_SHIFT))&STCU_SELF_TEST_CTRL_LBIST_EN_MASK)
#define STCU_SELF_TEST_CTRL_LBIST_TD_MASK 0x8000000u
#define STCU_SELF_TEST_CTRL_LBIST_TD_SHIFT 27u
#define STCU_SELF_TEST_CTRL_LBIST_TD_WIDTH 1u
#define STCU_SELF_TEST_CTRL_LBIST_TD(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_LBIST_TD_SHIFT))&STCU_SELF_TEST_CTRL_LBIST_TD_MASK)
#define STCU_SELF_TEST_CTRL_SCHK_EN_MASK 0x4000000u
#define STCU_SELF_TEST_CTRL_SCHK_EN_SHIFT 26u
#define STCU_SELF_TEST_CTRL_SCHK_EN_WIDTH 1u
#define STCU_SELF_TEST_CTRL_SCHK_EN(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_SCHK_EN_SHIFT))&STCU_SELF_TEST_CTRL_SCHK_EN_MASK)
#define STCU_SELF_TEST_CTRL_MBIST_LP_MASK 0x2000000u
#define STCU_SELF_TEST_CTRL_MBIST_LP_SHIFT 25u
#define STCU_SELF_TEST_CTRL_MBIST_LP_WIDTH 1u
#define STCU_SELF_TEST_CTRL_MBIST_LP(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_MBIST_LP_SHIFT))&STCU_SELF_TEST_CTRL_MBIST_LP_MASK)
#define STCU_SELF_TEST_CTRL_MBIST_EN_MASK 0x1000000u
#define STCU_SELF_TEST_CTRL_MBIST_EN_SHIFT 24u
#define STCU_SELF_TEST_CTRL_MBIST_EN_WIDTH 1u
#define STCU_SELF_TEST_CTRL_MBIST_EN(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_MBIST_EN_SHIFT))&STCU_SELF_TEST_CTRL_MBIST_EN_MASK)
#define STCU_SELF_TEST_CTRL_FCSMU_TRIG_MASK 0x400000u
#define STCU_SELF_TEST_CTRL_FCSMU_TRIG_SHIFT 22u
#define STCU_SELF_TEST_CTRL_FCSMU_TRIG_WIDTH 1u
#define STCU_SELF_TEST_CTRL_FCSMU_TRIG(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_FCSMU_TRIG_SHIFT))&STCU_SELF_TEST_CTRL_FCSMU_TRIG_MASK)
#define STCU_SELF_TEST_CTRL_CLK_SEL_MASK 0x200000u
#define STCU_SELF_TEST_CTRL_CLK_SEL_SHIFT 21u
#define STCU_SELF_TEST_CTRL_CLK_SEL_WIDTH 1u
#define STCU_SELF_TEST_CTRL_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_CLK_SEL_SHIFT))&STCU_SELF_TEST_CTRL_CLK_SEL_MASK)
#define STCU_SELF_TEST_CTRL_RST_TRIG_MASK 0x100000u
#define STCU_SELF_TEST_CTRL_RST_TRIG_SHIFT 20u
#define STCU_SELF_TEST_CTRL_RST_TRIG_WIDTH 1u
#define STCU_SELF_TEST_CTRL_RST_TRIG(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_RST_TRIG_SHIFT))&STCU_SELF_TEST_CTRL_RST_TRIG_MASK)
#define STCU_SELF_TEST_CTRL_STEST_BYPASS_MASK 0x80000u
#define STCU_SELF_TEST_CTRL_STEST_BYPASS_SHIFT 19u
#define STCU_SELF_TEST_CTRL_STEST_BYPASS_WIDTH 1u
#define STCU_SELF_TEST_CTRL_STEST_BYPASS(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_STEST_BYPASS_SHIFT))&STCU_SELF_TEST_CTRL_STEST_BYPASS_MASK)
#define STCU_SELF_TEST_CTRL_PS_MASK    0x40000u
#define STCU_SELF_TEST_CTRL_PS_SHIFT   18u
#define STCU_SELF_TEST_CTRL_PS_WIDTH   1u
#define STCU_SELF_TEST_CTRL_PS(x)      (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_PS_SHIFT))&STCU_SELF_TEST_CTRL_PS_MASK)
#define STCU_SELF_TEST_CTRL_PE_MASK    0x20000u
#define STCU_SELF_TEST_CTRL_PE_SHIFT   17u
#define STCU_SELF_TEST_CTRL_PE_WIDTH   1u
#define STCU_SELF_TEST_CTRL_PE(x)      (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_PE_SHIFT))&STCU_SELF_TEST_CTRL_PE_MASK)
#define STCU_SELF_TEST_CTRL_STEST_ST_MASK 0x10000u
#define STCU_SELF_TEST_CTRL_STEST_ST_SHIFT 16u
#define STCU_SELF_TEST_CTRL_STEST_ST_WIDTH 1u
#define STCU_SELF_TEST_CTRL_STEST_ST(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_STEST_ST_SHIFT))&STCU_SELF_TEST_CTRL_STEST_ST_MASK)
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN_MASK 0x8000u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN_SHIFT 15u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN_WIDTH 1u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN_SHIFT))&STCU_SELF_TEST_CTRL_FCSMU_PIN1_EN_MASK)
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN_MASK 0x4000u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN_SHIFT 14u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN_WIDTH 1u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN_SHIFT))&STCU_SELF_TEST_CTRL_FCSMU_PIN0_EN_MASK)
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL_MASK 0x2000u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL_SHIFT 13u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL_WIDTH 1u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL_SHIFT))&STCU_SELF_TEST_CTRL_FCSMU_PIN1_VAL_MASK)
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL_MASK 0x1000u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL_SHIFT 12u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL_WIDTH 1u
#define STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL_SHIFT))&STCU_SELF_TEST_CTRL_FCSMU_PIN0_VAL_MASK)
#define STCU_SELF_TEST_CTRL_MT_MASK    0xFFFu
#define STCU_SELF_TEST_CTRL_MT_SHIFT   0u
#define STCU_SELF_TEST_CTRL_MT_WIDTH   12u
#define STCU_SELF_TEST_CTRL_MT(x)      (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_CTRL_MT_SHIFT))&STCU_SELF_TEST_CTRL_MT_MASK)
/* SELF_TEST_CTRL Reg Mask */
#define STCU_SELF_TEST_CTRL_MASK       0xFF7FFFFFu

/* SELF_TEST_STATUS Bit Fields */
#define STCU_SELF_TEST_STATUS_SCHK_ERR_MASK 0x200u
#define STCU_SELF_TEST_STATUS_SCHK_ERR_SHIFT 9u
#define STCU_SELF_TEST_STATUS_SCHK_ERR_WIDTH 1u
#define STCU_SELF_TEST_STATUS_SCHK_ERR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_SCHK_ERR_SHIFT))&STCU_SELF_TEST_STATUS_SCHK_ERR_MASK)
#define STCU_SELF_TEST_STATUS_NVR_LD_ERR_MASK 0x100u
#define STCU_SELF_TEST_STATUS_NVR_LD_ERR_SHIFT 8u
#define STCU_SELF_TEST_STATUS_NVR_LD_ERR_WIDTH 1u
#define STCU_SELF_TEST_STATUS_NVR_LD_ERR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_NVR_LD_ERR_SHIFT))&STCU_SELF_TEST_STATUS_NVR_LD_ERR_MASK)
#define STCU_SELF_TEST_STATUS_TIMEOUT_ERR_MASK 0x40u
#define STCU_SELF_TEST_STATUS_TIMEOUT_ERR_SHIFT 6u
#define STCU_SELF_TEST_STATUS_TIMEOUT_ERR_WIDTH 1u
#define STCU_SELF_TEST_STATUS_TIMEOUT_ERR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_TIMEOUT_ERR_SHIFT))&STCU_SELF_TEST_STATUS_TIMEOUT_ERR_MASK)
#define STCU_SELF_TEST_STATUS_MBIST_ERR_MASK 0x20u
#define STCU_SELF_TEST_STATUS_MBIST_ERR_SHIFT 5u
#define STCU_SELF_TEST_STATUS_MBIST_ERR_WIDTH 1u
#define STCU_SELF_TEST_STATUS_MBIST_ERR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_MBIST_ERR_SHIFT))&STCU_SELF_TEST_STATUS_MBIST_ERR_MASK)
#define STCU_SELF_TEST_STATUS_LBIST_ERR_MASK 0x10u
#define STCU_SELF_TEST_STATUS_LBIST_ERR_SHIFT 4u
#define STCU_SELF_TEST_STATUS_LBIST_ERR_WIDTH 1u
#define STCU_SELF_TEST_STATUS_LBIST_ERR(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_LBIST_ERR_SHIFT))&STCU_SELF_TEST_STATUS_LBIST_ERR_MASK)
#define STCU_SELF_TEST_STATUS_STEST_ABORT_MASK 0x2u
#define STCU_SELF_TEST_STATUS_STEST_ABORT_SHIFT 1u
#define STCU_SELF_TEST_STATUS_STEST_ABORT_WIDTH 1u
#define STCU_SELF_TEST_STATUS_STEST_ABORT(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_STEST_ABORT_SHIFT))&STCU_SELF_TEST_STATUS_STEST_ABORT_MASK)
#define STCU_SELF_TEST_STATUS_STEST_DONE_MASK 0x1u
#define STCU_SELF_TEST_STATUS_STEST_DONE_SHIFT 0u
#define STCU_SELF_TEST_STATUS_STEST_DONE_WIDTH 1u
#define STCU_SELF_TEST_STATUS_STEST_DONE(x) (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_STATUS_STEST_DONE_SHIFT))&STCU_SELF_TEST_STATUS_STEST_DONE_MASK)
/* SELF_TEST_STATUS Reg Mask */
#define STCU_SELF_TEST_STATUS_MASK     0x00000373u

/* SELF_TEST_TRIG_A Bit Fields */
#define STCU_SELF_TEST_TRIG_A_TRIG_MASK 0x1u
#define STCU_SELF_TEST_TRIG_A_TRIG_SHIFT 0u
#define STCU_SELF_TEST_TRIG_A_TRIG_WIDTH 1u
#define STCU_SELF_TEST_TRIG_A_TRIG(x)  (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_TRIG_A_TRIG_SHIFT))&STCU_SELF_TEST_TRIG_A_TRIG_MASK)
/* SELF_TEST_TRIG_A Reg Mask */
#define STCU_SELF_TEST_TRIG_A_MASK     0x00000001u

/* SELF_TEST_TRIG_B Bit Fields */
#define STCU_SELF_TEST_TRIG_B_TRIG_MASK 0x1u
#define STCU_SELF_TEST_TRIG_B_TRIG_SHIFT 0u
#define STCU_SELF_TEST_TRIG_B_TRIG_WIDTH 1u
#define STCU_SELF_TEST_TRIG_B_TRIG(x)  (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_TRIG_B_TRIG_SHIFT))&STCU_SELF_TEST_TRIG_B_TRIG_MASK)
/* SELF_TEST_TRIG_B Reg Mask */
#define STCU_SELF_TEST_TRIG_B_MASK     0x00000001u

/* SELF_TEST_RESET Bit Fields */
#define STCU_SELF_TEST_RESET_RST_MASK  0x1u
#define STCU_SELF_TEST_RESET_RST_SHIFT 0u
#define STCU_SELF_TEST_RESET_RST_WIDTH 1u
#define STCU_SELF_TEST_RESET_RST(x)    (((uint32_t)(((uint32_t)(x))<<STCU_SELF_TEST_RESET_RST_SHIFT))&STCU_SELF_TEST_RESET_RST_MASK)
/* SELF_TEST_RESET Reg Mask */
#define STCU_SELF_TEST_RESET_MASK      0x00000001u

/* LBIST_PAT_CTRL Bit Fields */
#define STCU_LBIST_PAT_CTRL_N_MASK     0x3FFu
#define STCU_LBIST_PAT_CTRL_N_SHIFT    0u
#define STCU_LBIST_PAT_CTRL_N_WIDTH    10u
#define STCU_LBIST_PAT_CTRL_N(x)       (((uint32_t)(((uint32_t)(x))<<STCU_LBIST_PAT_CTRL_N_SHIFT))&STCU_LBIST_PAT_CTRL_N_MASK)
/* LBIST_PAT_CTRL Reg Mask */
#define STCU_LBIST_PAT_CTRL_MASK       0x000003FFu

/* LBIST_EXP_MISR Bit Fields */
#define STCU_LBIST_EXP_MISR_MISR_MASK  0xFFFFFFu
#define STCU_LBIST_EXP_MISR_MISR_SHIFT 0u
#define STCU_LBIST_EXP_MISR_MISR_WIDTH 24u
#define STCU_LBIST_EXP_MISR_MISR(x)    (((uint32_t)(((uint32_t)(x))<<STCU_LBIST_EXP_MISR_MISR_SHIFT))&STCU_LBIST_EXP_MISR_MISR_MASK)
/* LBIST_EXP_MISR Reg Mask */
#define STCU_LBIST_EXP_MISR_MASK       0x00FFFFFFu

/* LBIST_ACT_MISR Bit Fields */
#define STCU_LBIST_ACT_MISR_MISR_MASK  0xFFFFFFu
#define STCU_LBIST_ACT_MISR_MISR_SHIFT 0u
#define STCU_LBIST_ACT_MISR_MISR_WIDTH 24u
#define STCU_LBIST_ACT_MISR_MISR(x)    (((uint32_t)(((uint32_t)(x))<<STCU_LBIST_ACT_MISR_MISR_SHIFT))&STCU_LBIST_ACT_MISR_MISR_MASK)
/* LBIST_ACT_MISR Reg Mask */
#define STCU_LBIST_ACT_MISR_MASK       0x00FFFFFFu

/* LBIST_STATUS Bit Fields */
#define STCU_LBIST_STATUS_FAIL_MASK    0x10000u
#define STCU_LBIST_STATUS_FAIL_SHIFT   16u
#define STCU_LBIST_STATUS_FAIL_WIDTH   1u
#define STCU_LBIST_STATUS_FAIL(x)      (((uint32_t)(((uint32_t)(x))<<STCU_LBIST_STATUS_FAIL_SHIFT))&STCU_LBIST_STATUS_FAIL_MASK)
#define STCU_LBIST_STATUS_DONE_MASK    0x1u
#define STCU_LBIST_STATUS_DONE_SHIFT   0u
#define STCU_LBIST_STATUS_DONE_WIDTH   1u
#define STCU_LBIST_STATUS_DONE(x)      (((uint32_t)(((uint32_t)(x))<<STCU_LBIST_STATUS_DONE_SHIFT))&STCU_LBIST_STATUS_DONE_MASK)
/* LBIST_STATUS Reg Mask */
#define STCU_LBIST_STATUS_MASK         0x00010001u

/* MBIST_SEL Bit Fields */
#define STCU_MBIST_SEL_HSM_ROM_MASK    0x400u
#define STCU_MBIST_SEL_HSM_ROM_SHIFT   10u
#define STCU_MBIST_SEL_HSM_ROM_WIDTH   1u
#define STCU_MBIST_SEL_HSM_ROM(x)      (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_HSM_ROM_SHIFT))&STCU_MBIST_SEL_HSM_ROM_MASK)
#define STCU_MBIST_SEL_SYS_ROM_MASK    0x200u
#define STCU_MBIST_SEL_SYS_ROM_SHIFT   9u
#define STCU_MBIST_SEL_SYS_ROM_WIDTH   1u
#define STCU_MBIST_SEL_SYS_ROM(x)      (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_SYS_ROM_SHIFT))&STCU_MBIST_SEL_SYS_ROM_MASK)
#define STCU_MBIST_SEL_DMA_FLEXCAN_MASK 0x100u
#define STCU_MBIST_SEL_DMA_FLEXCAN_SHIFT 8u
#define STCU_MBIST_SEL_DMA_FLEXCAN_WIDTH 1u
#define STCU_MBIST_SEL_DMA_FLEXCAN(x)  (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_DMA_FLEXCAN_SHIFT))&STCU_MBIST_SEL_DMA_FLEXCAN_MASK)
#define STCU_MBIST_SEL_HSM_MASK        0x80u
#define STCU_MBIST_SEL_HSM_SHIFT       7u
#define STCU_MBIST_SEL_HSM_WIDTH       1u
#define STCU_MBIST_SEL_HSM(x)          (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_HSM_SHIFT))&STCU_MBIST_SEL_HSM_MASK)
#define STCU_MBIST_SEL_SUBSYS_MASK     0x40u
#define STCU_MBIST_SEL_SUBSYS_SHIFT    6u
#define STCU_MBIST_SEL_SUBSYS_WIDTH    1u
#define STCU_MBIST_SEL_SUBSYS(x)       (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_SUBSYS_SHIFT))&STCU_MBIST_SEL_SUBSYS_MASK)
#define STCU_MBIST_SEL_CACHE_MASK      0x20u
#define STCU_MBIST_SEL_CACHE_SHIFT     5u
#define STCU_MBIST_SEL_CACHE_WIDTH     1u
#define STCU_MBIST_SEL_CACHE(x)        (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_CACHE_SHIFT))&STCU_MBIST_SEL_CACHE_MASK)
#define STCU_MBIST_SEL_DTCM_CPU_MASK   0x10u
#define STCU_MBIST_SEL_DTCM_CPU_SHIFT  4u
#define STCU_MBIST_SEL_DTCM_CPU_WIDTH  1u
#define STCU_MBIST_SEL_DTCM_CPU(x)     (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_DTCM_CPU_SHIFT))&STCU_MBIST_SEL_DTCM_CPU_MASK)
#define STCU_MBIST_SEL_ITCM_CPU_MASK   0x8u
#define STCU_MBIST_SEL_ITCM_CPU_SHIFT  3u
#define STCU_MBIST_SEL_ITCM_CPU_WIDTH  1u
#define STCU_MBIST_SEL_ITCM_CPU(x)     (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_ITCM_CPU_SHIFT))&STCU_MBIST_SEL_ITCM_CPU_MASK)
#define STCU_MBIST_SEL_SRAM2_MASK      0x4u
#define STCU_MBIST_SEL_SRAM2_SHIFT     2u
#define STCU_MBIST_SEL_SRAM2_WIDTH     1u
#define STCU_MBIST_SEL_SRAM2(x)        (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_SRAM2_SHIFT))&STCU_MBIST_SEL_SRAM2_MASK)
#define STCU_MBIST_SEL_SRAM1_MASK      0x2u
#define STCU_MBIST_SEL_SRAM1_SHIFT     1u
#define STCU_MBIST_SEL_SRAM1_WIDTH     1u
#define STCU_MBIST_SEL_SRAM1(x)        (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_SRAM1_SHIFT))&STCU_MBIST_SEL_SRAM1_MASK)
#define STCU_MBIST_SEL_SRAM0_MASK      0x1u
#define STCU_MBIST_SEL_SRAM0_SHIFT     0u
#define STCU_MBIST_SEL_SRAM0_WIDTH     1u
#define STCU_MBIST_SEL_SRAM0(x)        (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_SEL_SRAM0_SHIFT))&STCU_MBIST_SEL_SRAM0_MASK)
/* MBIST_SEL Reg Mask */
#define STCU_MBIST_SEL_MASK            0x000007FFu

/* MBIST_ALG Bit Fields */
#define STCU_MBIST_ALG_TRIG_INI_EN_MASK 0x2000u
#define STCU_MBIST_ALG_TRIG_INI_EN_SHIFT 13u
#define STCU_MBIST_ALG_TRIG_INI_EN_WIDTH 1u
#define STCU_MBIST_ALG_TRIG_INI_EN(x)  (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_ALG_TRIG_INI_EN_SHIFT))&STCU_MBIST_ALG_TRIG_INI_EN_MASK)
#define STCU_MBIST_ALG_TRIG_ALG_SEL_MASK 0x1F00u
#define STCU_MBIST_ALG_TRIG_ALG_SEL_SHIFT 8u
#define STCU_MBIST_ALG_TRIG_ALG_SEL_WIDTH 5u
#define STCU_MBIST_ALG_TRIG_ALG_SEL(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_ALG_TRIG_ALG_SEL_SHIFT))&STCU_MBIST_ALG_TRIG_ALG_SEL_MASK)
#define STCU_MBIST_ALG_POR_INI_EN_MASK 0x20u
#define STCU_MBIST_ALG_POR_INI_EN_SHIFT 5u
#define STCU_MBIST_ALG_POR_INI_EN_WIDTH 1u
#define STCU_MBIST_ALG_POR_INI_EN(x)   (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_ALG_POR_INI_EN_SHIFT))&STCU_MBIST_ALG_POR_INI_EN_MASK)
#define STCU_MBIST_ALG_POR_ALG_SEL_MASK 0x1Fu
#define STCU_MBIST_ALG_POR_ALG_SEL_SHIFT 0u
#define STCU_MBIST_ALG_POR_ALG_SEL_WIDTH 5u
#define STCU_MBIST_ALG_POR_ALG_SEL(x)  (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_ALG_POR_ALG_SEL_SHIFT))&STCU_MBIST_ALG_POR_ALG_SEL_MASK)
/* MBIST_ALG Reg Mask */
#define STCU_MBIST_ALG_MASK            0x00003F3Fu

/* MBIST_DONE_STATUS Bit Fields */
#define STCU_MBIST_DONE_STATUS_HSM_ROM_MASK 0x400u
#define STCU_MBIST_DONE_STATUS_HSM_ROM_SHIFT 10u
#define STCU_MBIST_DONE_STATUS_HSM_ROM_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_HSM_ROM(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_HSM_ROM_SHIFT))&STCU_MBIST_DONE_STATUS_HSM_ROM_MASK)
#define STCU_MBIST_DONE_STATUS_SYS_ROM_MASK 0x200u
#define STCU_MBIST_DONE_STATUS_SYS_ROM_SHIFT 9u
#define STCU_MBIST_DONE_STATUS_SYS_ROM_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_SYS_ROM(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_SYS_ROM_SHIFT))&STCU_MBIST_DONE_STATUS_SYS_ROM_MASK)
#define STCU_MBIST_DONE_STATUS_DMA_FLEXCAN_MASK 0x100u
#define STCU_MBIST_DONE_STATUS_DMA_FLEXCAN_SHIFT 8u
#define STCU_MBIST_DONE_STATUS_DMA_FLEXCAN_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_DMA_FLEXCAN(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_DMA_FLEXCAN_SHIFT))&STCU_MBIST_DONE_STATUS_DMA_FLEXCAN_MASK)
#define STCU_MBIST_DONE_STATUS_HSM_MASK 0x80u
#define STCU_MBIST_DONE_STATUS_HSM_SHIFT 7u
#define STCU_MBIST_DONE_STATUS_HSM_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_HSM(x)  (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_HSM_SHIFT))&STCU_MBIST_DONE_STATUS_HSM_MASK)
#define STCU_MBIST_DONE_STATUS_SUBSYS_MASK 0x40u
#define STCU_MBIST_DONE_STATUS_SUBSYS_SHIFT 6u
#define STCU_MBIST_DONE_STATUS_SUBSYS_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_SUBSYS(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_SUBSYS_SHIFT))&STCU_MBIST_DONE_STATUS_SUBSYS_MASK)
#define STCU_MBIST_DONE_STATUS_CACHE_MASK 0x20u
#define STCU_MBIST_DONE_STATUS_CACHE_SHIFT 5u
#define STCU_MBIST_DONE_STATUS_CACHE_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_CACHE(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_CACHE_SHIFT))&STCU_MBIST_DONE_STATUS_CACHE_MASK)
#define STCU_MBIST_DONE_STATUS_DTCM_CPU_MASK 0x10u
#define STCU_MBIST_DONE_STATUS_DTCM_CPU_SHIFT 4u
#define STCU_MBIST_DONE_STATUS_DTCM_CPU_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_DTCM_CPU(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_DTCM_CPU_SHIFT))&STCU_MBIST_DONE_STATUS_DTCM_CPU_MASK)
#define STCU_MBIST_DONE_STATUS_ITCM_CPU_MASK 0x8u
#define STCU_MBIST_DONE_STATUS_ITCM_CPU_SHIFT 3u
#define STCU_MBIST_DONE_STATUS_ITCM_CPU_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_ITCM_CPU(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_ITCM_CPU_SHIFT))&STCU_MBIST_DONE_STATUS_ITCM_CPU_MASK)
#define STCU_MBIST_DONE_STATUS_SRAM2_MASK 0x4u
#define STCU_MBIST_DONE_STATUS_SRAM2_SHIFT 2u
#define STCU_MBIST_DONE_STATUS_SRAM2_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_SRAM2(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_SRAM2_SHIFT))&STCU_MBIST_DONE_STATUS_SRAM2_MASK)
#define STCU_MBIST_DONE_STATUS_SRAM1_MASK 0x2u
#define STCU_MBIST_DONE_STATUS_SRAM1_SHIFT 1u
#define STCU_MBIST_DONE_STATUS_SRAM1_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_SRAM1(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_SRAM1_SHIFT))&STCU_MBIST_DONE_STATUS_SRAM1_MASK)
#define STCU_MBIST_DONE_STATUS_SRAM0_MASK 0x1u
#define STCU_MBIST_DONE_STATUS_SRAM0_SHIFT 0u
#define STCU_MBIST_DONE_STATUS_SRAM0_WIDTH 1u
#define STCU_MBIST_DONE_STATUS_SRAM0(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_DONE_STATUS_SRAM0_SHIFT))&STCU_MBIST_DONE_STATUS_SRAM0_MASK)
/* MBIST_DONE_STATUS Reg Mask */
#define STCU_MBIST_DONE_STATUS_MASK    0x000007FFu

/* MBIST_FAIL_STATUS Bit Fields */
#define STCU_MBIST_FAIL_STATUS_HSM_ROM_MASK 0x400u
#define STCU_MBIST_FAIL_STATUS_HSM_ROM_SHIFT 10u
#define STCU_MBIST_FAIL_STATUS_HSM_ROM_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_HSM_ROM(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_HSM_ROM_SHIFT))&STCU_MBIST_FAIL_STATUS_HSM_ROM_MASK)
#define STCU_MBIST_FAIL_STATUS_SYS_ROM_MASK 0x200u
#define STCU_MBIST_FAIL_STATUS_SYS_ROM_SHIFT 9u
#define STCU_MBIST_FAIL_STATUS_SYS_ROM_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_SYS_ROM(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_SYS_ROM_SHIFT))&STCU_MBIST_FAIL_STATUS_SYS_ROM_MASK)
#define STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN_MASK 0x100u
#define STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN_SHIFT 8u
#define STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN_SHIFT))&STCU_MBIST_FAIL_STATUS_DMA_FLEXCAN_MASK)
#define STCU_MBIST_FAIL_STATUS_HSM_MASK 0x80u
#define STCU_MBIST_FAIL_STATUS_HSM_SHIFT 7u
#define STCU_MBIST_FAIL_STATUS_HSM_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_HSM(x)  (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_HSM_SHIFT))&STCU_MBIST_FAIL_STATUS_HSM_MASK)
#define STCU_MBIST_FAIL_STATUS_SUBSYS_MASK 0x40u
#define STCU_MBIST_FAIL_STATUS_SUBSYS_SHIFT 6u
#define STCU_MBIST_FAIL_STATUS_SUBSYS_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_SUBSYS(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_SUBSYS_SHIFT))&STCU_MBIST_FAIL_STATUS_SUBSYS_MASK)
#define STCU_MBIST_FAIL_STATUS_CACHE_MASK 0x20u
#define STCU_MBIST_FAIL_STATUS_CACHE_SHIFT 5u
#define STCU_MBIST_FAIL_STATUS_CACHE_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_CACHE(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_CACHE_SHIFT))&STCU_MBIST_FAIL_STATUS_CACHE_MASK)
#define STCU_MBIST_FAIL_STATUS_DTCM_CPU_MASK 0x10u
#define STCU_MBIST_FAIL_STATUS_DTCM_CPU_SHIFT 4u
#define STCU_MBIST_FAIL_STATUS_DTCM_CPU_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_DTCM_CPU(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_DTCM_CPU_SHIFT))&STCU_MBIST_FAIL_STATUS_DTCM_CPU_MASK)
#define STCU_MBIST_FAIL_STATUS_ITCM_CPU_MASK 0x8u
#define STCU_MBIST_FAIL_STATUS_ITCM_CPU_SHIFT 3u
#define STCU_MBIST_FAIL_STATUS_ITCM_CPU_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_ITCM_CPU(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_ITCM_CPU_SHIFT))&STCU_MBIST_FAIL_STATUS_ITCM_CPU_MASK)
#define STCU_MBIST_FAIL_STATUS_SRAM2_MASK 0x4u
#define STCU_MBIST_FAIL_STATUS_SRAM2_SHIFT 2u
#define STCU_MBIST_FAIL_STATUS_SRAM2_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_SRAM2(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_SRAM2_SHIFT))&STCU_MBIST_FAIL_STATUS_SRAM2_MASK)
#define STCU_MBIST_FAIL_STATUS_SRAM1_MASK 0x2u
#define STCU_MBIST_FAIL_STATUS_SRAM1_SHIFT 1u
#define STCU_MBIST_FAIL_STATUS_SRAM1_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_SRAM1(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_SRAM1_SHIFT))&STCU_MBIST_FAIL_STATUS_SRAM1_MASK)
#define STCU_MBIST_FAIL_STATUS_SRAM0_MASK 0x1u
#define STCU_MBIST_FAIL_STATUS_SRAM0_SHIFT 0u
#define STCU_MBIST_FAIL_STATUS_SRAM0_WIDTH 1u
#define STCU_MBIST_FAIL_STATUS_SRAM0(x) (((uint32_t)(((uint32_t)(x))<<STCU_MBIST_FAIL_STATUS_SRAM0_SHIFT))&STCU_MBIST_FAIL_STATUS_SRAM0_MASK)
/* MBIST_FAIL_STATUS Reg Mask */
#define STCU_MBIST_FAIL_STATUS_MASK    0x000007FFu

/* SRAM_INI_CTRL Bit Fields */
#define STCU_SRAM_INI_CTRL_MODE_MASK   0x30000u
#define STCU_SRAM_INI_CTRL_MODE_SHIFT  16u
#define STCU_SRAM_INI_CTRL_MODE_WIDTH  2u
#define STCU_SRAM_INI_CTRL_MODE(x)     (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_CTRL_MODE_SHIFT))&STCU_SRAM_INI_CTRL_MODE_MASK)
#define STCU_SRAM_INI_CTRL_OFF_EN_MASK 0x4u
#define STCU_SRAM_INI_CTRL_OFF_EN_SHIFT 2u
#define STCU_SRAM_INI_CTRL_OFF_EN_WIDTH 1u
#define STCU_SRAM_INI_CTRL_OFF_EN(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_CTRL_OFF_EN_SHIFT))&STCU_SRAM_INI_CTRL_OFF_EN_MASK)
#define STCU_SRAM_INI_CTRL_LOCK_MASK   0x2u
#define STCU_SRAM_INI_CTRL_LOCK_SHIFT  1u
#define STCU_SRAM_INI_CTRL_LOCK_WIDTH  1u
#define STCU_SRAM_INI_CTRL_LOCK(x)     (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_CTRL_LOCK_SHIFT))&STCU_SRAM_INI_CTRL_LOCK_MASK)
#define STCU_SRAM_INI_CTRL_EN_MASK     0x1u
#define STCU_SRAM_INI_CTRL_EN_SHIFT    0u
#define STCU_SRAM_INI_CTRL_EN_WIDTH    1u
#define STCU_SRAM_INI_CTRL_EN(x)       (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_CTRL_EN_SHIFT))&STCU_SRAM_INI_CTRL_EN_MASK)
/* SRAM_INI_CTRL Reg Mask */
#define STCU_SRAM_INI_CTRL_MASK        0x00030007u

/* SRAM_INI_STATUS Bit Fields */
#define STCU_SRAM_INI_STATUS_ABORT_MASK 0x4u
#define STCU_SRAM_INI_STATUS_ABORT_SHIFT 2u
#define STCU_SRAM_INI_STATUS_ABORT_WIDTH 1u
#define STCU_SRAM_INI_STATUS_ABORT(x)  (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_STATUS_ABORT_SHIFT))&STCU_SRAM_INI_STATUS_ABORT_MASK)
#define STCU_SRAM_INI_STATUS_BUSY_MASK 0x2u
#define STCU_SRAM_INI_STATUS_BUSY_SHIFT 1u
#define STCU_SRAM_INI_STATUS_BUSY_WIDTH 1u
#define STCU_SRAM_INI_STATUS_BUSY(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_STATUS_BUSY_SHIFT))&STCU_SRAM_INI_STATUS_BUSY_MASK)
#define STCU_SRAM_INI_STATUS_DONE_MASK 0x1u
#define STCU_SRAM_INI_STATUS_DONE_SHIFT 0u
#define STCU_SRAM_INI_STATUS_DONE_WIDTH 1u
#define STCU_SRAM_INI_STATUS_DONE(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_STATUS_DONE_SHIFT))&STCU_SRAM_INI_STATUS_DONE_MASK)
/* SRAM_INI_STATUS Reg Mask */
#define STCU_SRAM_INI_STATUS_MASK      0x00000007u

/* SRAM_INI_SEL Bit Fields */
#define STCU_SRAM_INI_SEL_DTCM_CPU1_MASK 0x40u
#define STCU_SRAM_INI_SEL_DTCM_CPU1_SHIFT 6u
#define STCU_SRAM_INI_SEL_DTCM_CPU1_WIDTH 1u
#define STCU_SRAM_INI_SEL_DTCM_CPU1(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_DTCM_CPU1_SHIFT))&STCU_SRAM_INI_SEL_DTCM_CPU1_MASK)
#define STCU_SRAM_INI_SEL_ITCM_CPU1_MASK 0x20u
#define STCU_SRAM_INI_SEL_ITCM_CPU1_SHIFT 5u
#define STCU_SRAM_INI_SEL_ITCM_CPU1_WIDTH 1u
#define STCU_SRAM_INI_SEL_ITCM_CPU1(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_ITCM_CPU1_SHIFT))&STCU_SRAM_INI_SEL_ITCM_CPU1_MASK)
#define STCU_SRAM_INI_SEL_DTCM_CPU0_MASK 0x10u
#define STCU_SRAM_INI_SEL_DTCM_CPU0_SHIFT 4u
#define STCU_SRAM_INI_SEL_DTCM_CPU0_WIDTH 1u
#define STCU_SRAM_INI_SEL_DTCM_CPU0(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_DTCM_CPU0_SHIFT))&STCU_SRAM_INI_SEL_DTCM_CPU0_MASK)
#define STCU_SRAM_INI_SEL_ITCM_CPU0_MASK 0x8u
#define STCU_SRAM_INI_SEL_ITCM_CPU0_SHIFT 3u
#define STCU_SRAM_INI_SEL_ITCM_CPU0_WIDTH 1u
#define STCU_SRAM_INI_SEL_ITCM_CPU0(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_ITCM_CPU0_SHIFT))&STCU_SRAM_INI_SEL_ITCM_CPU0_MASK)
#define STCU_SRAM_INI_SEL_SRAM2_MASK 0x4u
#define STCU_SRAM_INI_SEL_SRAM2_SHIFT 2u
#define STCU_SRAM_INI_SEL_SRAM2_WIDTH 1u
#define STCU_SRAM_INI_SEL_SRAM2(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_SRAM2_SHIFT))&STCU_SRAM_INI_SEL_SRAM2_MASK)
#define STCU_SRAM_INI_SEL_SRAM1_MASK 0x2u
#define STCU_SRAM_INI_SEL_SRAM1_SHIFT 1u
#define STCU_SRAM_INI_SEL_SRAM1_WIDTH 1u
#define STCU_SRAM_INI_SEL_SRAM1(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_SRAM1_SHIFT))&STCU_SRAM_INI_SEL_SRAM1_MASK)
#define STCU_SRAM_INI_SEL_SRAM0_MASK 0x1u
#define STCU_SRAM_INI_SEL_SRAM0_SHIFT 0u
#define STCU_SRAM_INI_SEL_SRAM0_WIDTH 1u
#define STCU_SRAM_INI_SEL_SRAM0(x)   (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_SEL_SRAM0_SHIFT))&STCU_SRAM_INI_SEL_SRAM0_MASK)
/* SRAM_INI_SEL Reg Mask */
#define STCU_SRAM_INI_SEL_MASK         0x0000007Fu

/* SRAM_INI_DONE_STATUS Bit Fields */
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1_MASK 0x40u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1_SHIFT 6u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1_SHIFT))&STCU_SRAM_INI_DONE_STATUS_DTCM_CPU1_MASK)
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1_MASK 0x20u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1_SHIFT 5u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1_SHIFT))&STCU_SRAM_INI_DONE_STATUS_ITCM_CPU1_MASK)
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0_MASK 0x10u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0_SHIFT 4u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0_SHIFT))&STCU_SRAM_INI_DONE_STATUS_DTCM_CPU0_MASK)
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0_MASK 0x8u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0_SHIFT 3u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0_SHIFT))&STCU_SRAM_INI_DONE_STATUS_ITCM_CPU0_MASK)
#define STCU_SRAM_INI_DONE_STATUS_SRAM2_MASK 0x4u
#define STCU_SRAM_INI_DONE_STATUS_SRAM2_SHIFT 2u
#define STCU_SRAM_INI_DONE_STATUS_SRAM2_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_SRAM2(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_SRAM2_SHIFT))&STCU_SRAM_INI_DONE_STATUS_SRAM2_MASK)
#define STCU_SRAM_INI_DONE_STATUS_SRAM1_MASK 0x2u
#define STCU_SRAM_INI_DONE_STATUS_SRAM1_SHIFT 1u
#define STCU_SRAM_INI_DONE_STATUS_SRAM1_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_SRAM1(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_SRAM1_SHIFT))&STCU_SRAM_INI_DONE_STATUS_SRAM1_MASK)
#define STCU_SRAM_INI_DONE_STATUS_SRAM0_MASK 0x1u
#define STCU_SRAM_INI_DONE_STATUS_SRAM0_SHIFT 0u
#define STCU_SRAM_INI_DONE_STATUS_SRAM0_WIDTH 1u
#define STCU_SRAM_INI_DONE_STATUS_SRAM0(x) (((uint32_t)(((uint32_t)(x))<<STCU_SRAM_INI_DONE_STATUS_SRAM0_SHIFT))&STCU_SRAM_INI_DONE_STATUS_SRAM0_MASK)
/* SRAM_INI_DONE_STATUS Reg Mask */
#define STCU_SRAM_INI_DONE_STATUS_MASK 0x0000007Fu

/* IRQ Bit Fields */
#define STCU_IRQ_EN_MASK               0x80000000u
#define STCU_IRQ_EN_SHIFT              31u
#define STCU_IRQ_EN_WIDTH              1u
#define STCU_IRQ_EN(x)                 (((uint32_t)(((uint32_t)(x))<<STCU_IRQ_EN_SHIFT))&STCU_IRQ_EN_MASK)
#define STCU_IRQ_SEQ_ERR_MASK          0x2u
#define STCU_IRQ_SEQ_ERR_SHIFT         1u
#define STCU_IRQ_SEQ_ERR_WIDTH         1u
#define STCU_IRQ_SEQ_ERR(x)            (((uint32_t)(((uint32_t)(x))<<STCU_IRQ_SEQ_ERR_SHIFT))&STCU_IRQ_SEQ_ERR_MASK)
#define STCU_IRQ_SIZE_ERR_MASK         0x1u
#define STCU_IRQ_SIZE_ERR_SHIFT        0u
#define STCU_IRQ_SIZE_ERR_WIDTH        1u
#define STCU_IRQ_SIZE_ERR(x)           (((uint32_t)(((uint32_t)(x))<<STCU_IRQ_SIZE_ERR_SHIFT))&STCU_IRQ_SIZE_ERR_MASK)
/* IRQ Reg Mask */
#define STCU_IRQ_MASK                  0x80000003u


/*!
 * @}
 */ /* end of group STCU_Register_Masks */

/*!
 * @}
 */ /* end of group STCU_Peripheral_Access_Layer */

#endif
