#ifndef _MODULE_EFTU_CCM_gmbhdijq131_REGS_H_EFTU_CCM_H_
#define _MODULE_EFTU_CCM_gmbhdijq131_REGS_H_EFTU_CCM_H_

/* ----------------------------------------------------------------------------
   -- EFTU_CCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EFTU_CCM_Peripheral_Access_Layer EFTU_CCM Peripheral Access Layer
 * @{
 */

/** EFTU_CCM - Size of Registers Arrays */

/** EFTU_CCM - Register Layout Typedef */
#define EFTU_CCM_RESn_LOCK_COUNT 14
#define EFTU_CCM_DMA_SRC_COUNT 8

typedef struct {

       uint8_t  RESERVED_0[16];
  __IO uint32_t CNTO_MUX                      ; /* Counter output mux Register, offset: 0x10 */
       uint8_t  RESERVED_1[236];
  __IO uint32_t RESn_LOCK[EFTU_CCM_RESn_LOCK_COUNT]; /* Resource N's Lock Register, offset: 0x100 */
       uint8_t  RESERVED_2[168];
  __IO uint32_t TIM_IN_SRC                    ; /* TIM Input Source Register, offset: 0x1E0 */
  __IO uint32_t TIM_IN_SRC0                   ; /* TIM AUX Input Source Register, offset: 0x1E4 */
  __IO uint32_t TIM_IN_SRC1                   ; /* TIM AUX Input Source Register, offset: 0x1E8 */
  __I  uint32_t EFTU_OUT                      ; /* EFTU Output status Register, offset: 0x1EC */
  __IO uint32_t CMU_CLK_CFG                   ; /* CMU Clock Configuration Register, offset: 0x1F0 */
       uint8_t  RESERVED_3[4];
  __IO uint32_t CFG                           ; /* Configuration Register, offset: 0x1F8 */
  __IO uint32_t PROT                          ; /* Protection Register, offset: 0x1FC */
  __IO uint32_t GTOM_MUX_0                    ; /* GTOM Multiplex0 Register, offset: 0x200 */
  __IO uint32_t GTOM_MUX_1                    ; /* GTOM Multiplex1 Register, offset: 0x204 */
  __IO uint32_t GTOM_MUX_2                    ; /* GTOM Multiplex2 Register, offset: 0x208 */
  __IO uint32_t GTOM_MUX_3                    ; /* GTOM Multiplex3 Register, offset: 0x20C */
       uint8_t  RESERVED_4[4];
  __IO uint32_t TRG_MUX                       ; /* Trigger Multiplex Register, offset: 0x214 */
  __IO uint32_t TRG_EN0                       ; /* Trigger Enable0 Register, offset: 0x218 */
  __IO uint32_t TRG_EN1                       ; /* Trigger Enable1 Register, offset: 0x21C */
  __IO uint32_t CMP_MUX_SEL                   ; /* CMP Multiplex Selection Register, offset: 0x220 */
       uint8_t  RESERVED_5[12];
  __IO uint32_t TOM_MUX                       ; /* TOM MUX Register, offset: 0x230 */
       uint8_t  RESERVED_6[8];
  __IO uint32_t SPEC_LOCK                     ; /* Special Lock Register, offset: 0x23C */
  __IO uint32_t EINT_ST                       ; /* Error Interrupt Status Register, offset: 0x240 */
  __IO uint32_t EINT_EN                       ; /* Error Interrupt Enable Register, offset: 0x244 */
  __IO uint32_t TIM_EINT_EN0                  ; /* TIM Error Interrupt Enable0 Register, offset: 0x248 */
  __IO uint32_t TIM_EINT_EN1                  ; /* TIM Error Interrupt Enable1 Register, offset: 0x24C */
  __IO uint32_t TIM_EINT_ST0                  ; /* TIM Error Interrupt Status0 Register, offset: 0x250 */
  __IO uint32_t TIM_EINT_ST1                  ; /* TIM Error Interrupt Status1 Register, offset: 0x254 */
       uint8_t  RESERVED_7[8];
  __I  uint32_t DMA_ST                        ; /* DMA Status Register, offset: 0x260 */
  __IO uint32_t DMA_SRC[EFTU_CCM_DMA_SRC_COUNT]; /* DMA Source Register, offset: 0x264 */

} EFTU_CCM_Type, *EFTU_CCM_MemMapPtr;


/* EFTU_CCM - Peripheral instance base addresses */
/** Peripheral EFTU_CCM base address */
#define EFTU_CCM_BASE                            (0x4083E000u)
/** Peripheral EFTU_CCM base pointer */
#define EFTU_CCM                                 ((EFTU_CCM_Type *)EFTU_CCM_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the EFTU_CCM module. */
//#define EFTU_CCM_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the EFTU_CCM module. */
//#define EFTU_CCM_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the EFTU_CCM peripheral type */
//#define EFTU_CCM_IRQS                            {EFTU_CCM_IRQn}


/* ----------------------------------------------------------------------------
   -- EFTU_CCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EFTU_CCM_Register_Masks EFTU_CCM Register Masks
 * @{
 */

/* CNTO_MUX Bit Fields */
#define EFTU_CCM_CNTO_MUX_CNT0_MUX_MASK 0x7u
#define EFTU_CCM_CNTO_MUX_CNT0_MUX_SHIFT 0u
#define EFTU_CCM_CNTO_MUX_CNT0_MUX_WIDTH 3u
#define EFTU_CCM_CNTO_MUX_CNT0_MUX(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CNTO_MUX_CNT0_MUX_SHIFT))&EFTU_CCM_CNTO_MUX_CNT0_MUX_MASK)
#define EFTU_CCM_CNTO_MUX_CNT1_MUX_MASK 0x70u
#define EFTU_CCM_CNTO_MUX_CNT1_MUX_SHIFT 4u
#define EFTU_CCM_CNTO_MUX_CNT1_MUX_WIDTH 3u
#define EFTU_CCM_CNTO_MUX_CNT1_MUX(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CNTO_MUX_CNT1_MUX_SHIFT))&EFTU_CCM_CNTO_MUX_CNT1_MUX_MASK)
/* CNTO_MUX Reg Mask */
#define EFTU_CCM_CNTO_MUX_MASK         0x00000077u

/* RESn_LOCK Bit Fields */
#define EFTU_CCM_RESn_LOCK_LOCK_CHN_MASK 0xFFu
#define EFTU_CCM_RESn_LOCK_LOCK_CHN_SHIFT 0u
#define EFTU_CCM_RESn_LOCK_LOCK_CHN_WIDTH 8u
#define EFTU_CCM_RESn_LOCK_LOCK_CHN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_RESn_LOCK_LOCK_CHN_SHIFT))&EFTU_CCM_RESn_LOCK_LOCK_CHN_MASK)
/* RES0_LOCK Reg Mask */
#define EFTU_CCM_RESn_LOCK_MASK        0x000000FFu

/* CMU_CLK_CFG Bit Fields */
#define EFTU_CCM_CMU_CLK_CFG_CLK0_SRC_MASK 0x3u
#define EFTU_CCM_CMU_CLK_CFG_CLK0_SRC_SHIFT 0u
#define EFTU_CCM_CMU_CLK_CFG_CLK0_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK0_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK0_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK0_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK1_SRC_MASK 0x30u
#define EFTU_CCM_CMU_CLK_CFG_CLK1_SRC_SHIFT 4u
#define EFTU_CCM_CMU_CLK_CFG_CLK1_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK1_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK1_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK1_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK2_SRC_MASK 0x300u
#define EFTU_CCM_CMU_CLK_CFG_CLK2_SRC_SHIFT 8u
#define EFTU_CCM_CMU_CLK_CFG_CLK2_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK2_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK2_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK2_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK3_SRC_MASK 0x3000u
#define EFTU_CCM_CMU_CLK_CFG_CLK3_SRC_SHIFT 12u
#define EFTU_CCM_CMU_CLK_CFG_CLK3_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK3_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK3_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK3_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK4_SRC_MASK 0x30000u
#define EFTU_CCM_CMU_CLK_CFG_CLK4_SRC_SHIFT 16u
#define EFTU_CCM_CMU_CLK_CFG_CLK4_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK4_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK4_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK4_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK5_SRC_MASK 0x300000u
#define EFTU_CCM_CMU_CLK_CFG_CLK5_SRC_SHIFT 20u
#define EFTU_CCM_CMU_CLK_CFG_CLK5_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK5_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK5_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK5_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK6_SRC_MASK 0x3000000u
#define EFTU_CCM_CMU_CLK_CFG_CLK6_SRC_SHIFT 24u
#define EFTU_CCM_CMU_CLK_CFG_CLK6_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK6_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK6_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK6_SRC_MASK)
#define EFTU_CCM_CMU_CLK_CFG_CLK7_SRC_MASK 0x30000000u
#define EFTU_CCM_CMU_CLK_CFG_CLK7_SRC_SHIFT 28u
#define EFTU_CCM_CMU_CLK_CFG_CLK7_SRC_WIDTH 2u
#define EFTU_CCM_CMU_CLK_CFG_CLK7_SRC(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMU_CLK_CFG_CLK7_SRC_SHIFT))&EFTU_CCM_CMU_CLK_CFG_CLK7_SRC_MASK)
/* CMU_CLK_CFG Reg Mask */
#define EFTU_CCM_CMU_CLK_CFG_MASK      0x33333333u

/* CFG Bit Fields */
#define EFTU_CCM_CFG_EN_TIM_MASK       0x1u
#define EFTU_CCM_CFG_EN_TIM_SHIFT      0u
#define EFTU_CCM_CFG_EN_TIM_WIDTH      1u
#define EFTU_CCM_CFG_EN_TIM(x)         (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CFG_EN_TIM_SHIFT))&EFTU_CCM_CFG_EN_TIM_MASK)
#define EFTU_CCM_CFG_EN_TOM0_MASK      0x2u
#define EFTU_CCM_CFG_EN_TOM0_SHIFT     1u
#define EFTU_CCM_CFG_EN_TOM0_WIDTH     1u
#define EFTU_CCM_CFG_EN_TOM0(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CFG_EN_TOM0_SHIFT))&EFTU_CCM_CFG_EN_TOM0_MASK)
#define EFTU_CCM_CFG_EN_TOM1_MASK      0x4u
#define EFTU_CCM_CFG_EN_TOM1_SHIFT     2u
#define EFTU_CCM_CFG_EN_TOM1_WIDTH     1u
#define EFTU_CCM_CFG_EN_TOM1(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CFG_EN_TOM1_SHIFT))&EFTU_CCM_CFG_EN_TOM1_MASK)
/* CFG Reg Mask */
#define EFTU_CCM_CFG_MASK              0x00000007u

/* PROT Bit Fields */
#define EFTU_CCM_PROT_CLS_PROT_MASK    0x1u
#define EFTU_CCM_PROT_CLS_PROT_SHIFT   0u
#define EFTU_CCM_PROT_CLS_PROT_WIDTH   1u
#define EFTU_CCM_PROT_CLS_PROT(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_PROT_CLS_PROT_SHIFT))&EFTU_CCM_PROT_CLS_PROT_MASK)
#define EFTU_CCM_PROT_DBG_MODE_MASK    0x6u
#define EFTU_CCM_PROT_DBG_MODE_SHIFT   1u
#define EFTU_CCM_PROT_DBG_MODE_WIDTH   2u
#define EFTU_CCM_PROT_DBG_MODE(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_PROT_DBG_MODE_SHIFT))&EFTU_CCM_PROT_DBG_MODE_MASK)
/* PROT Reg Mask */
#define EFTU_CCM_PROT_MASK             0x00000007u

/* TIM_IN_SRC Bit Fields */
#define EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL_MASK 0xFFu
#define EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL_SHIFT 0u
#define EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL_WIDTH 8u
#define EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL_SHIFT))&EFTU_CCM_TIM_IN_SRC_TIM_IN_SEL_MASK)
/* TIM_IN_SRC Reg Mask */
#define EFTU_CCM_TIM_IN_SRC_MASK       0x000000FFu

/* TIM_IN_SRC0 Bit Fields */
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0_MASK 0x7Fu
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0_SHIFT 0u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0_SHIFT))&EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL0_MASK)
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1_MASK 0x7F00u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1_SHIFT 8u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1_SHIFT))&EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL1_MASK)
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2_MASK 0x7F0000u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2_SHIFT 16u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2_SHIFT))&EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL2_MASK)
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3_MASK 0x7F000000u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3_SHIFT 24u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3_SHIFT))&EFTU_CCM_TIM_IN_SRC0_TIM_AUX_SEL3_MASK)
/* TIM_IN_SRC0 Reg Mask */
#define EFTU_CCM_TIM_IN_SRC0_MASK      0x7F7F7F7Fu

/* TIM_IN_SRC1 Bit Fields */
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4_MASK 0x7Fu
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4_SHIFT 0u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4_SHIFT))&EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL4_MASK)
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5_MASK 0x7F00u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5_SHIFT 8u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5_SHIFT))&EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL5_MASK)
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6_MASK 0x7F0000u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6_SHIFT 16u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6_SHIFT))&EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL6_MASK)
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7_MASK 0x7F000000u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7_SHIFT 24u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7_WIDTH 7u
#define EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7_SHIFT))&EFTU_CCM_TIM_IN_SRC1_TIM_AUX_SEL7_MASK)
/* TIM_IN_SRC1 Reg Mask */
#define EFTU_CCM_TIM_IN_SRC1_MASK      0x7F7F7F7Fu

/* EFTU_OUT Bit Fields */
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_MASK 0xFFFFu
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_SHIFT 0u
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_WIDTH 16u
#define EFTU_CCM_EFTU_OUT_EFTU_OUT(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EFTU_OUT_EFTU_OUT_SHIFT))&EFTU_CCM_EFTU_OUT_EFTU_OUT_MASK)
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_T_MASK 0xFFFF0000u
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_T_SHIFT 16u
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_T_WIDTH 16u
#define EFTU_CCM_EFTU_OUT_EFTU_OUT_T(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EFTU_OUT_EFTU_OUT_T_SHIFT))&EFTU_CCM_EFTU_OUT_EFTU_OUT_T_MASK)
/* EFTU_OUT Reg Mask */
#define EFTU_CCM_EFTU_OUT_MASK         0xFFFFFFFFu

/* GTOM_MUX_0 Bit Fields */
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0_MASK 0x7Fu
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0_SHIFT 0u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0_SHIFT))&EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_0_MASK)
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1_MASK 0x7F00u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1_SHIFT 8u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1_SHIFT))&EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_1_MASK)
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2_MASK 0x7F0000u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2_SHIFT 16u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2_SHIFT))&EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_2_MASK)
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3_MASK 0x7F000000u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3_SHIFT 24u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3_SHIFT))&EFTU_CCM_GTOM_MUX_0_GTOM_MUX_CTRL_3_MASK)
/* GTOM_MUX_0 Reg Mask */
#define EFTU_CCM_GTOM_MUX_0_MASK       0x7F7F7F7Fu

/* GTOM_MUX_1 Bit Fields */
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4_MASK 0x7Fu
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4_SHIFT 0u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4_SHIFT))&EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_4_MASK)
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5_MASK 0x7F00u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5_SHIFT 8u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5_SHIFT))&EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_5_MASK)
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6_MASK 0x7F0000u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6_SHIFT 16u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6_SHIFT))&EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_6_MASK)
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7_MASK 0x7F000000u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7_SHIFT 24u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7_SHIFT))&EFTU_CCM_GTOM_MUX_1_GTOM_MUX_CTRL_7_MASK)
/* GTOM_MUX_1 Reg Mask */
#define EFTU_CCM_GTOM_MUX_1_MASK       0x7F7F7F7Fu

/* GTOM_MUX_2 Bit Fields */
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8_MASK 0x7Fu
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8_SHIFT 0u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8_SHIFT))&EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_8_MASK)
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9_MASK 0x7F00u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9_SHIFT 8u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9_SHIFT))&EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_9_MASK)
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10_MASK 0x7F0000u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10_SHIFT 16u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10_SHIFT))&EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_10_MASK)
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11_MASK 0x7F000000u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11_SHIFT 24u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11_SHIFT))&EFTU_CCM_GTOM_MUX_2_GTOM_MUX_CTRL_11_MASK)
/* GTOM_MUX_2 Reg Mask */
#define EFTU_CCM_GTOM_MUX_2_MASK       0x7F7F7F7Fu

/* GTOM_MUX_3 Bit Fields */
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12_MASK 0x7Fu
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12_SHIFT 0u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12_SHIFT))&EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_12_MASK)
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13_MASK 0x7F00u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13_SHIFT 8u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13_SHIFT))&EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_13_MASK)
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14_MASK 0x7F0000u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14_SHIFT 16u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14_SHIFT))&EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_14_MASK)
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15_MASK 0x7F000000u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15_SHIFT 24u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15_WIDTH 7u
#define EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15_SHIFT))&EFTU_CCM_GTOM_MUX_3_GTOM_MUX_CTRL_15_MASK)
/* GTOM_MUX_3 Reg Mask */
#define EFTU_CCM_GTOM_MUX_3_MASK       0x7F7F7F7Fu

/* TRG_MUX Bit Fields */
#define EFTU_CCM_TRG_MUX_TRIG_MUX_MASK 0xFFFFu
#define EFTU_CCM_TRG_MUX_TRIG_MUX_SHIFT 0u
#define EFTU_CCM_TRG_MUX_TRIG_MUX_WIDTH 16u
#define EFTU_CCM_TRG_MUX_TRIG_MUX(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_MUX_TRIG_MUX_SHIFT))&EFTU_CCM_TRG_MUX_TRIG_MUX_MASK)
/* TRG_MUX Reg Mask */
#define EFTU_CCM_TRG_MUX_MASK          0x0000FFFFu

/* TRG_EN0 Bit Fields */
#define EFTU_CCM_TRG_EN0_SRC_ENABLE3_MASK 0x1F000000u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE3_SHIFT 24u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE3_WIDTH 5u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN0_SRC_ENABLE3_SHIFT))&EFTU_CCM_TRG_EN0_SRC_ENABLE3_MASK)
#define EFTU_CCM_TRG_EN0_SRC_ENABLE2_MASK 0x1F0000u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE2_SHIFT 16u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE2_WIDTH 5u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN0_SRC_ENABLE2_SHIFT))&EFTU_CCM_TRG_EN0_SRC_ENABLE2_MASK)
#define EFTU_CCM_TRG_EN0_SRC_ENABLE1_MASK 0x1F00u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE1_SHIFT 8u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE1_WIDTH 5u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN0_SRC_ENABLE1_SHIFT))&EFTU_CCM_TRG_EN0_SRC_ENABLE1_MASK)
#define EFTU_CCM_TRG_EN0_SRC_ENABLE0_MASK 0x1Fu
#define EFTU_CCM_TRG_EN0_SRC_ENABLE0_SHIFT 0u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE0_WIDTH 5u
#define EFTU_CCM_TRG_EN0_SRC_ENABLE0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN0_SRC_ENABLE0_SHIFT))&EFTU_CCM_TRG_EN0_SRC_ENABLE0_MASK)
/* TRG_EN0 Reg Mask */
#define EFTU_CCM_TRG_EN0_MASK          0x1F1F1F1Fu

/* TRG_EN1 Bit Fields */
#define EFTU_CCM_TRG_EN1_SRC_ENABLE7_MASK 0x1F000000u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE7_SHIFT 24u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE7_WIDTH 5u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN1_SRC_ENABLE7_SHIFT))&EFTU_CCM_TRG_EN1_SRC_ENABLE7_MASK)
#define EFTU_CCM_TRG_EN1_SRC_ENABLE6_MASK 0x1F0000u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE6_SHIFT 16u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE6_WIDTH 5u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN1_SRC_ENABLE6_SHIFT))&EFTU_CCM_TRG_EN1_SRC_ENABLE6_MASK)
#define EFTU_CCM_TRG_EN1_SRC_ENABLE5_MASK 0x1F00u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE5_SHIFT 8u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE5_WIDTH 5u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN1_SRC_ENABLE5_SHIFT))&EFTU_CCM_TRG_EN1_SRC_ENABLE5_MASK)
#define EFTU_CCM_TRG_EN1_SRC_ENABLE4_MASK 0x1Fu
#define EFTU_CCM_TRG_EN1_SRC_ENABLE4_SHIFT 0u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE4_WIDTH 5u
#define EFTU_CCM_TRG_EN1_SRC_ENABLE4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TRG_EN1_SRC_ENABLE4_SHIFT))&EFTU_CCM_TRG_EN1_SRC_ENABLE4_MASK)
/* TRG_EN1 Reg Mask */
#define EFTU_CCM_TRG_EN1_MASK          0x1F1F1F1Fu

/* CMP_MUX_SEL Bit Fields */
#define EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL_MASK 0xFu
#define EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL_SHIFT 0u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL_WIDTH 4u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP0_X_SEL_MASK)
#define EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL_MASK 0xF0u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL_SHIFT 4u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL_WIDTH 4u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP0_Y_SEL_MASK)
#define EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL_MASK 0xF00u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL_SHIFT 8u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL_WIDTH 4u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP1_X_SEL_MASK)
#define EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL_MASK 0xF000u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL_SHIFT 12u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL_WIDTH 4u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP1_Y_SEL_MASK)
#define EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN_MASK 0xFF0000u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN_SHIFT 16u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN_WIDTH 8u
#define EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP0_CMP_EN_MASK)
#define EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN_MASK 0xFF000000u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN_SHIFT 24u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN_WIDTH 8u
#define EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN_SHIFT))&EFTU_CCM_CMP_MUX_SEL_CMP1_CMP_EN_MASK)
/* CMP_MUX_SEL Reg Mask */
#define EFTU_CCM_CMP_MUX_SEL_MASK      0xFFFFFFFFu

/* TOM_MUX Bit Fields */
#define EFTU_CCM_TOM_MUX_TOM_MUX_CTRL_MASK 0x1u
#define EFTU_CCM_TOM_MUX_TOM_MUX_CTRL_SHIFT 0u
#define EFTU_CCM_TOM_MUX_TOM_MUX_CTRL_WIDTH 1u
#define EFTU_CCM_TOM_MUX_TOM_MUX_CTRL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TOM_MUX_TOM_MUX_CTRL_SHIFT))&EFTU_CCM_TOM_MUX_TOM_MUX_CTRL_MASK)
#define EFTU_CCM_TOM_MUX_TOM_SWAP_MASK 0x7Eu
#define EFTU_CCM_TOM_MUX_TOM_SWAP_SHIFT 1u
#define EFTU_CCM_TOM_MUX_TOM_SWAP_WIDTH 6u
#define EFTU_CCM_TOM_MUX_TOM_SWAP(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TOM_MUX_TOM_SWAP_SHIFT))&EFTU_CCM_TOM_MUX_TOM_SWAP_MASK)
/* TOM_MUX Reg Mask */
#define EFTU_CCM_TOM_MUX_MASK          0x0000007Fu

/* SPEC_LOCK Bit Fields */
#define EFTU_CCM_SPEC_LOCK_SPEC_LOCK_MASK 0xFFFFFFFFu
#define EFTU_CCM_SPEC_LOCK_SPEC_LOCK_SHIFT 0u
#define EFTU_CCM_SPEC_LOCK_SPEC_LOCK_WIDTH 32u
#define EFTU_CCM_SPEC_LOCK_SPEC_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_SPEC_LOCK_SPEC_LOCK_SHIFT))&EFTU_CCM_SPEC_LOCK_SPEC_LOCK_MASK)
/* SPEC_LOCK Reg Mask */
#define EFTU_CCM_SPEC_LOCK_MASK        0xFFFFFFFFu

/* EINT_ST Bit Fields */
#define EFTU_CCM_EINT_ST_CMP0_ERR_MASK 0x1u
#define EFTU_CCM_EINT_ST_CMP0_ERR_SHIFT 0u
#define EFTU_CCM_EINT_ST_CMP0_ERR_WIDTH 1u
#define EFTU_CCM_EINT_ST_CMP0_ERR(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_CMP0_ERR_SHIFT))&EFTU_CCM_EINT_ST_CMP0_ERR_MASK)
#define EFTU_CCM_EINT_ST_CMP1_ERR_MASK 0x2u
#define EFTU_CCM_EINT_ST_CMP1_ERR_SHIFT 1u
#define EFTU_CCM_EINT_ST_CMP1_ERR_WIDTH 1u
#define EFTU_CCM_EINT_ST_CMP1_ERR(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_CMP1_ERR_SHIFT))&EFTU_CCM_EINT_ST_CMP1_ERR_MASK)
#define EFTU_CCM_EINT_ST_SPE0_INT_MASK 0x200000u
#define EFTU_CCM_EINT_ST_SPE0_INT_SHIFT 21u
#define EFTU_CCM_EINT_ST_SPE0_INT_WIDTH 1u
#define EFTU_CCM_EINT_ST_SPE0_INT(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_SPE0_INT_SHIFT))&EFTU_CCM_EINT_ST_SPE0_INT_MASK)
#define EFTU_CCM_EINT_ST_SPE1_INT_MASK 0x400000u
#define EFTU_CCM_EINT_ST_SPE1_INT_SHIFT 22u
#define EFTU_CCM_EINT_ST_SPE1_INT_WIDTH 1u
#define EFTU_CCM_EINT_ST_SPE1_INT(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_SPE1_INT_SHIFT))&EFTU_CCM_EINT_ST_SPE1_INT_MASK)
#define EFTU_CCM_EINT_ST_EAC_INT_MASK  0x800000u
#define EFTU_CCM_EINT_ST_EAC_INT_SHIFT 23u
#define EFTU_CCM_EINT_ST_EAC_INT_WIDTH 1u
#define EFTU_CCM_EINT_ST_EAC_INT(x)    (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_EAC_INT_SHIFT))&EFTU_CCM_EINT_ST_EAC_INT_MASK)
#define EFTU_CCM_EINT_ST_TIM_ERR_MASK  0xFF000000u
#define EFTU_CCM_EINT_ST_TIM_ERR_SHIFT 24u
#define EFTU_CCM_EINT_ST_TIM_ERR_WIDTH 8u
#define EFTU_CCM_EINT_ST_TIM_ERR(x)    (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_ST_TIM_ERR_SHIFT))&EFTU_CCM_EINT_ST_TIM_ERR_MASK)
/* EINT_ST Reg Mask */
#define EFTU_CCM_EINT_ST_MASK          0xFFE00003u

/* EINT_EN Bit Fields */
#define EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK 0x1u
#define EFTU_CCM_EINT_EN_CMP0_ENABLE_SHIFT 0u
#define EFTU_CCM_EINT_EN_CMP0_ENABLE_WIDTH 1u
#define EFTU_CCM_EINT_EN_CMP0_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_EN_CMP0_ENABLE_SHIFT))&EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK)
#define EFTU_CCM_EINT_EN_CMP1_ENABLE_MASK 0x2u
#define EFTU_CCM_EINT_EN_CMP1_ENABLE_SHIFT 1u
#define EFTU_CCM_EINT_EN_CMP1_ENABLE_WIDTH 1u
#define EFTU_CCM_EINT_EN_CMP1_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_EN_CMP1_ENABLE_SHIFT))&EFTU_CCM_EINT_EN_CMP1_ENABLE_MASK)
#define EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER_MASK 0xFF00u
#define EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER_SHIFT 8u
#define EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER_WIDTH 8u
#define EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER_SHIFT))&EFTU_CCM_EINT_EN_ERR_IRQ_ROUTER_MASK)
#define EFTU_CCM_EINT_EN_TIM_ERR_MASK  0xFF000000u
#define EFTU_CCM_EINT_EN_TIM_ERR_SHIFT 24u
#define EFTU_CCM_EINT_EN_TIM_ERR_WIDTH 8u
#define EFTU_CCM_EINT_EN_TIM_ERR(x)    (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_EINT_EN_TIM_ERR_SHIFT))&EFTU_CCM_EINT_EN_TIM_ERR_MASK)
/* EINT_EN Reg Mask */
#define EFTU_CCM_EINT_EN_MASK          0xFF00FF03u

/* TIM_EINT_EN0 Bit Fields */
#define EFTU_CCM_TIM_EINT_EN0_CH0_EN_MASK 0x3Fu
#define EFTU_CCM_TIM_EINT_EN0_CH0_EN_SHIFT 0u
#define EFTU_CCM_TIM_EINT_EN0_CH0_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN0_CH0_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN0_CH0_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN0_CH0_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN0_CH1_EN_MASK 0x3F00u
#define EFTU_CCM_TIM_EINT_EN0_CH1_EN_SHIFT 8u
#define EFTU_CCM_TIM_EINT_EN0_CH1_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN0_CH1_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN0_CH1_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN0_CH1_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN0_CH2_EN_MASK 0x3F0000u
#define EFTU_CCM_TIM_EINT_EN0_CH2_EN_SHIFT 16u
#define EFTU_CCM_TIM_EINT_EN0_CH2_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN0_CH2_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN0_CH2_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN0_CH2_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN0_CH3_EN_MASK 0x3F000000u
#define EFTU_CCM_TIM_EINT_EN0_CH3_EN_SHIFT 24u
#define EFTU_CCM_TIM_EINT_EN0_CH3_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN0_CH3_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN0_CH3_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN0_CH3_EN_MASK)
/* TIM_EINT_EN0 Reg Mask */
#define EFTU_CCM_TIM_EINT_EN0_MASK     0x3F3F3F3Fu

/* TIM_EINT_EN1 Bit Fields */
#define EFTU_CCM_TIM_EINT_EN1_CH4_EN_MASK 0x3Fu
#define EFTU_CCM_TIM_EINT_EN1_CH4_EN_SHIFT 0u
#define EFTU_CCM_TIM_EINT_EN1_CH4_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN1_CH4_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN1_CH4_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN1_CH4_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN1_CH5_EN_MASK 0x3F00u
#define EFTU_CCM_TIM_EINT_EN1_CH5_EN_SHIFT 8u
#define EFTU_CCM_TIM_EINT_EN1_CH5_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN1_CH5_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN1_CH5_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN1_CH5_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN1_CH6_EN_MASK 0x3F0000u
#define EFTU_CCM_TIM_EINT_EN1_CH6_EN_SHIFT 16u
#define EFTU_CCM_TIM_EINT_EN1_CH6_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN1_CH6_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN1_CH6_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN1_CH6_EN_MASK)
#define EFTU_CCM_TIM_EINT_EN1_CH7_EN_MASK 0x3F000000u
#define EFTU_CCM_TIM_EINT_EN1_CH7_EN_SHIFT 24u
#define EFTU_CCM_TIM_EINT_EN1_CH7_EN_WIDTH 6u
#define EFTU_CCM_TIM_EINT_EN1_CH7_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_EN1_CH7_EN_SHIFT))&EFTU_CCM_TIM_EINT_EN1_CH7_EN_MASK)
/* TIM_EINT_EN1 Reg Mask */
#define EFTU_CCM_TIM_EINT_EN1_MASK     0x3F3F3F3Fu

/* TIM_EINT_ST0 Bit Fields */
#define EFTU_CCM_TIM_EINT_ST0_CH0_ST_MASK 0x3Fu
#define EFTU_CCM_TIM_EINT_ST0_CH0_ST_SHIFT 0u
#define EFTU_CCM_TIM_EINT_ST0_CH0_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST0_CH0_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST0_CH0_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST0_CH0_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST0_CH1_ST_MASK 0x3F00u
#define EFTU_CCM_TIM_EINT_ST0_CH1_ST_SHIFT 8u
#define EFTU_CCM_TIM_EINT_ST0_CH1_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST0_CH1_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST0_CH1_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST0_CH1_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST0_CH2_ST_MASK 0x3F0000u
#define EFTU_CCM_TIM_EINT_ST0_CH2_ST_SHIFT 16u
#define EFTU_CCM_TIM_EINT_ST0_CH2_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST0_CH2_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST0_CH2_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST0_CH2_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST0_CH3_ST_MASK 0x3F000000u
#define EFTU_CCM_TIM_EINT_ST0_CH3_ST_SHIFT 24u
#define EFTU_CCM_TIM_EINT_ST0_CH3_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST0_CH3_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST0_CH3_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST0_CH3_ST_MASK)
/* TIM_EINT_ST0 Reg Mask */
#define EFTU_CCM_TIM_EINT_ST0_MASK     0x3F3F3F3Fu

/* TIM_EINT_ST1 Bit Fields */
#define EFTU_CCM_TIM_EINT_ST1_CH4_ST_MASK 0x3Fu
#define EFTU_CCM_TIM_EINT_ST1_CH4_ST_SHIFT 0u
#define EFTU_CCM_TIM_EINT_ST1_CH4_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST1_CH4_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST1_CH4_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST1_CH4_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST1_CH5_ST_MASK 0x3F00u
#define EFTU_CCM_TIM_EINT_ST1_CH5_ST_SHIFT 8u
#define EFTU_CCM_TIM_EINT_ST1_CH5_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST1_CH5_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST1_CH5_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST1_CH5_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST1_CH6_ST_MASK 0x3F0000u
#define EFTU_CCM_TIM_EINT_ST1_CH6_ST_SHIFT 16u
#define EFTU_CCM_TIM_EINT_ST1_CH6_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST1_CH6_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST1_CH6_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST1_CH6_ST_MASK)
#define EFTU_CCM_TIM_EINT_ST1_CH7_ST_MASK 0x3F000000u
#define EFTU_CCM_TIM_EINT_ST1_CH7_ST_SHIFT 24u
#define EFTU_CCM_TIM_EINT_ST1_CH7_ST_WIDTH 6u
#define EFTU_CCM_TIM_EINT_ST1_CH7_ST(x) (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_TIM_EINT_ST1_CH7_ST_SHIFT))&EFTU_CCM_TIM_EINT_ST1_CH7_ST_MASK)
/* TIM_EINT_ST1 Reg Mask */
#define EFTU_CCM_TIM_EINT_ST1_MASK     0x3F3F3F3Fu

/* DMA_ST Bit Fields */
#define EFTU_CCM_DMA_ST_DMA_REQ_MASK   0x3FFFC0u
#define EFTU_CCM_DMA_ST_DMA_REQ_SHIFT  6u
#define EFTU_CCM_DMA_ST_DMA_REQ_WIDTH  16u
#define EFTU_CCM_DMA_ST_DMA_REQ(x)     (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_DMA_ST_DMA_REQ_SHIFT))&EFTU_CCM_DMA_ST_DMA_REQ_MASK)
/* DMA_ST Reg Mask */
#define EFTU_CCM_DMA_ST_MASK           0x003FFFC0u

/* DMA_SRC Bit Fields */
#define EFTU_CCM_DMA_SRC_REQ_0_MASK    0xFFu
#define EFTU_CCM_DMA_SRC_REQ_0_SHIFT   0u
#define EFTU_CCM_DMA_SRC_REQ_0_WIDTH   8u
#define EFTU_CCM_DMA_SRC_REQ_0(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_DMA_SRC_REQ_0_SHIFT))&EFTU_CCM_DMA_SRC_REQ_0_MASK)
#define EFTU_CCM_DMA_SRC_REQ_1_MASK    0xFF0000u
#define EFTU_CCM_DMA_SRC_REQ_1_SHIFT   16u
#define EFTU_CCM_DMA_SRC_REQ_1_WIDTH   8u
#define EFTU_CCM_DMA_SRC_REQ_1(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_CCM_DMA_SRC_REQ_1_SHIFT))&EFTU_CCM_DMA_SRC_REQ_1_MASK)
/* DMA_SRC0 Reg Mask */
#define EFTU_CCM_DMA_SRC_MASK          0x00FF00FFu


/*!
 * @}
 */ /* end of group EFTU_CCM_Register_Masks */

/*!
 * @}
 */ /* end of group EFTU_CCM_Peripheral_Access_Layer */

#endif
