#ifndef _MODULE_SCM_gmbhdijq249_REGS_H_SCM_H_
#define _MODULE_SCM_gmbhdijq249_REGS_H_SCM_H_

/* ----------------------------------------------------------------------------
   -- SCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCM_Peripheral_Access_Layer SCM Peripheral Access Layer
 * @{
 */

/** SCM - Size of Registers Arrays */

/** SCM - Register Layout Typedef */
#define SCM_INT_ROUTER_COUNT 154

typedef struct {

  __I  uint32_t UIDL                          ; /* Unique Identification Register 0, offset: 0x0 */
  __I  uint32_t UIDML                         ; /* Unique Identification Register 1, offset: 0x4 */
  __I  uint32_t UIDMH                         ; /* Unique Identification Register 2, offset: 0x8 */
  __I  uint32_t UIDH                          ; /* Unique Identification Register 3, offset: 0xC */
  __I  uint32_t PARTID0                       ; /* PART ID Register, offset: 0x10 */
       uint8_t  RESERVED_0[4];
  __I  uint32_t CHIPCFG0                      ; /* Chip Configuration Register 0, offset: 0x18 */
  __I  uint32_t CHIPCFG1                      ; /* Chip Configuration Register 1, offset: 0x1C */
  __IO uint32_t MAMECCEN0                     ; /* MAM ECC Enable Register 0, offset: 0x20 */
  __IO uint32_t MAMECCEN1                     ; /* MAM ECC Enable Register 1, offset: 0x24 */
  __IO uint32_t CPU0ECCEN                     ; /* CPU0 ECC Enable Register, offset: 0x28 */
  __IO uint32_t CPU0VTOR                      ; /* CPU0 Vector Table Register, offset: 0x2C */
  __IO uint32_t CPU1ECCEN                     ; /* CPU1 ECC Enable Register, offset: 0x30 */
  __IO uint32_t CPU1VTOR                      ; /* CPU1 Vector Table Register, offset: 0x34 */
  __IO uint32_t CPU2ECCEN                     ; /* CPU2 ECC Enable Register, offset: 0x38 */
  __IO uint32_t CPU2VTOR                      ; /* CPU2 Vector Table Register, offset: 0x3C */
  __IO uint32_t CORE_HOLD                     ; /* Core Hold Register, offset: 0x40 */
       uint8_t  RESERVED_1[12];
  __IO uint32_t FCSPI_ROUTING                 ; /* FCSPI Routing Register, offset: 0x50 */
  __IO uint32_t FCUART_ROUTING0               ; /* FCUART Routing Register 0, offset: 0x54 */
  __IO uint32_t FCUART_ROUTING1               ; /* FCUART Routing Register 1, offset: 0x58 */
  __IO uint32_t ENET_CTRL                     ; /* ENET Control Register, offset: 0x5C */
  __IO uint32_t ADC_ROUTING                   ; /* ADC Routing Register, offset: 0x60 */
  __IO uint32_t FTU_ROUTING                   ; /* FTU Routing Register, offset: 0x64 */
  __IO uint32_t FTU_GTBC                      ; /* FTU Global Time Base Control Register, offset: 0x68 */
  __IO uint32_t FTU_SYNC                      ; /* FTU SYNC Register, offset: 0x6C */
  __IO uint32_t DEBUG_TRACE                   ; /* Debug Trace Register, offset: 0x70 */
  __IO uint32_t SOCMISC                       ; /* SOCMISC Register, offset: 0x74 */
       uint8_t  RESERVED_2[8];
  __I  uint32_t CCM0_STATUS                   ; /* CCM0 Status Register, offset: 0x80 */
  __I  uint32_t CCM1_STATUS                   ; /* CCM1 Status Register, offset: 0x84 */
  __I  uint32_t CCM2_STATUS                   ; /* CCM2 Status Register, offset: 0x88 */
  __I  uint32_t ENET_STATUS                   ; /* ENET Status Register, offset: 0x8C */
  __IO uint32_t SDDF_ROUTING                  ; /* SDDF ROUTING Register, offset: 0x90 */
  __IO uint32_t FLEXCAN_ROUTING               ; /* FLEXCAN Routing Register, offset: 0x94 */
  __IO uint32_t MSC0_ROUTING                  ; /* MSC0 Routing Register, offset: 0x98 */
  __IO uint32_t MSC1_ROUTING                  ; /* MSC1 Routing Register, offset: 0x9C */
  __IO uint32_t PERI_CLKDIV                   ; /* PERI CLKDIV Register, offset: 0xA0 */
  __IO uint32_t FCSMU_SW                      ; /* FCSMU Software Trigger Register, offset: 0xA4 */
  __IO uint32_t ISM_ROUTING                   ; /* ISM Routing Register, offset: 0xA8 */
       uint8_t  RESERVED_3[4];
  __IO uint32_t MATRIX_STATUS0                ; /* Matrix Status Register 0, offset: 0xB0 */
  __IO uint32_t MATRIX_STATUS1                ; /* Matrix Status Register 1, offset: 0xB4 */
  __IO uint32_t MATRIX_STATUS2                ; /* Matrix Status Register 2, offset: 0xB8 */
  __IO uint32_t MATRIX_STATUS3                ; /* Matrix Status Register 3, offset: 0xBC */
  __IO uint32_t MATRIX_STATUS4                ; /* Matrix Status Register 4, offset: 0xC0 */
  __IO uint32_t MATRIX_STATUS5                ; /* Matrix Status Register 5, offset: 0xC4 */
  __IO uint32_t MATRIX_ID_STATUS0             ; /* Matrix Master ID Status Register 0, offset: 0xC8 */
       uint8_t  RESERVED_4[20];
  __IO uint32_t CPU0_TXRX_EN                  ; /* CPU0 TXRX Enable Register, offset: 0xE0 */
  __IO uint32_t CPU1_TXRX_EN                  ; /* CPU1 TXRX Enable Register, offset: 0xE4 */
  __IO uint32_t CPU2_TXRX_EN                  ; /* CPU2 TXRX Enable Register, offset: 0xE8 */
       uint8_t  RESERVED_5[20];
  __IO uint32_t SYSAP_MDO                     ; /* SYSAP MDO Register, offset: 0x100 */
  __I  uint32_t SYSAP_MDI                     ; /* SYSAP MDI Register, offset: 0x104 */
  __I  uint32_t SYSAP_CTRL                    ; /* SYSAP Control Register, offset: 0x108 */
       uint8_t  RESERVED_6[4];
  __IO uint32_t HSM_PCC                       ; /* HSM_PCC Register, offset: 0x110 */
  __I  uint32_t HSM_STATUS                    ; /* HSM Status Register, offset: 0x114 */
  __I  uint32_t MDO_FLAG                      ; /* Mailbox Data Output Flag Register, offset: 0x118 */
       uint8_t  RESERVED_7[4];
  __IO uint32_t MASTER_HALT_REQ               ; /* Master Halt Request Register, offset: 0x120 */
  __I  uint32_t MASTER_HALT_ACK               ; /* MASTER Halt ACK Register, offset: 0x124 */
       uint8_t  RESERVED_8[212];
  __IO uint32_t INT_ROUTER_NMI                ; /* NMI Interrupt Router Register, offset: 0x1FC */
  __IO uint32_t INT_ROUTER[SCM_INT_ROUTER_COUNT]; /* NVIC Interrupt Router Register, offset: 0x200 */
       uint8_t  RESERVED_9[920];
  __IO uint32_t CRCCSR                        ; /* CRC Control Status Register, offset: 0x800 */
  __I  uint32_t CRCRES                        ; /* CRC Result Register, offset: 0x804 */

} SCM_Type, *SCM_MemMapPtr;


/* SCM - Peripheral instance base addresses */
/** Peripheral SCM base address */
#define SCM_BASE                                 (0x40072000u)
/** Peripheral SCM base pointer */
#define SCM                                      ((SCM_Type *)SCM_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the SCM module. */
//#define SCM_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the SCM module. */
//#define SCM_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the SCM peripheral type */
//#define SCM_IRQS                                 {SCM_IRQn}


/* ----------------------------------------------------------------------------
   -- SCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCM_Register_Masks SCM Register Masks
 * @{
 */

/* UIDL Bit Fields */
#define SCM_UIDL_UIDL_MASK             0xFFFFFFFFu
#define SCM_UIDL_UIDL_SHIFT            0u
#define SCM_UIDL_UIDL_WIDTH            32u
#define SCM_UIDL_UIDL(x)               (((uint32_t)(((uint32_t)(x))<<SCM_UIDL_UIDL_SHIFT))&SCM_UIDL_UIDL_MASK)
/* UIDL Reg Mask */
#define SCM_UIDL_MASK                  0xFFFFFFFFu

/* UIDML Bit Fields */
#define SCM_UIDML_UIDML_MASK           0xFFFFFFFFu
#define SCM_UIDML_UIDML_SHIFT          0u
#define SCM_UIDML_UIDML_WIDTH          32u
#define SCM_UIDML_UIDML(x)             (((uint32_t)(((uint32_t)(x))<<SCM_UIDML_UIDML_SHIFT))&SCM_UIDML_UIDML_MASK)
/* UIDML Reg Mask */
#define SCM_UIDML_MASK                 0xFFFFFFFFu

/* UIDMH Bit Fields */
#define SCM_UIDMH_UDMH_MASK            0xFFFFFFFFu
#define SCM_UIDMH_UDMH_SHIFT           0u
#define SCM_UIDMH_UDMH_WIDTH           32u
#define SCM_UIDMH_UDMH(x)              (((uint32_t)(((uint32_t)(x))<<SCM_UIDMH_UDMH_SHIFT))&SCM_UIDMH_UDMH_MASK)
/* UIDMH Reg Mask */
#define SCM_UIDMH_MASK                 0xFFFFFFFFu

/* UIDH Bit Fields */
#define SCM_UIDH_UIDH_MASK             0xFFFFFFFFu
#define SCM_UIDH_UIDH_SHIFT            0u
#define SCM_UIDH_UIDH_WIDTH            32u
#define SCM_UIDH_UIDH(x)               (((uint32_t)(((uint32_t)(x))<<SCM_UIDH_UIDH_SHIFT))&SCM_UIDH_UIDH_MASK)
/* UIDH Reg Mask */
#define SCM_UIDH_MASK                  0xFFFFFFFFu

/* PARTID0 Bit Fields */
#define SCM_PARTID0_FAM_ID_MASK        0xFF0u
#define SCM_PARTID0_FAM_ID_SHIFT       4u
#define SCM_PARTID0_FAM_ID_WIDTH       8u
#define SCM_PARTID0_FAM_ID(x)          (((uint32_t)(((uint32_t)(x))<<SCM_PARTID0_FAM_ID_SHIFT))&SCM_PARTID0_FAM_ID_MASK)
#define SCM_PARTID0_REVID_MASK         0xFu
#define SCM_PARTID0_REVID_SHIFT        0u
#define SCM_PARTID0_REVID_WIDTH        4u
#define SCM_PARTID0_REVID(x)           (((uint32_t)(((uint32_t)(x))<<SCM_PARTID0_REVID_SHIFT))&SCM_PARTID0_REVID_MASK)
/* PARTID0 Reg Mask */
#define SCM_PARTID0_MASK               0x00000FFFu

/* CHIPCFG0 Bit Fields */
#define SCM_CHIPCFG0_CPU1_LOCKSTEP_EN_MASK 0x80000000u
#define SCM_CHIPCFG0_CPU1_LOCKSTEP_EN_SHIFT 31u
#define SCM_CHIPCFG0_CPU1_LOCKSTEP_EN_WIDTH 1u
#define SCM_CHIPCFG0_CPU1_LOCKSTEP_EN(x) (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_CPU1_LOCKSTEP_EN_SHIFT))&SCM_CHIPCFG0_CPU1_LOCKSTEP_EN_MASK)
#define SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_MASK 0x40000000u
#define SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_SHIFT 30u
#define SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_WIDTH 1u
#define SCM_CHIPCFG0_CPU0_LOCKSTEP_EN(x) (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_SHIFT))&SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_MASK)
#define SCM_CHIPCFG0_OSPI_MASK         0x4000u
#define SCM_CHIPCFG0_OSPI_SHIFT        14u
#define SCM_CHIPCFG0_OSPI_WIDTH        1u
#define SCM_CHIPCFG0_OSPI(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_OSPI_SHIFT))&SCM_CHIPCFG0_OSPI_MASK)
#define SCM_CHIPCFG0_ENET_MASK         0x200u
#define SCM_CHIPCFG0_ENET_SHIFT        9u
#define SCM_CHIPCFG0_ENET_WIDTH        1u
#define SCM_CHIPCFG0_ENET(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_ENET_SHIFT))&SCM_CHIPCFG0_ENET_MASK)
#define SCM_CHIPCFG0_CAN_FD_MASK       0x100u
#define SCM_CHIPCFG0_CAN_FD_SHIFT      8u
#define SCM_CHIPCFG0_CAN_FD_WIDTH      1u
#define SCM_CHIPCFG0_CAN_FD(x)         (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_CAN_FD_SHIFT))&SCM_CHIPCFG0_CAN_FD_MASK)
#define SCM_CHIPCFG0_FLEXCAN_NUM_MASK  0x7u
#define SCM_CHIPCFG0_FLEXCAN_NUM_SHIFT 0u
#define SCM_CHIPCFG0_FLEXCAN_NUM_WIDTH 3u
#define SCM_CHIPCFG0_FLEXCAN_NUM(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG0_FLEXCAN_NUM_SHIFT))&SCM_CHIPCFG0_FLEXCAN_NUM_MASK)
/* CHIPCFG0 Reg Mask */
#define SCM_CHIPCFG0_MASK              0xC0004307u

/* CHIPCFG1 Bit Fields */
#define SCM_CHIPCFG1_DEVICE_ID_MASK    0xFFFFFFF0u
#define SCM_CHIPCFG1_DEVICE_ID_SHIFT   4u
#define SCM_CHIPCFG1_DEVICE_ID_WIDTH   28u
#define SCM_CHIPCFG1_DEVICE_ID(x)      (((uint32_t)(((uint32_t)(x))<<SCM_CHIPCFG1_DEVICE_ID_SHIFT))&SCM_CHIPCFG1_DEVICE_ID_MASK)
/* CHIPCFG1 Reg Mask */
#define SCM_CHIPCFG1_MASK              0xFFFFFFF0u

/* MAMECCEN0 Bit Fields */
#define SCM_MAMECCEN0_WPB_LOCK_MASK    0x80000000u
#define SCM_MAMECCEN0_WPB_LOCK_SHIFT   31u
#define SCM_MAMECCEN0_WPB_LOCK_WIDTH   1u
#define SCM_MAMECCEN0_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_WPB_LOCK_SHIFT))&SCM_MAMECCEN0_WPB_LOCK_MASK)
#define SCM_MAMECCEN0_WPB_MASK         0x70000000u
#define SCM_MAMECCEN0_WPB_SHIFT        28u
#define SCM_MAMECCEN0_WPB_WIDTH        3u
#define SCM_MAMECCEN0_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_WPB_SHIFT))&SCM_MAMECCEN0_WPB_MASK)
#define SCM_MAMECCEN0_SRAM2_ECC_MASK   0xC000000u
#define SCM_MAMECCEN0_SRAM2_ECC_SHIFT  26u
#define SCM_MAMECCEN0_SRAM2_ECC_WIDTH  2u
#define SCM_MAMECCEN0_SRAM2_ECC(x)     (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_SRAM2_ECC_SHIFT))&SCM_MAMECCEN0_SRAM2_ECC_MASK)
#define SCM_MAMECCEN0_SRAM1_ECC_MASK   0x3000000u
#define SCM_MAMECCEN0_SRAM1_ECC_SHIFT  24u
#define SCM_MAMECCEN0_SRAM1_ECC_WIDTH  2u
#define SCM_MAMECCEN0_SRAM1_ECC(x)     (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_SRAM1_ECC_SHIFT))&SCM_MAMECCEN0_SRAM1_ECC_MASK)
#define SCM_MAMECCEN0_SRAM0_ECC_MASK   0xC00000u
#define SCM_MAMECCEN0_SRAM0_ECC_SHIFT  22u
#define SCM_MAMECCEN0_SRAM0_ECC_WIDTH  2u
#define SCM_MAMECCEN0_SRAM0_ECC(x)     (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_SRAM0_ECC_SHIFT))&SCM_MAMECCEN0_SRAM0_ECC_MASK)
#define SCM_MAMECCEN0_MAM2_S2_ECC_MASK 0x300000u
#define SCM_MAMECCEN0_MAM2_S2_ECC_SHIFT 20u
#define SCM_MAMECCEN0_MAM2_S2_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM2_S2_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM2_S2_ECC_SHIFT))&SCM_MAMECCEN0_MAM2_S2_ECC_MASK)
#define SCM_MAMECCEN0_MAM2_S1_ECC_MASK 0xC0000u
#define SCM_MAMECCEN0_MAM2_S1_ECC_SHIFT 18u
#define SCM_MAMECCEN0_MAM2_S1_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM2_S1_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM2_S1_ECC_SHIFT))&SCM_MAMECCEN0_MAM2_S1_ECC_MASK)
#define SCM_MAMECCEN0_MAM2_S0_ECC_MASK 0x30000u
#define SCM_MAMECCEN0_MAM2_S0_ECC_SHIFT 16u
#define SCM_MAMECCEN0_MAM2_S0_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM2_S0_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM2_S0_ECC_SHIFT))&SCM_MAMECCEN0_MAM2_S0_ECC_MASK)
#define SCM_MAMECCEN0_MAM1_S3_ECC_MASK 0xC000u
#define SCM_MAMECCEN0_MAM1_S3_ECC_SHIFT 14u
#define SCM_MAMECCEN0_MAM1_S3_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM1_S3_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM1_S3_ECC_SHIFT))&SCM_MAMECCEN0_MAM1_S3_ECC_MASK)
#define SCM_MAMECCEN0_MAM1_S2_ECC_MASK 0x3000u
#define SCM_MAMECCEN0_MAM1_S2_ECC_SHIFT 12u
#define SCM_MAMECCEN0_MAM1_S2_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM1_S2_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM1_S2_ECC_SHIFT))&SCM_MAMECCEN0_MAM1_S2_ECC_MASK)
#define SCM_MAMECCEN0_MAM1_S1_ECC_MASK 0xC00u
#define SCM_MAMECCEN0_MAM1_S1_ECC_SHIFT 10u
#define SCM_MAMECCEN0_MAM1_S1_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM1_S1_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM1_S1_ECC_SHIFT))&SCM_MAMECCEN0_MAM1_S1_ECC_MASK)
#define SCM_MAMECCEN0_MAM1_S0_ECC_MASK 0x300u
#define SCM_MAMECCEN0_MAM1_S0_ECC_SHIFT 8u
#define SCM_MAMECCEN0_MAM1_S0_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM1_S0_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM1_S0_ECC_SHIFT))&SCM_MAMECCEN0_MAM1_S0_ECC_MASK)
#define SCM_MAMECCEN0_MAM0_S3_ECC_MASK 0xC0u
#define SCM_MAMECCEN0_MAM0_S3_ECC_SHIFT 6u
#define SCM_MAMECCEN0_MAM0_S3_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM0_S3_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM0_S3_ECC_SHIFT))&SCM_MAMECCEN0_MAM0_S3_ECC_MASK)
#define SCM_MAMECCEN0_MAM0_S2_ECC_MASK 0x30u
#define SCM_MAMECCEN0_MAM0_S2_ECC_SHIFT 4u
#define SCM_MAMECCEN0_MAM0_S2_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM0_S2_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM0_S2_ECC_SHIFT))&SCM_MAMECCEN0_MAM0_S2_ECC_MASK)
#define SCM_MAMECCEN0_MAM0_S1_ECC_MASK 0xCu
#define SCM_MAMECCEN0_MAM0_S1_ECC_SHIFT 2u
#define SCM_MAMECCEN0_MAM0_S1_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM0_S1_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM0_S1_ECC_SHIFT))&SCM_MAMECCEN0_MAM0_S1_ECC_MASK)
#define SCM_MAMECCEN0_MAM0_S0_ECC_MASK 0x3u
#define SCM_MAMECCEN0_MAM0_S0_ECC_SHIFT 0u
#define SCM_MAMECCEN0_MAM0_S0_ECC_WIDTH 2u
#define SCM_MAMECCEN0_MAM0_S0_ECC(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN0_MAM0_S0_ECC_SHIFT))&SCM_MAMECCEN0_MAM0_S0_ECC_MASK)
/* MAMECCEN0 Reg Mask */
#define SCM_MAMECCEN0_MASK             0xFFFFFFFFu

/* MAMECCEN1 Bit Fields */
#define SCM_MAMECCEN1_WPB_LOCK_MASK    0x80000000u
#define SCM_MAMECCEN1_WPB_LOCK_SHIFT   31u
#define SCM_MAMECCEN1_WPB_LOCK_WIDTH   1u
#define SCM_MAMECCEN1_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_WPB_LOCK_SHIFT))&SCM_MAMECCEN1_WPB_LOCK_MASK)
#define SCM_MAMECCEN1_WPB_MASK         0x70000000u
#define SCM_MAMECCEN1_WPB_SHIFT        28u
#define SCM_MAMECCEN1_WPB_WIDTH        3u
#define SCM_MAMECCEN1_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_WPB_SHIFT))&SCM_MAMECCEN1_WPB_MASK)
#define SCM_MAMECCEN1_DMA1_CFG_ECC_MASK 0x200u
#define SCM_MAMECCEN1_DMA1_CFG_ECC_SHIFT 9u
#define SCM_MAMECCEN1_DMA1_CFG_ECC_WIDTH 1u
#define SCM_MAMECCEN1_DMA1_CFG_ECC(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_DMA1_CFG_ECC_SHIFT))&SCM_MAMECCEN1_DMA1_CFG_ECC_MASK)
#define SCM_MAMECCEN1_DMA0_CFG_ECC_MASK 0x100u
#define SCM_MAMECCEN1_DMA0_CFG_ECC_SHIFT 8u
#define SCM_MAMECCEN1_DMA0_CFG_ECC_WIDTH 1u
#define SCM_MAMECCEN1_DMA0_CFG_ECC(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_DMA0_CFG_ECC_SHIFT))&SCM_MAMECCEN1_DMA0_CFG_ECC_MASK)
#define SCM_MAMECCEN1_DMA1_ECC_MASK    0xC0u
#define SCM_MAMECCEN1_DMA1_ECC_SHIFT   6u
#define SCM_MAMECCEN1_DMA1_ECC_WIDTH   2u
#define SCM_MAMECCEN1_DMA1_ECC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_DMA1_ECC_SHIFT))&SCM_MAMECCEN1_DMA1_ECC_MASK)
#define SCM_MAMECCEN1_DMA0_ECC_MASK    0x30u
#define SCM_MAMECCEN1_DMA0_ECC_SHIFT   4u
#define SCM_MAMECCEN1_DMA0_ECC_WIDTH   2u
#define SCM_MAMECCEN1_DMA0_ECC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_DMA0_ECC_SHIFT))&SCM_MAMECCEN1_DMA0_ECC_MASK)
#define SCM_MAMECCEN1_ENET_ECC_MASK    0xCu
#define SCM_MAMECCEN1_ENET_ECC_SHIFT   2u
#define SCM_MAMECCEN1_ENET_ECC_WIDTH   2u
#define SCM_MAMECCEN1_ENET_ECC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_ENET_ECC_SHIFT))&SCM_MAMECCEN1_ENET_ECC_MASK)
#define SCM_MAMECCEN1_HSM_ECC_MASK     0x3u
#define SCM_MAMECCEN1_HSM_ECC_SHIFT    0u
#define SCM_MAMECCEN1_HSM_ECC_WIDTH    2u
#define SCM_MAMECCEN1_HSM_ECC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_MAMECCEN1_HSM_ECC_SHIFT))&SCM_MAMECCEN1_HSM_ECC_MASK)
/* MAMECCEN1 Reg Mask */
#define SCM_MAMECCEN1_MASK             0xF00003FFu

/* CPU0ECCEN Bit Fields */
#define SCM_CPU0ECCEN_WPB_LOCK_MASK    0x80000000u
#define SCM_CPU0ECCEN_WPB_LOCK_SHIFT   31u
#define SCM_CPU0ECCEN_WPB_LOCK_WIDTH   1u
#define SCM_CPU0ECCEN_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_WPB_LOCK_SHIFT))&SCM_CPU0ECCEN_WPB_LOCK_MASK)
#define SCM_CPU0ECCEN_WPB_MASK         0x70000000u
#define SCM_CPU0ECCEN_WPB_SHIFT        28u
#define SCM_CPU0ECCEN_WPB_WIDTH        3u
#define SCM_CPU0ECCEN_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_WPB_SHIFT))&SCM_CPU0ECCEN_WPB_MASK)
#define SCM_CPU0ECCEN_CPU0_ITCM_ECC_MASK 0xC00u
#define SCM_CPU0ECCEN_CPU0_ITCM_ECC_SHIFT 10u
#define SCM_CPU0ECCEN_CPU0_ITCM_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_ITCM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_ITCM_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_ITCM_ECC_MASK)
#define SCM_CPU0ECCEN_CPU0_DTCM1_ECC_MASK 0x300u
#define SCM_CPU0ECCEN_CPU0_DTCM1_ECC_SHIFT 8u
#define SCM_CPU0ECCEN_CPU0_DTCM1_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_DTCM1_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_DTCM1_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_DTCM1_ECC_MASK)
#define SCM_CPU0ECCEN_CPU0_DTCM0_ECC_MASK 0xC0u
#define SCM_CPU0ECCEN_CPU0_DTCM0_ECC_SHIFT 6u
#define SCM_CPU0ECCEN_CPU0_DTCM0_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_DTCM0_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_DTCM0_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_DTCM0_ECC_MASK)
#define SCM_CPU0ECCEN_CPU0_AHBS_ECC_MASK 0x30u
#define SCM_CPU0ECCEN_CPU0_AHBS_ECC_SHIFT 4u
#define SCM_CPU0ECCEN_CPU0_AHBS_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_AHBS_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_AHBS_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_AHBS_ECC_MASK)
#define SCM_CPU0ECCEN_CPU0_AHBP_ECC_MASK 0xCu
#define SCM_CPU0ECCEN_CPU0_AHBP_ECC_SHIFT 2u
#define SCM_CPU0ECCEN_CPU0_AHBP_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_AHBP_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_AHBP_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_AHBP_ECC_MASK)
#define SCM_CPU0ECCEN_CPU0_AHBM_ECC_MASK 0x3u
#define SCM_CPU0ECCEN_CPU0_AHBM_ECC_SHIFT 0u
#define SCM_CPU0ECCEN_CPU0_AHBM_ECC_WIDTH 2u
#define SCM_CPU0ECCEN_CPU0_AHBM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0ECCEN_CPU0_AHBM_ECC_SHIFT))&SCM_CPU0ECCEN_CPU0_AHBM_ECC_MASK)
/* CPU0ECCEN Reg Mask */
#define SCM_CPU0ECCEN_MASK             0xF0000FFFu

/* CPU0VTOR Bit Fields */
#define SCM_CPU0VTOR_CPU0_INIT_VECTOR_MASK 0xFFFFFF8u
#define SCM_CPU0VTOR_CPU0_INIT_VECTOR_SHIFT 3u
#define SCM_CPU0VTOR_CPU0_INIT_VECTOR_WIDTH 25u
#define SCM_CPU0VTOR_CPU0_INIT_VECTOR(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU0VTOR_CPU0_INIT_VECTOR_SHIFT))&SCM_CPU0VTOR_CPU0_INIT_VECTOR_MASK)
/* CPU0VTOR Reg Mask */
#define SCM_CPU0VTOR_MASK              0x0FFFFFF8u

/* CPU1ECCEN Bit Fields */
#define SCM_CPU1ECCEN_WPB_LOCK_MASK    0x80000000u
#define SCM_CPU1ECCEN_WPB_LOCK_SHIFT   31u
#define SCM_CPU1ECCEN_WPB_LOCK_WIDTH   1u
#define SCM_CPU1ECCEN_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_WPB_LOCK_SHIFT))&SCM_CPU1ECCEN_WPB_LOCK_MASK)
#define SCM_CPU1ECCEN_WPB_MASK         0x70000000u
#define SCM_CPU1ECCEN_WPB_SHIFT        28u
#define SCM_CPU1ECCEN_WPB_WIDTH        3u
#define SCM_CPU1ECCEN_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_WPB_SHIFT))&SCM_CPU1ECCEN_WPB_MASK)
#define SCM_CPU1ECCEN_CPU1_ITCM_ECC_MASK 0xC00u
#define SCM_CPU1ECCEN_CPU1_ITCM_ECC_SHIFT 10u
#define SCM_CPU1ECCEN_CPU1_ITCM_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_ITCM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_ITCM_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_ITCM_ECC_MASK)
#define SCM_CPU1ECCEN_CPU1_DTCM1_ECC_MASK 0x300u
#define SCM_CPU1ECCEN_CPU1_DTCM1_ECC_SHIFT 8u
#define SCM_CPU1ECCEN_CPU1_DTCM1_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_DTCM1_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_DTCM1_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_DTCM1_ECC_MASK)
#define SCM_CPU1ECCEN_CPU1_DTCM0_ECC_MASK 0xC0u
#define SCM_CPU1ECCEN_CPU1_DTCM0_ECC_SHIFT 6u
#define SCM_CPU1ECCEN_CPU1_DTCM0_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_DTCM0_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_DTCM0_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_DTCM0_ECC_MASK)
#define SCM_CPU1ECCEN_CPU1_AHBS_ECC_MASK 0x30u
#define SCM_CPU1ECCEN_CPU1_AHBS_ECC_SHIFT 4u
#define SCM_CPU1ECCEN_CPU1_AHBS_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_AHBS_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_AHBS_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_AHBS_ECC_MASK)
#define SCM_CPU1ECCEN_CPU1_AHBP_ECC_MASK 0xCu
#define SCM_CPU1ECCEN_CPU1_AHBP_ECC_SHIFT 2u
#define SCM_CPU1ECCEN_CPU1_AHBP_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_AHBP_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_AHBP_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_AHBP_ECC_MASK)
#define SCM_CPU1ECCEN_CPU1_AHBM_ECC_MASK 0x3u
#define SCM_CPU1ECCEN_CPU1_AHBM_ECC_SHIFT 0u
#define SCM_CPU1ECCEN_CPU1_AHBM_ECC_WIDTH 2u
#define SCM_CPU1ECCEN_CPU1_AHBM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1ECCEN_CPU1_AHBM_ECC_SHIFT))&SCM_CPU1ECCEN_CPU1_AHBM_ECC_MASK)
/* CPU1ECCEN Reg Mask */
#define SCM_CPU1ECCEN_MASK             0xF0000FFFu

/* CPU1VTOR Bit Fields */
#define SCM_CPU1VTOR_WPB_LOCK_MASK     0x80000000u
#define SCM_CPU1VTOR_WPB_LOCK_SHIFT    31u
#define SCM_CPU1VTOR_WPB_LOCK_WIDTH    1u
#define SCM_CPU1VTOR_WPB_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<SCM_CPU1VTOR_WPB_LOCK_SHIFT))&SCM_CPU1VTOR_WPB_LOCK_MASK)
#define SCM_CPU1VTOR_WPB_MASK          0x70000000u
#define SCM_CPU1VTOR_WPB_SHIFT         28u
#define SCM_CPU1VTOR_WPB_WIDTH         3u
#define SCM_CPU1VTOR_WPB(x)            (((uint32_t)(((uint32_t)(x))<<SCM_CPU1VTOR_WPB_SHIFT))&SCM_CPU1VTOR_WPB_MASK)
#define SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK 0xFFFFFF8u
#define SCM_CPU1VTOR_CPU1_INIT_VECTOR_SHIFT 3u
#define SCM_CPU1VTOR_CPU1_INIT_VECTOR_WIDTH 25u
#define SCM_CPU1VTOR_CPU1_INIT_VECTOR(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU1VTOR_CPU1_INIT_VECTOR_SHIFT))&SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK)
/* CPU1VTOR Reg Mask */
#define SCM_CPU1VTOR_MASK              0xFFFFFFF8u

/* CPU2ECCEN Bit Fields */
#define SCM_CPU2ECCEN_WPB_LOCK_MASK    0x80000000u
#define SCM_CPU2ECCEN_WPB_LOCK_SHIFT   31u
#define SCM_CPU2ECCEN_WPB_LOCK_WIDTH   1u
#define SCM_CPU2ECCEN_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_WPB_LOCK_SHIFT))&SCM_CPU2ECCEN_WPB_LOCK_MASK)
#define SCM_CPU2ECCEN_WPB_MASK         0x70000000u
#define SCM_CPU2ECCEN_WPB_SHIFT        28u
#define SCM_CPU2ECCEN_WPB_WIDTH        3u
#define SCM_CPU2ECCEN_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_WPB_SHIFT))&SCM_CPU2ECCEN_WPB_MASK)
#define SCM_CPU2ECCEN_CPU2_ITCM_ECC_MASK 0xC00u
#define SCM_CPU2ECCEN_CPU2_ITCM_ECC_SHIFT 10u
#define SCM_CPU2ECCEN_CPU2_ITCM_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_ITCM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_ITCM_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_ITCM_ECC_MASK)
#define SCM_CPU2ECCEN_CPU2_DTCM1_ECC_MASK 0x300u
#define SCM_CPU2ECCEN_CPU2_DTCM1_ECC_SHIFT 8u
#define SCM_CPU2ECCEN_CPU2_DTCM1_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_DTCM1_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_DTCM1_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_DTCM1_ECC_MASK)
#define SCM_CPU2ECCEN_CPU2_DTCM0_ECC_MASK 0xC0u
#define SCM_CPU2ECCEN_CPU2_DTCM0_ECC_SHIFT 6u
#define SCM_CPU2ECCEN_CPU2_DTCM0_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_DTCM0_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_DTCM0_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_DTCM0_ECC_MASK)
#define SCM_CPU2ECCEN_CPU2_AHBS_ECC_MASK 0x30u
#define SCM_CPU2ECCEN_CPU2_AHBS_ECC_SHIFT 4u
#define SCM_CPU2ECCEN_CPU2_AHBS_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_AHBS_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_AHBS_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_AHBS_ECC_MASK)
#define SCM_CPU2ECCEN_CPU2_AHBP_ECC_MASK 0xCu
#define SCM_CPU2ECCEN_CPU2_AHBP_ECC_SHIFT 2u
#define SCM_CPU2ECCEN_CPU2_AHBP_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_AHBP_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_AHBP_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_AHBP_ECC_MASK)
#define SCM_CPU2ECCEN_CPU2_AHBM_ECC_MASK 0x3u
#define SCM_CPU2ECCEN_CPU2_AHBM_ECC_SHIFT 0u
#define SCM_CPU2ECCEN_CPU2_AHBM_ECC_WIDTH 2u
#define SCM_CPU2ECCEN_CPU2_AHBM_ECC(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2ECCEN_CPU2_AHBM_ECC_SHIFT))&SCM_CPU2ECCEN_CPU2_AHBM_ECC_MASK)
/* CPU2ECCEN Reg Mask */
#define SCM_CPU2ECCEN_MASK             0xF0000FFFu

/* CPU2VTOR Bit Fields */
#define SCM_CPU2VTOR_WPB_LOCK_MASK     0x80000000u
#define SCM_CPU2VTOR_WPB_LOCK_SHIFT    31u
#define SCM_CPU2VTOR_WPB_LOCK_WIDTH    1u
#define SCM_CPU2VTOR_WPB_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<SCM_CPU2VTOR_WPB_LOCK_SHIFT))&SCM_CPU2VTOR_WPB_LOCK_MASK)
#define SCM_CPU2VTOR_WPB_MASK          0x70000000u
#define SCM_CPU2VTOR_WPB_SHIFT         28u
#define SCM_CPU2VTOR_WPB_WIDTH         3u
#define SCM_CPU2VTOR_WPB(x)            (((uint32_t)(((uint32_t)(x))<<SCM_CPU2VTOR_WPB_SHIFT))&SCM_CPU2VTOR_WPB_MASK)
#define SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK 0xFFFFFF8u
#define SCM_CPU2VTOR_CPU2_INIT_VECTOR_SHIFT 3u
#define SCM_CPU2VTOR_CPU2_INIT_VECTOR_WIDTH 25u
#define SCM_CPU2VTOR_CPU2_INIT_VECTOR(x) (((uint32_t)(((uint32_t)(x))<<SCM_CPU2VTOR_CPU2_INIT_VECTOR_SHIFT))&SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK)
/* CPU2VTOR Reg Mask */
#define SCM_CPU2VTOR_MASK              0xFFFFFFF8u

/* CORE_HOLD Bit Fields */
#define SCM_CORE_HOLD_WPB_LOCK_MASK    0x80000000u
#define SCM_CORE_HOLD_WPB_LOCK_SHIFT   31u
#define SCM_CORE_HOLD_WPB_LOCK_WIDTH   1u
#define SCM_CORE_HOLD_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_CORE_HOLD_WPB_LOCK_SHIFT))&SCM_CORE_HOLD_WPB_LOCK_MASK)
#define SCM_CORE_HOLD_WPB_MASK         0x70000000u
#define SCM_CORE_HOLD_WPB_SHIFT        28u
#define SCM_CORE_HOLD_WPB_WIDTH        3u
#define SCM_CORE_HOLD_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CORE_HOLD_WPB_SHIFT))&SCM_CORE_HOLD_WPB_MASK)
#define SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK 0x4u
#define SCM_CORE_HOLD_CPU2_CORE_HOLD_SHIFT 2u
#define SCM_CORE_HOLD_CPU2_CORE_HOLD_WIDTH 1u
#define SCM_CORE_HOLD_CPU2_CORE_HOLD(x) (((uint32_t)(((uint32_t)(x))<<SCM_CORE_HOLD_CPU2_CORE_HOLD_SHIFT))&SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK)
#define SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK 0x2u
#define SCM_CORE_HOLD_CPU1_CORE_HOLD_SHIFT 1u
#define SCM_CORE_HOLD_CPU1_CORE_HOLD_WIDTH 1u
#define SCM_CORE_HOLD_CPU1_CORE_HOLD(x) (((uint32_t)(((uint32_t)(x))<<SCM_CORE_HOLD_CPU1_CORE_HOLD_SHIFT))&SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK)
/* CORE_HOLD Reg Mask */
#define SCM_CORE_HOLD_MASK             0xF0000006u

/* FCSPI_ROUTING Bit Fields */
#define SCM_FCSPI_ROUTING_SPI7_ROUTING_MASK 0x70000000u
#define SCM_FCSPI_ROUTING_SPI7_ROUTING_SHIFT 28u
#define SCM_FCSPI_ROUTING_SPI7_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI7_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI7_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI7_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI6_ROUTING_MASK 0x7000000u
#define SCM_FCSPI_ROUTING_SPI6_ROUTING_SHIFT 24u
#define SCM_FCSPI_ROUTING_SPI6_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI6_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI6_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI6_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI5_ROUTING_MASK 0x700000u
#define SCM_FCSPI_ROUTING_SPI5_ROUTING_SHIFT 20u
#define SCM_FCSPI_ROUTING_SPI5_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI5_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI5_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI5_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI4_ROUTING_MASK 0x70000u
#define SCM_FCSPI_ROUTING_SPI4_ROUTING_SHIFT 16u
#define SCM_FCSPI_ROUTING_SPI4_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI4_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI4_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI4_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI3_ROUTING_MASK 0x7000u
#define SCM_FCSPI_ROUTING_SPI3_ROUTING_SHIFT 12u
#define SCM_FCSPI_ROUTING_SPI3_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI3_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI3_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI3_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI2_ROUTING_MASK 0x700u
#define SCM_FCSPI_ROUTING_SPI2_ROUTING_SHIFT 8u
#define SCM_FCSPI_ROUTING_SPI2_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI2_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI2_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI2_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI1_ROUTING_MASK 0x70u
#define SCM_FCSPI_ROUTING_SPI1_ROUTING_SHIFT 4u
#define SCM_FCSPI_ROUTING_SPI1_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI1_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI1_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI1_ROUTING_MASK)
#define SCM_FCSPI_ROUTING_SPI0_ROUTING_MASK 0x7u
#define SCM_FCSPI_ROUTING_SPI0_ROUTING_SHIFT 0u
#define SCM_FCSPI_ROUTING_SPI0_ROUTING_WIDTH 3u
#define SCM_FCSPI_ROUTING_SPI0_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCSPI_ROUTING_SPI0_ROUTING_SHIFT))&SCM_FCSPI_ROUTING_SPI0_ROUTING_MASK)
/* FCSPI_ROUTING Reg Mask */
#define SCM_FCSPI_ROUTING_MASK         0x77777777u

/* FCUART_ROUTING0 Bit Fields */
#define SCM_FCUART_ROUTING0_UART7_ROUTING_MASK 0xF0000000u
#define SCM_FCUART_ROUTING0_UART7_ROUTING_SHIFT 28u
#define SCM_FCUART_ROUTING0_UART7_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART7_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART7_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART7_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART6_ROUTING_MASK 0xF000000u
#define SCM_FCUART_ROUTING0_UART6_ROUTING_SHIFT 24u
#define SCM_FCUART_ROUTING0_UART6_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART6_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART6_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART6_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART5_ROUTING_MASK 0xF00000u
#define SCM_FCUART_ROUTING0_UART5_ROUTING_SHIFT 20u
#define SCM_FCUART_ROUTING0_UART5_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART5_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART5_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART5_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART4_ROUTING_MASK 0xF0000u
#define SCM_FCUART_ROUTING0_UART4_ROUTING_SHIFT 16u
#define SCM_FCUART_ROUTING0_UART4_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART4_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART4_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART4_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART3_ROUTING_MASK 0xF000u
#define SCM_FCUART_ROUTING0_UART3_ROUTING_SHIFT 12u
#define SCM_FCUART_ROUTING0_UART3_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART3_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART3_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART3_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART2_ROUTING_MASK 0xF00u
#define SCM_FCUART_ROUTING0_UART2_ROUTING_SHIFT 8u
#define SCM_FCUART_ROUTING0_UART2_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART2_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART2_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART2_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART1_ROUTING_MASK 0xF0u
#define SCM_FCUART_ROUTING0_UART1_ROUTING_SHIFT 4u
#define SCM_FCUART_ROUTING0_UART1_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART1_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART1_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART1_ROUTING_MASK)
#define SCM_FCUART_ROUTING0_UART0_ROUTING_MASK 0xFu
#define SCM_FCUART_ROUTING0_UART0_ROUTING_SHIFT 0u
#define SCM_FCUART_ROUTING0_UART0_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING0_UART0_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING0_UART0_ROUTING_SHIFT))&SCM_FCUART_ROUTING0_UART0_ROUTING_MASK)
/* FCUART_ROUTING0 Reg Mask */
#define SCM_FCUART_ROUTING0_MASK       0xFFFFFFFFu

/* FCUART_ROUTING1 Bit Fields */
#define SCM_FCUART_ROUTING1_UART15_ROUTING_MASK 0xF0000000u
#define SCM_FCUART_ROUTING1_UART15_ROUTING_SHIFT 28u
#define SCM_FCUART_ROUTING1_UART15_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART15_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART15_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART15_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART14_ROUTING_MASK 0xF000000u
#define SCM_FCUART_ROUTING1_UART14_ROUTING_SHIFT 24u
#define SCM_FCUART_ROUTING1_UART14_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART14_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART14_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART14_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART13_ROUTING_MASK 0xF00000u
#define SCM_FCUART_ROUTING1_UART13_ROUTING_SHIFT 20u
#define SCM_FCUART_ROUTING1_UART13_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART13_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART13_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART13_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART12_ROUTING_MASK 0xF0000u
#define SCM_FCUART_ROUTING1_UART12_ROUTING_SHIFT 16u
#define SCM_FCUART_ROUTING1_UART12_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART12_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART12_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART12_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART11_ROUTING_MASK 0xF000u
#define SCM_FCUART_ROUTING1_UART11_ROUTING_SHIFT 12u
#define SCM_FCUART_ROUTING1_UART11_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART11_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART11_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART11_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART10_ROUTING_MASK 0xF00u
#define SCM_FCUART_ROUTING1_UART10_ROUTING_SHIFT 8u
#define SCM_FCUART_ROUTING1_UART10_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART10_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART10_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART10_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART9_ROUTING_MASK 0xF0u
#define SCM_FCUART_ROUTING1_UART9_ROUTING_SHIFT 4u
#define SCM_FCUART_ROUTING1_UART9_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART9_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART9_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART9_ROUTING_MASK)
#define SCM_FCUART_ROUTING1_UART8_ROUTING_MASK 0xFu
#define SCM_FCUART_ROUTING1_UART8_ROUTING_SHIFT 0u
#define SCM_FCUART_ROUTING1_UART8_ROUTING_WIDTH 4u
#define SCM_FCUART_ROUTING1_UART8_ROUTING(x) (((uint32_t)(((uint32_t)(x))<<SCM_FCUART_ROUTING1_UART8_ROUTING_SHIFT))&SCM_FCUART_ROUTING1_UART8_ROUTING_MASK)
/* FCUART_ROUTING1 Reg Mask */
#define SCM_FCUART_ROUTING1_MASK       0xFFFFFFFFu

/* ENET_CTRL Bit Fields */
#define SCM_ENET_CTRL_WPB_LOCK_MASK    0x80000000u
#define SCM_ENET_CTRL_WPB_LOCK_SHIFT   31u
#define SCM_ENET_CTRL_WPB_LOCK_WIDTH   1u
#define SCM_ENET_CTRL_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_WPB_LOCK_SHIFT))&SCM_ENET_CTRL_WPB_LOCK_MASK)
#define SCM_ENET_CTRL_WPB_MASK         0x70000000u
#define SCM_ENET_CTRL_WPB_SHIFT        28u
#define SCM_ENET_CTRL_WPB_WIDTH        3u
#define SCM_ENET_CTRL_WPB(x)           (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_WPB_SHIFT))&SCM_ENET_CTRL_WPB_MASK)
#define SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_MASK 0xC000000u
#define SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_SHIFT 26u
#define SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_WIDTH 2u
#define SCM_ENET_CTRL_ENET_RGMII_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_SHIFT))&SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_MASK)
#define SCM_ENET_CTRL_ENET_TXCLK_SEL_MASK 0x3000000u
#define SCM_ENET_CTRL_ENET_TXCLK_SEL_SHIFT 24u
#define SCM_ENET_CTRL_ENET_TXCLK_SEL_WIDTH 2u
#define SCM_ENET_CTRL_ENET_TXCLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_ENET_TXCLK_SEL_SHIFT))&SCM_ENET_CTRL_ENET_TXCLK_SEL_MASK)
#define SCM_ENET_CTRL_ENET_TIMER_OBE_MASK 0xF00000u
#define SCM_ENET_CTRL_ENET_TIMER_OBE_SHIFT 20u
#define SCM_ENET_CTRL_ENET_TIMER_OBE_WIDTH 4u
#define SCM_ENET_CTRL_ENET_TIMER_OBE(x) (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_ENET_TIMER_OBE_SHIFT))&SCM_ENET_CTRL_ENET_TIMER_OBE_MASK)
#define SCM_ENET_CTRL_ENET_CLK_SWRST_MASK 0x10000u
#define SCM_ENET_CTRL_ENET_CLK_SWRST_SHIFT 16u
#define SCM_ENET_CTRL_ENET_CLK_SWRST_WIDTH 1u
#define SCM_ENET_CTRL_ENET_CLK_SWRST(x) (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_ENET_CLK_SWRST_SHIFT))&SCM_ENET_CTRL_ENET_CLK_SWRST_MASK)
#define SCM_ENET_CTRL_MII_TX_CLK_OBE_MASK 0x800u
#define SCM_ENET_CTRL_MII_TX_CLK_OBE_SHIFT 11u
#define SCM_ENET_CTRL_MII_TX_CLK_OBE_WIDTH 1u
#define SCM_ENET_CTRL_MII_TX_CLK_OBE(x) (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_MII_TX_CLK_OBE_SHIFT))&SCM_ENET_CTRL_MII_TX_CLK_OBE_MASK)
#define SCM_ENET_CTRL_PHY_SEL_MASK     0xE0u
#define SCM_ENET_CTRL_PHY_SEL_SHIFT    5u
#define SCM_ENET_CTRL_PHY_SEL_WIDTH    3u
#define SCM_ENET_CTRL_PHY_SEL(x)       (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_PHY_SEL_SHIFT))&SCM_ENET_CTRL_PHY_SEL_MASK)
#define SCM_ENET_CTRL_PTPCLK_SEL_MASK  0xCu
#define SCM_ENET_CTRL_PTPCLK_SEL_SHIFT 2u
#define SCM_ENET_CTRL_PTPCLK_SEL_WIDTH 2u
#define SCM_ENET_CTRL_PTPCLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_PTPCLK_SEL_SHIFT))&SCM_ENET_CTRL_PTPCLK_SEL_MASK)
#define SCM_ENET_CTRL_RMII_5M_MASK     0x2u
#define SCM_ENET_CTRL_RMII_5M_SHIFT    1u
#define SCM_ENET_CTRL_RMII_5M_WIDTH    1u
#define SCM_ENET_CTRL_RMII_5M(x)       (((uint32_t)(((uint32_t)(x))<<SCM_ENET_CTRL_RMII_5M_SHIFT))&SCM_ENET_CTRL_RMII_5M_MASK)
/* ENET_CTRL Reg Mask */
#define SCM_ENET_CTRL_MASK             0xFFF108EEu

/* ADC_ROUTING Bit Fields */
#define SCM_ADC_ROUTING_PTIMER23LOOP_MASK 0x80000000u
#define SCM_ADC_ROUTING_PTIMER23LOOP_SHIFT 31u
#define SCM_ADC_ROUTING_PTIMER23LOOP_WIDTH 1u
#define SCM_ADC_ROUTING_PTIMER23LOOP(x) (((uint32_t)(((uint32_t)(x))<<SCM_ADC_ROUTING_PTIMER23LOOP_SHIFT))&SCM_ADC_ROUTING_PTIMER23LOOP_MASK)
#define SCM_ADC_ROUTING_PTIMER01LOOP_MASK 0x8000u
#define SCM_ADC_ROUTING_PTIMER01LOOP_SHIFT 15u
#define SCM_ADC_ROUTING_PTIMER01LOOP_WIDTH 1u
#define SCM_ADC_ROUTING_PTIMER01LOOP(x) (((uint32_t)(((uint32_t)(x))<<SCM_ADC_ROUTING_PTIMER01LOOP_SHIFT))&SCM_ADC_ROUTING_PTIMER01LOOP_MASK)
/* ADC_ROUTING Reg Mask */
#define SCM_ADC_ROUTING_MASK           0x80008000u

/* FTU_ROUTING Bit Fields */
#define SCM_FTU_ROUTING_FTU3_OUTSEL_MASK 0xFF000000u
#define SCM_FTU_ROUTING_FTU3_OUTSEL_SHIFT 24u
#define SCM_FTU_ROUTING_FTU3_OUTSEL_WIDTH 8u
#define SCM_FTU_ROUTING_FTU3_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_FTU3_OUTSEL_SHIFT))&SCM_FTU_ROUTING_FTU3_OUTSEL_MASK)
#define SCM_FTU_ROUTING_FTU0_OUTSEL_MASK 0xFF0000u
#define SCM_FTU_ROUTING_FTU0_OUTSEL_SHIFT 16u
#define SCM_FTU_ROUTING_FTU0_OUTSEL_WIDTH 8u
#define SCM_FTU_ROUTING_FTU0_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_FTU0_OUTSEL_SHIFT))&SCM_FTU_ROUTING_FTU0_OUTSEL_MASK)
#define SCM_FTU_ROUTING_FTU2_CH1SEL_MASK 0x400u
#define SCM_FTU_ROUTING_FTU2_CH1SEL_SHIFT 10u
#define SCM_FTU_ROUTING_FTU2_CH1SEL_WIDTH 1u
#define SCM_FTU_ROUTING_FTU2_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_FTU2_CH1SEL_SHIFT))&SCM_FTU_ROUTING_FTU2_CH1SEL_MASK)
#define SCM_FTU_ROUTING_FTU2_CH0SEL_MASK 0x300u
#define SCM_FTU_ROUTING_FTU2_CH0SEL_SHIFT 8u
#define SCM_FTU_ROUTING_FTU2_CH0SEL_WIDTH 2u
#define SCM_FTU_ROUTING_FTU2_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_FTU2_CH0SEL_SHIFT))&SCM_FTU_ROUTING_FTU2_CH0SEL_MASK)
#define SCM_FTU_ROUTING_FTU1_CH0SEL_MASK 0x30u
#define SCM_FTU_ROUTING_FTU1_CH0SEL_SHIFT 4u
#define SCM_FTU_ROUTING_FTU1_CH0SEL_WIDTH 2u
#define SCM_FTU_ROUTING_FTU1_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_FTU1_CH0SEL_SHIFT))&SCM_FTU_ROUTING_FTU1_CH0SEL_MASK)
#define SCM_FTU_ROUTING_LOCK_MASK      0x1u
#define SCM_FTU_ROUTING_LOCK_SHIFT     0u
#define SCM_FTU_ROUTING_LOCK_WIDTH     1u
#define SCM_FTU_ROUTING_LOCK(x)        (((uint32_t)(((uint32_t)(x))<<SCM_FTU_ROUTING_LOCK_SHIFT))&SCM_FTU_ROUTING_LOCK_MASK)
/* FTU_ROUTING Reg Mask */
#define SCM_FTU_ROUTING_MASK           0xFFFF0731u

/* FTU_GTBC Bit Fields */
#define SCM_FTU_GTBC_FTU_GTBC_MASK     0x10u
#define SCM_FTU_GTBC_FTU_GTBC_SHIFT    4u
#define SCM_FTU_GTBC_FTU_GTBC_WIDTH    1u
#define SCM_FTU_GTBC_FTU_GTBC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_GTBC_FTU_GTBC_SHIFT))&SCM_FTU_GTBC_FTU_GTBC_MASK)
#define SCM_FTU_GTBC_LOCK_MASK         0x1u
#define SCM_FTU_GTBC_LOCK_SHIFT        0u
#define SCM_FTU_GTBC_LOCK_WIDTH        1u
#define SCM_FTU_GTBC_LOCK(x)           (((uint32_t)(((uint32_t)(x))<<SCM_FTU_GTBC_LOCK_SHIFT))&SCM_FTU_GTBC_LOCK_MASK)
/* FTU_GTBC Reg Mask */
#define SCM_FTU_GTBC_MASK              0x00000011u

/* FTU_SYNC Bit Fields */
#define SCM_FTU_SYNC_FTU11SYNC_MASK    0x400000u
#define SCM_FTU_SYNC_FTU11SYNC_SHIFT   22u
#define SCM_FTU_SYNC_FTU11SYNC_WIDTH   1u
#define SCM_FTU_SYNC_FTU11SYNC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU11SYNC_SHIFT))&SCM_FTU_SYNC_FTU11SYNC_MASK)
#define SCM_FTU_SYNC_FTU10SYNC_MASK    0x100000u
#define SCM_FTU_SYNC_FTU10SYNC_SHIFT   20u
#define SCM_FTU_SYNC_FTU10SYNC_WIDTH   1u
#define SCM_FTU_SYNC_FTU10SYNC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU10SYNC_SHIFT))&SCM_FTU_SYNC_FTU10SYNC_MASK)
#define SCM_FTU_SYNC_FTU9SYNC_MASK     0x40000u
#define SCM_FTU_SYNC_FTU9SYNC_SHIFT    18u
#define SCM_FTU_SYNC_FTU9SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU9SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU9SYNC_SHIFT))&SCM_FTU_SYNC_FTU9SYNC_MASK)
#define SCM_FTU_SYNC_FTU8SYNC_MASK     0x10000u
#define SCM_FTU_SYNC_FTU8SYNC_SHIFT    16u
#define SCM_FTU_SYNC_FTU8SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU8SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU8SYNC_SHIFT))&SCM_FTU_SYNC_FTU8SYNC_MASK)
#define SCM_FTU_SYNC_FTU7SYNC_MASK     0x4000u
#define SCM_FTU_SYNC_FTU7SYNC_SHIFT    14u
#define SCM_FTU_SYNC_FTU7SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU7SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU7SYNC_SHIFT))&SCM_FTU_SYNC_FTU7SYNC_MASK)
#define SCM_FTU_SYNC_FTU6SYNC_MASK     0x1000u
#define SCM_FTU_SYNC_FTU6SYNC_SHIFT    12u
#define SCM_FTU_SYNC_FTU6SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU6SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU6SYNC_SHIFT))&SCM_FTU_SYNC_FTU6SYNC_MASK)
#define SCM_FTU_SYNC_FTU5SYNC_MASK     0x400u
#define SCM_FTU_SYNC_FTU5SYNC_SHIFT    10u
#define SCM_FTU_SYNC_FTU5SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU5SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU5SYNC_SHIFT))&SCM_FTU_SYNC_FTU5SYNC_MASK)
#define SCM_FTU_SYNC_FTU4SYNC_MASK     0x100u
#define SCM_FTU_SYNC_FTU4SYNC_SHIFT    8u
#define SCM_FTU_SYNC_FTU4SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU4SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU4SYNC_SHIFT))&SCM_FTU_SYNC_FTU4SYNC_MASK)
#define SCM_FTU_SYNC_FTU3SYNC_MASK     0x40u
#define SCM_FTU_SYNC_FTU3SYNC_SHIFT    6u
#define SCM_FTU_SYNC_FTU3SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU3SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU3SYNC_SHIFT))&SCM_FTU_SYNC_FTU3SYNC_MASK)
#define SCM_FTU_SYNC_FTU2SYNC_MASK     0x10u
#define SCM_FTU_SYNC_FTU2SYNC_SHIFT    4u
#define SCM_FTU_SYNC_FTU2SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU2SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU2SYNC_SHIFT))&SCM_FTU_SYNC_FTU2SYNC_MASK)
#define SCM_FTU_SYNC_FTU1SYNC_MASK     0x4u
#define SCM_FTU_SYNC_FTU1SYNC_SHIFT    2u
#define SCM_FTU_SYNC_FTU1SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU1SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU1SYNC_SHIFT))&SCM_FTU_SYNC_FTU1SYNC_MASK)
#define SCM_FTU_SYNC_FTU0SYNC_MASK     0x1u
#define SCM_FTU_SYNC_FTU0SYNC_SHIFT    0u
#define SCM_FTU_SYNC_FTU0SYNC_WIDTH    1u
#define SCM_FTU_SYNC_FTU0SYNC(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FTU_SYNC_FTU0SYNC_SHIFT))&SCM_FTU_SYNC_FTU0SYNC_MASK)
/* FTU_SYNC Reg Mask */
#define SCM_FTU_SYNC_MASK              0x00555555u

/* DEBUG_TRACE Bit Fields */
#define SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_MASK 0x80000000u
#define SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_SHIFT 31u
#define SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_WIDTH 1u
#define SCM_DEBUG_TRACE_DEBUG_ATCLK_EN(x) (((uint32_t)(((uint32_t)(x))<<SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_SHIFT))&SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_MASK)
#define SCM_DEBUG_TRACE_TRACECLK_DIV_MASK 0xF0u
#define SCM_DEBUG_TRACE_TRACECLK_DIV_SHIFT 4u
#define SCM_DEBUG_TRACE_TRACECLK_DIV_WIDTH 4u
#define SCM_DEBUG_TRACE_TRACECLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<SCM_DEBUG_TRACE_TRACECLK_DIV_SHIFT))&SCM_DEBUG_TRACE_TRACECLK_DIV_MASK)
#define SCM_DEBUG_TRACE_TRACECLK_SEL_MASK 0x8u
#define SCM_DEBUG_TRACE_TRACECLK_SEL_SHIFT 3u
#define SCM_DEBUG_TRACE_TRACECLK_SEL_WIDTH 1u
#define SCM_DEBUG_TRACE_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_DEBUG_TRACE_TRACECLK_SEL_SHIFT))&SCM_DEBUG_TRACE_TRACECLK_SEL_MASK)
#define SCM_DEBUG_TRACE_TRACECLK_EN_MASK 0x4u
#define SCM_DEBUG_TRACE_TRACECLK_EN_SHIFT 2u
#define SCM_DEBUG_TRACE_TRACECLK_EN_WIDTH 1u
#define SCM_DEBUG_TRACE_TRACECLK_EN(x) (((uint32_t)(((uint32_t)(x))<<SCM_DEBUG_TRACE_TRACECLK_EN_SHIFT))&SCM_DEBUG_TRACE_TRACECLK_EN_MASK)
#define SCM_DEBUG_TRACE_LOCK_MASK      0x1u
#define SCM_DEBUG_TRACE_LOCK_SHIFT     0u
#define SCM_DEBUG_TRACE_LOCK_WIDTH     1u
#define SCM_DEBUG_TRACE_LOCK(x)        (((uint32_t)(((uint32_t)(x))<<SCM_DEBUG_TRACE_LOCK_SHIFT))&SCM_DEBUG_TRACE_LOCK_MASK)
/* DEBUG_TRACE Reg Mask */
#define SCM_DEBUG_TRACE_MASK           0x800000FDu

/* SOCMISC Bit Fields */
#define SCM_SOCMISC_WPB_LOCK_MASK      0x80000000u
#define SCM_SOCMISC_WPB_LOCK_SHIFT     31u
#define SCM_SOCMISC_WPB_LOCK_WIDTH     1u
#define SCM_SOCMISC_WPB_LOCK(x)        (((uint32_t)(((uint32_t)(x))<<SCM_SOCMISC_WPB_LOCK_SHIFT))&SCM_SOCMISC_WPB_LOCK_MASK)
#define SCM_SOCMISC_WPB_MASK           0x70000000u
#define SCM_SOCMISC_WPB_SHIFT          28u
#define SCM_SOCMISC_WPB_WIDTH          3u
#define SCM_SOCMISC_WPB(x)             (((uint32_t)(((uint32_t)(x))<<SCM_SOCMISC_WPB_SHIFT))&SCM_SOCMISC_WPB_MASK)
#define SCM_SOCMISC_GPR_SW_TRIG_7_4_MASK 0xF0u
#define SCM_SOCMISC_GPR_SW_TRIG_7_4_SHIFT 4u
#define SCM_SOCMISC_GPR_SW_TRIG_7_4_WIDTH 4u
#define SCM_SOCMISC_GPR_SW_TRIG_7_4(x) (((uint32_t)(((uint32_t)(x))<<SCM_SOCMISC_GPR_SW_TRIG_7_4_SHIFT))&SCM_SOCMISC_GPR_SW_TRIG_7_4_MASK)
#define SCM_SOCMISC_GPR_SW_TRIG_3_0_MASK 0xFu
#define SCM_SOCMISC_GPR_SW_TRIG_3_0_SHIFT 0u
#define SCM_SOCMISC_GPR_SW_TRIG_3_0_WIDTH 4u
#define SCM_SOCMISC_GPR_SW_TRIG_3_0(x) (((uint32_t)(((uint32_t)(x))<<SCM_SOCMISC_GPR_SW_TRIG_3_0_SHIFT))&SCM_SOCMISC_GPR_SW_TRIG_3_0_MASK)
/* SOCMISC Reg Mask */
#define SCM_SOCMISC_MASK               0xF00000FFu

/* CCM0_STATUS Bit Fields */
#define SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK 0x80u
#define SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_SHIFT 7u
#define SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_SHIFT))&SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK)
#define SCM_CCM0_STATUS_CPU0_STOP_MASTER_MASK 0x40u
#define SCM_CCM0_STATUS_CPU0_STOP_MASTER_SHIFT 6u
#define SCM_CCM0_STATUS_CPU0_STOP_MASTER_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_STOP_MASTER(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_STOP_MASTER_SHIFT))&SCM_CCM0_STATUS_CPU0_STOP_MASTER_MASK)
#define SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK 0x20u
#define SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_SHIFT 5u
#define SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_SHIFT))&SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK)
#define SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK 0x10u
#define SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_SHIFT 4u
#define SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_SHIFT))&SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK)
#define SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_MASK 0x2u
#define SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_SHIFT 1u
#define SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_DEEPSLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_SHIFT))&SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_MASK)
#define SCM_CCM0_STATUS_CPU0_SLEEPING_MASK 0x1u
#define SCM_CCM0_STATUS_CPU0_SLEEPING_SHIFT 0u
#define SCM_CCM0_STATUS_CPU0_SLEEPING_WIDTH 1u
#define SCM_CCM0_STATUS_CPU0_SLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM0_STATUS_CPU0_SLEEPING_SHIFT))&SCM_CCM0_STATUS_CPU0_SLEEPING_MASK)
/* CCM0_STATUS Reg Mask */
#define SCM_CCM0_STATUS_MASK           0x000000F3u

/* CCM1_STATUS Bit Fields */
#define SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE_MASK 0x80u
#define SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE_SHIFT 7u
#define SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE_SHIFT))&SCM_CCM1_STATUS_CPU1_STOP_SYS_SLAVE_MASK)
#define SCM_CCM1_STATUS_CPU1_STOP_MASTER_MASK 0x40u
#define SCM_CCM1_STATUS_CPU1_STOP_MASTER_SHIFT 6u
#define SCM_CCM1_STATUS_CPU1_STOP_MASTER_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_STOP_MASTER(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_STOP_MASTER_SHIFT))&SCM_CCM1_STATUS_CPU1_STOP_MASTER_MASK)
#define SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE_MASK 0x20u
#define SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE_SHIFT 5u
#define SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE_SHIFT))&SCM_CCM1_STATUS_CPU1_STOP_SLOW_SLAVE_MASK)
#define SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE_MASK 0x10u
#define SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE_SHIFT 4u
#define SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE_SHIFT))&SCM_CCM1_STATUS_CPU1_STOP_BUS_SLAVE_MASK)
#define SCM_CCM1_STATUS_CPU1_DEEPSLEEPING_MASK 0x2u
#define SCM_CCM1_STATUS_CPU1_DEEPSLEEPING_SHIFT 1u
#define SCM_CCM1_STATUS_CPU1_DEEPSLEEPING_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_DEEPSLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_DEEPSLEEPING_SHIFT))&SCM_CCM1_STATUS_CPU1_DEEPSLEEPING_MASK)
#define SCM_CCM1_STATUS_CPU1_SLEEPING_MASK 0x1u
#define SCM_CCM1_STATUS_CPU1_SLEEPING_SHIFT 0u
#define SCM_CCM1_STATUS_CPU1_SLEEPING_WIDTH 1u
#define SCM_CCM1_STATUS_CPU1_SLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM1_STATUS_CPU1_SLEEPING_SHIFT))&SCM_CCM1_STATUS_CPU1_SLEEPING_MASK)
/* CCM1_STATUS Reg Mask */
#define SCM_CCM1_STATUS_MASK           0x000000F3u

/* CCM2_STATUS Bit Fields */
#define SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE_MASK 0x80u
#define SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE_SHIFT 7u
#define SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE_SHIFT))&SCM_CCM2_STATUS_CPU2_STOP_SYS_SLAVE_MASK)
#define SCM_CCM2_STATUS_CPU2_STOP_MASTER_MASK 0x40u
#define SCM_CCM2_STATUS_CPU2_STOP_MASTER_SHIFT 6u
#define SCM_CCM2_STATUS_CPU2_STOP_MASTER_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_STOP_MASTER(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_STOP_MASTER_SHIFT))&SCM_CCM2_STATUS_CPU2_STOP_MASTER_MASK)
#define SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE_MASK 0x20u
#define SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE_SHIFT 5u
#define SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE_SHIFT))&SCM_CCM2_STATUS_CPU2_STOP_SLOW_SLAVE_MASK)
#define SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE_MASK 0x10u
#define SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE_SHIFT 4u
#define SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE_SHIFT))&SCM_CCM2_STATUS_CPU2_STOP_BUS_SLAVE_MASK)
#define SCM_CCM2_STATUS_CPU2_DEEPSLEEPING_MASK 0x2u
#define SCM_CCM2_STATUS_CPU2_DEEPSLEEPING_SHIFT 1u
#define SCM_CCM2_STATUS_CPU2_DEEPSLEEPING_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_DEEPSLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_DEEPSLEEPING_SHIFT))&SCM_CCM2_STATUS_CPU2_DEEPSLEEPING_MASK)
#define SCM_CCM2_STATUS_CPU2_SLEEPING_MASK 0x1u
#define SCM_CCM2_STATUS_CPU2_SLEEPING_SHIFT 0u
#define SCM_CCM2_STATUS_CPU2_SLEEPING_WIDTH 1u
#define SCM_CCM2_STATUS_CPU2_SLEEPING(x) (((uint32_t)(((uint32_t)(x))<<SCM_CCM2_STATUS_CPU2_SLEEPING_SHIFT))&SCM_CCM2_STATUS_CPU2_SLEEPING_MASK)
/* CCM2_STATUS Reg Mask */
#define SCM_CCM2_STATUS_MASK           0x000000F3u

/* ENET_STATUS Bit Fields */
#define SCM_ENET_STATUS_ENET_CHID_MASK 0x3u
#define SCM_ENET_STATUS_ENET_CHID_SHIFT 0u
#define SCM_ENET_STATUS_ENET_CHID_WIDTH 2u
#define SCM_ENET_STATUS_ENET_CHID(x)   (((uint32_t)(((uint32_t)(x))<<SCM_ENET_STATUS_ENET_CHID_SHIFT))&SCM_ENET_STATUS_ENET_CHID_MASK)
/* ENET_STATUS Reg Mask */
#define SCM_ENET_STATUS_MASK           0x00000003u

/* SDDF_ROUTING Bit Fields */
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL_MASK 0xC0000000u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL_SHIFT 30u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH3_CLKOUTSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL_MASK 0x30000000u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL_SHIFT 28u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH2_CLKOUTSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL_MASK 0xC000000u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL_SHIFT 26u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH1_CLKOUTSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL_MASK 0x3000000u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL_SHIFT 24u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH0_CLKOUTSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL_MASK 0xC000u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL_SHIFT 14u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH3_CLKINSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL_MASK 0x3000u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL_SHIFT 12u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH2_CLKINSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL_MASK 0xC00u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL_SHIFT 10u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH1_CLKINSEL_MASK)
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL_MASK 0x300u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL_SHIFT 8u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL_WIDTH 2u
#define SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL_SHIFT))&SCM_SDDF_ROUTING_SDDF_CH0_CLKINSEL_MASK)
#define SCM_SDDF_ROUTING_LOCK_MASK     0x1u
#define SCM_SDDF_ROUTING_LOCK_SHIFT    0u
#define SCM_SDDF_ROUTING_LOCK_WIDTH    1u
#define SCM_SDDF_ROUTING_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<SCM_SDDF_ROUTING_LOCK_SHIFT))&SCM_SDDF_ROUTING_LOCK_MASK)
/* SDDF_ROUTING Reg Mask */
#define SCM_SDDF_ROUTING_MASK          0xFF00FF01u

/* FLEXCAN_ROUTING Bit Fields */
#define SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER_MASK 0xC00u
#define SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER_SHIFT 10u
#define SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER_WIDTH 2u
#define SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER(x) (((uint32_t)(((uint32_t)(x))<<SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER_SHIFT))&SCM_FLEXCAN_ROUTING_FLEXCAN9_ROUTER_MASK)
#define SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER_MASK 0x300u
#define SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER_SHIFT 8u
#define SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER_WIDTH 2u
#define SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER(x) (((uint32_t)(((uint32_t)(x))<<SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER_SHIFT))&SCM_FLEXCAN_ROUTING_FLEXCAN8_ROUTER_MASK)
#define SCM_FLEXCAN_ROUTING_LOCK_MASK  0x1u
#define SCM_FLEXCAN_ROUTING_LOCK_SHIFT 0u
#define SCM_FLEXCAN_ROUTING_LOCK_WIDTH 1u
#define SCM_FLEXCAN_ROUTING_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<SCM_FLEXCAN_ROUTING_LOCK_SHIFT))&SCM_FLEXCAN_ROUTING_LOCK_MASK)
/* FLEXCAN_ROUTING Reg Mask */
#define SCM_FLEXCAN_ROUTING_MASK       0x00000F01u

/* MSC0_ROUTING Bit Fields */
#define SCM_MSC0_ROUTING_MSC0_31_24_SEL_MASK 0xF0000000u
#define SCM_MSC0_ROUTING_MSC0_31_24_SEL_SHIFT 28u
#define SCM_MSC0_ROUTING_MSC0_31_24_SEL_WIDTH 4u
#define SCM_MSC0_ROUTING_MSC0_31_24_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC0_ROUTING_MSC0_31_24_SEL_SHIFT))&SCM_MSC0_ROUTING_MSC0_31_24_SEL_MASK)
#define SCM_MSC0_ROUTING_MSC0_23_16_SEL_MASK 0xF000000u
#define SCM_MSC0_ROUTING_MSC0_23_16_SEL_SHIFT 24u
#define SCM_MSC0_ROUTING_MSC0_23_16_SEL_WIDTH 4u
#define SCM_MSC0_ROUTING_MSC0_23_16_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC0_ROUTING_MSC0_23_16_SEL_SHIFT))&SCM_MSC0_ROUTING_MSC0_23_16_SEL_MASK)
#define SCM_MSC0_ROUTING_MSC0_15_8_SEL_MASK 0xF00000u
#define SCM_MSC0_ROUTING_MSC0_15_8_SEL_SHIFT 20u
#define SCM_MSC0_ROUTING_MSC0_15_8_SEL_WIDTH 4u
#define SCM_MSC0_ROUTING_MSC0_15_8_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC0_ROUTING_MSC0_15_8_SEL_SHIFT))&SCM_MSC0_ROUTING_MSC0_15_8_SEL_MASK)
#define SCM_MSC0_ROUTING_MSC0_7_0_SEL_MASK 0xF0000u
#define SCM_MSC0_ROUTING_MSC0_7_0_SEL_SHIFT 16u
#define SCM_MSC0_ROUTING_MSC0_7_0_SEL_WIDTH 4u
#define SCM_MSC0_ROUTING_MSC0_7_0_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC0_ROUTING_MSC0_7_0_SEL_SHIFT))&SCM_MSC0_ROUTING_MSC0_7_0_SEL_MASK)
#define SCM_MSC0_ROUTING_LOCK_MASK     0x1u
#define SCM_MSC0_ROUTING_LOCK_SHIFT    0u
#define SCM_MSC0_ROUTING_LOCK_WIDTH    1u
#define SCM_MSC0_ROUTING_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<SCM_MSC0_ROUTING_LOCK_SHIFT))&SCM_MSC0_ROUTING_LOCK_MASK)
/* MSC0_ROUTING Reg Mask */
#define SCM_MSC0_ROUTING_MASK          0xFFFF0001u

/* MSC1_ROUTING Bit Fields */
#define SCM_MSC1_ROUTING_MSC1_31_24_SEL_MASK 0xF0000000u
#define SCM_MSC1_ROUTING_MSC1_31_24_SEL_SHIFT 28u
#define SCM_MSC1_ROUTING_MSC1_31_24_SEL_WIDTH 4u
#define SCM_MSC1_ROUTING_MSC1_31_24_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC1_ROUTING_MSC1_31_24_SEL_SHIFT))&SCM_MSC1_ROUTING_MSC1_31_24_SEL_MASK)
#define SCM_MSC1_ROUTING_MSC1_23_16_SEL_MASK 0xF000000u
#define SCM_MSC1_ROUTING_MSC1_23_16_SEL_SHIFT 24u
#define SCM_MSC1_ROUTING_MSC1_23_16_SEL_WIDTH 4u
#define SCM_MSC1_ROUTING_MSC1_23_16_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC1_ROUTING_MSC1_23_16_SEL_SHIFT))&SCM_MSC1_ROUTING_MSC1_23_16_SEL_MASK)
#define SCM_MSC1_ROUTING_MSC1_15_8_SEL_MASK 0xF00000u
#define SCM_MSC1_ROUTING_MSC1_15_8_SEL_SHIFT 20u
#define SCM_MSC1_ROUTING_MSC1_15_8_SEL_WIDTH 4u
#define SCM_MSC1_ROUTING_MSC1_15_8_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC1_ROUTING_MSC1_15_8_SEL_SHIFT))&SCM_MSC1_ROUTING_MSC1_15_8_SEL_MASK)
#define SCM_MSC1_ROUTING_MSC1_7_0_SEL_MASK 0xF0000u
#define SCM_MSC1_ROUTING_MSC1_7_0_SEL_SHIFT 16u
#define SCM_MSC1_ROUTING_MSC1_7_0_SEL_WIDTH 4u
#define SCM_MSC1_ROUTING_MSC1_7_0_SEL(x) (((uint32_t)(((uint32_t)(x))<<SCM_MSC1_ROUTING_MSC1_7_0_SEL_SHIFT))&SCM_MSC1_ROUTING_MSC1_7_0_SEL_MASK)
#define SCM_MSC1_ROUTING_LOCK_MASK     0x1u
#define SCM_MSC1_ROUTING_LOCK_SHIFT    0u
#define SCM_MSC1_ROUTING_LOCK_WIDTH    1u
#define SCM_MSC1_ROUTING_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<SCM_MSC1_ROUTING_LOCK_SHIFT))&SCM_MSC1_ROUTING_LOCK_MASK)
/* MSC1_ROUTING Reg Mask */
#define SCM_MSC1_ROUTING_MASK          0xFFFF0001u

/* PERI_CLKDIV Bit Fields */
#define SCM_PERI_CLKDIV_ENET_PLL0_DIV_MASK 0xF0u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIV_SHIFT 4u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIV_WIDTH 4u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIV(x) (((uint32_t)(((uint32_t)(x))<<SCM_PERI_CLKDIV_ENET_PLL0_DIV_SHIFT))&SCM_PERI_CLKDIV_ENET_PLL0_DIV_MASK)
#define SCM_PERI_CLKDIV_ENET_PLL0_DIVEN_MASK 0x8u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIVEN_SHIFT 3u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIVEN_WIDTH 1u
#define SCM_PERI_CLKDIV_ENET_PLL0_DIVEN(x) (((uint32_t)(((uint32_t)(x))<<SCM_PERI_CLKDIV_ENET_PLL0_DIVEN_SHIFT))&SCM_PERI_CLKDIV_ENET_PLL0_DIVEN_MASK)
#define SCM_PERI_CLKDIV_LOCK_MASK      0x1u
#define SCM_PERI_CLKDIV_LOCK_SHIFT     0u
#define SCM_PERI_CLKDIV_LOCK_WIDTH     1u
#define SCM_PERI_CLKDIV_LOCK(x)        (((uint32_t)(((uint32_t)(x))<<SCM_PERI_CLKDIV_LOCK_SHIFT))&SCM_PERI_CLKDIV_LOCK_MASK)
/* PERI_CLKDIV Reg Mask */
#define SCM_PERI_CLKDIV_MASK           0x000000F9u

/* FCSMU_SW Bit Fields */
#define SCM_FCSMU_SW_FCSMU_SW_MASK     0x1u
#define SCM_FCSMU_SW_FCSMU_SW_SHIFT    0u
#define SCM_FCSMU_SW_FCSMU_SW_WIDTH    1u
#define SCM_FCSMU_SW_FCSMU_SW(x)       (((uint32_t)(((uint32_t)(x))<<SCM_FCSMU_SW_FCSMU_SW_SHIFT))&SCM_FCSMU_SW_FCSMU_SW_MASK)
/* FCSMU_SW Reg Mask */
#define SCM_FCSMU_SW_MASK              0x00000001u

/* ISM_ROUTING Bit Fields */
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_B_MASK 0xF0u
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_B_SHIFT 4u
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_B_WIDTH 4u
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_B(x) (((uint32_t)(((uint32_t)(x))<<SCM_ISM_ROUTING_ISM_ROUT_FTU_B_SHIFT))&SCM_ISM_ROUTING_ISM_ROUT_FTU_B_MASK)
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_A_MASK 0xFu
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_A_SHIFT 0u
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_A_WIDTH 4u
#define SCM_ISM_ROUTING_ISM_ROUT_FTU_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_ISM_ROUTING_ISM_ROUT_FTU_A_SHIFT))&SCM_ISM_ROUTING_ISM_ROUT_FTU_A_MASK)
/* ISM_ROUTING Reg Mask */
#define SCM_ISM_ROUTING_MASK           0x000000FFu

/* MATRIX_STATUS0 Bit Fields */
#define SCM_MATRIX_STATUS0_MAM1_S3_M_MASK 0x80000000u
#define SCM_MATRIX_STATUS0_MAM1_S3_M_SHIFT 31u
#define SCM_MATRIX_STATUS0_MAM1_S3_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S3_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S3_M_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S3_M_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S3_AT_MASK 0x40000000u
#define SCM_MATRIX_STATUS0_MAM1_S3_AT_SHIFT 30u
#define SCM_MATRIX_STATUS0_MAM1_S3_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S3_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S3_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S3_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S3_D_MASK 0x20000000u
#define SCM_MATRIX_STATUS0_MAM1_S3_D_SHIFT 29u
#define SCM_MATRIX_STATUS0_MAM1_S3_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S3_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S3_D_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S3_D_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S3_A_MASK 0x10000000u
#define SCM_MATRIX_STATUS0_MAM1_S3_A_SHIFT 28u
#define SCM_MATRIX_STATUS0_MAM1_S3_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S3_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S3_A_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S3_A_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S2_M_MASK 0x8000000u
#define SCM_MATRIX_STATUS0_MAM1_S2_M_SHIFT 27u
#define SCM_MATRIX_STATUS0_MAM1_S2_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S2_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S2_M_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S2_M_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S2_AT_MASK 0x4000000u
#define SCM_MATRIX_STATUS0_MAM1_S2_AT_SHIFT 26u
#define SCM_MATRIX_STATUS0_MAM1_S2_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S2_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S2_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S2_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S2_D_MASK 0x2000000u
#define SCM_MATRIX_STATUS0_MAM1_S2_D_SHIFT 25u
#define SCM_MATRIX_STATUS0_MAM1_S2_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S2_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S2_D_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S2_D_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S2_A_MASK 0x1000000u
#define SCM_MATRIX_STATUS0_MAM1_S2_A_SHIFT 24u
#define SCM_MATRIX_STATUS0_MAM1_S2_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S2_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S2_A_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S2_A_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S1_M_MASK 0x800000u
#define SCM_MATRIX_STATUS0_MAM1_S1_M_SHIFT 23u
#define SCM_MATRIX_STATUS0_MAM1_S1_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S1_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S1_M_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S1_M_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S1_AT_MASK 0x400000u
#define SCM_MATRIX_STATUS0_MAM1_S1_AT_SHIFT 22u
#define SCM_MATRIX_STATUS0_MAM1_S1_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S1_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S1_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S1_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S1_D_MASK 0x200000u
#define SCM_MATRIX_STATUS0_MAM1_S1_D_SHIFT 21u
#define SCM_MATRIX_STATUS0_MAM1_S1_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S1_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S1_D_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S1_D_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S1_A_MASK 0x100000u
#define SCM_MATRIX_STATUS0_MAM1_S1_A_SHIFT 20u
#define SCM_MATRIX_STATUS0_MAM1_S1_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S1_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S1_A_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S1_A_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S0_M_MASK 0x80000u
#define SCM_MATRIX_STATUS0_MAM1_S0_M_SHIFT 19u
#define SCM_MATRIX_STATUS0_MAM1_S0_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S0_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S0_M_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S0_M_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S0_AT_MASK 0x40000u
#define SCM_MATRIX_STATUS0_MAM1_S0_AT_SHIFT 18u
#define SCM_MATRIX_STATUS0_MAM1_S0_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S0_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S0_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S0_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S0_D_MASK 0x20000u
#define SCM_MATRIX_STATUS0_MAM1_S0_D_SHIFT 17u
#define SCM_MATRIX_STATUS0_MAM1_S0_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S0_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S0_D_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S0_D_MASK)
#define SCM_MATRIX_STATUS0_MAM1_S0_A_MASK 0x10000u
#define SCM_MATRIX_STATUS0_MAM1_S0_A_SHIFT 16u
#define SCM_MATRIX_STATUS0_MAM1_S0_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM1_S0_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM1_S0_A_SHIFT))&SCM_MATRIX_STATUS0_MAM1_S0_A_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S3_M_MASK 0x8000u
#define SCM_MATRIX_STATUS0_MAM0_S3_M_SHIFT 15u
#define SCM_MATRIX_STATUS0_MAM0_S3_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S3_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S3_M_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S3_M_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S3_AT_MASK 0x4000u
#define SCM_MATRIX_STATUS0_MAM0_S3_AT_SHIFT 14u
#define SCM_MATRIX_STATUS0_MAM0_S3_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S3_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S3_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S3_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S3_D_MASK 0x2000u
#define SCM_MATRIX_STATUS0_MAM0_S3_D_SHIFT 13u
#define SCM_MATRIX_STATUS0_MAM0_S3_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S3_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S3_D_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S3_D_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S3_A_MASK 0x1000u
#define SCM_MATRIX_STATUS0_MAM0_S3_A_SHIFT 12u
#define SCM_MATRIX_STATUS0_MAM0_S3_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S3_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S3_A_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S3_A_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S2_M_MASK 0x800u
#define SCM_MATRIX_STATUS0_MAM0_S2_M_SHIFT 11u
#define SCM_MATRIX_STATUS0_MAM0_S2_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S2_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S2_M_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S2_M_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S2_AT_MASK 0x400u
#define SCM_MATRIX_STATUS0_MAM0_S2_AT_SHIFT 10u
#define SCM_MATRIX_STATUS0_MAM0_S2_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S2_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S2_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S2_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S2_D_MASK 0x200u
#define SCM_MATRIX_STATUS0_MAM0_S2_D_SHIFT 9u
#define SCM_MATRIX_STATUS0_MAM0_S2_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S2_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S2_D_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S2_D_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S2_A_MASK 0x100u
#define SCM_MATRIX_STATUS0_MAM0_S2_A_SHIFT 8u
#define SCM_MATRIX_STATUS0_MAM0_S2_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S2_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S2_A_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S2_A_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S1_M_MASK 0x80u
#define SCM_MATRIX_STATUS0_MAM0_S1_M_SHIFT 7u
#define SCM_MATRIX_STATUS0_MAM0_S1_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S1_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S1_M_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S1_M_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S1_AT_MASK 0x40u
#define SCM_MATRIX_STATUS0_MAM0_S1_AT_SHIFT 6u
#define SCM_MATRIX_STATUS0_MAM0_S1_AT_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S1_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S1_AT_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S1_AT_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S1_D_MASK 0x20u
#define SCM_MATRIX_STATUS0_MAM0_S1_D_SHIFT 5u
#define SCM_MATRIX_STATUS0_MAM0_S1_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S1_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S1_D_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S1_D_MASK)
#define SCM_MATRIX_STATUS0_MAM0_S1_A_MASK 0x10u
#define SCM_MATRIX_STATUS0_MAM0_S1_A_SHIFT 4u
#define SCM_MATRIX_STATUS0_MAM0_S1_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_MAM0_S1_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_MAM0_S1_A_SHIFT))&SCM_MATRIX_STATUS0_MAM0_S1_A_MASK)
#define SCM_MATRIX_STATUS0_ROM_M_MASK  0x8u
#define SCM_MATRIX_STATUS0_ROM_M_SHIFT 3u
#define SCM_MATRIX_STATUS0_ROM_M_WIDTH 1u
#define SCM_MATRIX_STATUS0_ROM_M(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_ROM_M_SHIFT))&SCM_MATRIX_STATUS0_ROM_M_MASK)
#define SCM_MATRIX_STATUS0_ROM_D_MASK  0x2u
#define SCM_MATRIX_STATUS0_ROM_D_SHIFT 1u
#define SCM_MATRIX_STATUS0_ROM_D_WIDTH 1u
#define SCM_MATRIX_STATUS0_ROM_D(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_ROM_D_SHIFT))&SCM_MATRIX_STATUS0_ROM_D_MASK)
#define SCM_MATRIX_STATUS0_ROM_A_MASK  0x1u
#define SCM_MATRIX_STATUS0_ROM_A_SHIFT 0u
#define SCM_MATRIX_STATUS0_ROM_A_WIDTH 1u
#define SCM_MATRIX_STATUS0_ROM_A(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS0_ROM_A_SHIFT))&SCM_MATRIX_STATUS0_ROM_A_MASK)
/* MATRIX_STATUS0 Reg Mask */
#define SCM_MATRIX_STATUS0_MASK        0xFFFFFFFBu

/* MATRIX_STATUS1 Bit Fields */
#define SCM_MATRIX_STATUS1_DMA1_M_MASK 0x80000000u
#define SCM_MATRIX_STATUS1_DMA1_M_SHIFT 31u
#define SCM_MATRIX_STATUS1_DMA1_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA1_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA1_M_SHIFT))&SCM_MATRIX_STATUS1_DMA1_M_MASK)
#define SCM_MATRIX_STATUS1_DMA1_D_MASK 0x20000000u
#define SCM_MATRIX_STATUS1_DMA1_D_SHIFT 29u
#define SCM_MATRIX_STATUS1_DMA1_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA1_D(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA1_D_SHIFT))&SCM_MATRIX_STATUS1_DMA1_D_MASK)
#define SCM_MATRIX_STATUS1_DMA1_A_MASK 0x10000000u
#define SCM_MATRIX_STATUS1_DMA1_A_SHIFT 28u
#define SCM_MATRIX_STATUS1_DMA1_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA1_A(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA1_A_SHIFT))&SCM_MATRIX_STATUS1_DMA1_A_MASK)
#define SCM_MATRIX_STATUS1_DMA0_M_MASK 0x8000000u
#define SCM_MATRIX_STATUS1_DMA0_M_SHIFT 27u
#define SCM_MATRIX_STATUS1_DMA0_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA0_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA0_M_SHIFT))&SCM_MATRIX_STATUS1_DMA0_M_MASK)
#define SCM_MATRIX_STATUS1_DMA0_D_MASK 0x2000000u
#define SCM_MATRIX_STATUS1_DMA0_D_SHIFT 25u
#define SCM_MATRIX_STATUS1_DMA0_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA0_D(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA0_D_SHIFT))&SCM_MATRIX_STATUS1_DMA0_D_MASK)
#define SCM_MATRIX_STATUS1_DMA0_A_MASK 0x1000000u
#define SCM_MATRIX_STATUS1_DMA0_A_SHIFT 24u
#define SCM_MATRIX_STATUS1_DMA0_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_DMA0_A(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_DMA0_A_SHIFT))&SCM_MATRIX_STATUS1_DMA0_A_MASK)
#define SCM_MATRIX_STATUS1_HSM_M_MASK  0x800000u
#define SCM_MATRIX_STATUS1_HSM_M_SHIFT 23u
#define SCM_MATRIX_STATUS1_HSM_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_HSM_M(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_HSM_M_SHIFT))&SCM_MATRIX_STATUS1_HSM_M_MASK)
#define SCM_MATRIX_STATUS1_HSM_D_MASK  0x200000u
#define SCM_MATRIX_STATUS1_HSM_D_SHIFT 21u
#define SCM_MATRIX_STATUS1_HSM_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_HSM_D(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_HSM_D_SHIFT))&SCM_MATRIX_STATUS1_HSM_D_MASK)
#define SCM_MATRIX_STATUS1_HSM_A_MASK  0x100000u
#define SCM_MATRIX_STATUS1_HSM_A_SHIFT 20u
#define SCM_MATRIX_STATUS1_HSM_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_HSM_A(x)    (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_HSM_A_SHIFT))&SCM_MATRIX_STATUS1_HSM_A_MASK)
#define SCM_MATRIX_STATUS1_ENET_M_MASK 0x80000u
#define SCM_MATRIX_STATUS1_ENET_M_SHIFT 19u
#define SCM_MATRIX_STATUS1_ENET_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_ENET_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_ENET_M_SHIFT))&SCM_MATRIX_STATUS1_ENET_M_MASK)
#define SCM_MATRIX_STATUS1_ENET_D_MASK 0x20000u
#define SCM_MATRIX_STATUS1_ENET_D_SHIFT 17u
#define SCM_MATRIX_STATUS1_ENET_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_ENET_D(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_ENET_D_SHIFT))&SCM_MATRIX_STATUS1_ENET_D_MASK)
#define SCM_MATRIX_STATUS1_ENET_A_MASK 0x10000u
#define SCM_MATRIX_STATUS1_ENET_A_SHIFT 16u
#define SCM_MATRIX_STATUS1_ENET_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_ENET_A(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_ENET_A_SHIFT))&SCM_MATRIX_STATUS1_ENET_A_MASK)
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_M_MASK 0x8000u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_M_SHIFT 15u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM1_S3_DS_M_SHIFT))&SCM_MATRIX_STATUS1_MAM1_S3_DS_M_MASK)
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_D_MASK 0x2000u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_D_SHIFT 13u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM1_S3_DS_D_SHIFT))&SCM_MATRIX_STATUS1_MAM1_S3_DS_D_MASK)
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_A_MASK 0x1000u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_A_SHIFT 12u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM1_S3_DS_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM1_S3_DS_A_SHIFT))&SCM_MATRIX_STATUS1_MAM1_S3_DS_A_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S2_M_MASK 0x800u
#define SCM_MATRIX_STATUS1_MAM2_S2_M_SHIFT 11u
#define SCM_MATRIX_STATUS1_MAM2_S2_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S2_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S2_M_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S2_M_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S2_AT_MASK 0x400u
#define SCM_MATRIX_STATUS1_MAM2_S2_AT_SHIFT 10u
#define SCM_MATRIX_STATUS1_MAM2_S2_AT_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S2_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S2_AT_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S2_AT_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S2_D_MASK 0x200u
#define SCM_MATRIX_STATUS1_MAM2_S2_D_SHIFT 9u
#define SCM_MATRIX_STATUS1_MAM2_S2_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S2_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S2_D_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S2_D_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S2_A_MASK 0x100u
#define SCM_MATRIX_STATUS1_MAM2_S2_A_SHIFT 8u
#define SCM_MATRIX_STATUS1_MAM2_S2_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S2_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S2_A_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S2_A_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S1_M_MASK 0x80u
#define SCM_MATRIX_STATUS1_MAM2_S1_M_SHIFT 7u
#define SCM_MATRIX_STATUS1_MAM2_S1_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S1_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S1_M_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S1_M_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S1_AT_MASK 0x40u
#define SCM_MATRIX_STATUS1_MAM2_S1_AT_SHIFT 6u
#define SCM_MATRIX_STATUS1_MAM2_S1_AT_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S1_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S1_AT_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S1_AT_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S1_D_MASK 0x20u
#define SCM_MATRIX_STATUS1_MAM2_S1_D_SHIFT 5u
#define SCM_MATRIX_STATUS1_MAM2_S1_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S1_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S1_D_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S1_D_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S1_A_MASK 0x10u
#define SCM_MATRIX_STATUS1_MAM2_S1_A_SHIFT 4u
#define SCM_MATRIX_STATUS1_MAM2_S1_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S1_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S1_A_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S1_A_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S0_M_MASK 0x8u
#define SCM_MATRIX_STATUS1_MAM2_S0_M_SHIFT 3u
#define SCM_MATRIX_STATUS1_MAM2_S0_M_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S0_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S0_M_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S0_M_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S0_AT_MASK 0x4u
#define SCM_MATRIX_STATUS1_MAM2_S0_AT_SHIFT 2u
#define SCM_MATRIX_STATUS1_MAM2_S0_AT_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S0_AT(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S0_AT_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S0_AT_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S0_D_MASK 0x2u
#define SCM_MATRIX_STATUS1_MAM2_S0_D_SHIFT 1u
#define SCM_MATRIX_STATUS1_MAM2_S0_D_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S0_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S0_D_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S0_D_MASK)
#define SCM_MATRIX_STATUS1_MAM2_S0_A_MASK 0x1u
#define SCM_MATRIX_STATUS1_MAM2_S0_A_SHIFT 0u
#define SCM_MATRIX_STATUS1_MAM2_S0_A_WIDTH 1u
#define SCM_MATRIX_STATUS1_MAM2_S0_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS1_MAM2_S0_A_SHIFT))&SCM_MATRIX_STATUS1_MAM2_S0_A_MASK)
/* MATRIX_STATUS1 Reg Mask */
#define SCM_MATRIX_STATUS1_MASK        0xBBBBBFFFu

/* MATRIX_STATUS2 Bit Fields */
#define SCM_MATRIX_STATUS2_STALL_ERR_MASK 0x80000000u
#define SCM_MATRIX_STATUS2_STALL_ERR_SHIFT 31u
#define SCM_MATRIX_STATUS2_STALL_ERR_WIDTH 1u
#define SCM_MATRIX_STATUS2_STALL_ERR(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_STALL_ERR_SHIFT))&SCM_MATRIX_STATUS2_STALL_ERR_MASK)
#define SCM_MATRIX_STATUS2_MAM2_S2_DS_MASK 0x40000000u
#define SCM_MATRIX_STATUS2_MAM2_S2_DS_SHIFT 30u
#define SCM_MATRIX_STATUS2_MAM2_S2_DS_WIDTH 1u
#define SCM_MATRIX_STATUS2_MAM2_S2_DS(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_MAM2_S2_DS_SHIFT))&SCM_MATRIX_STATUS2_MAM2_S2_DS_MASK)
#define SCM_MATRIX_STATUS2_MAM1_S3_DS_MASK 0x20000000u
#define SCM_MATRIX_STATUS2_MAM1_S3_DS_SHIFT 29u
#define SCM_MATRIX_STATUS2_MAM1_S3_DS_WIDTH 1u
#define SCM_MATRIX_STATUS2_MAM1_S3_DS(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_MAM1_S3_DS_SHIFT))&SCM_MATRIX_STATUS2_MAM1_S3_DS_MASK)
#define SCM_MATRIX_STATUS2_MAM1_S3_S2F_MASK 0x10000000u
#define SCM_MATRIX_STATUS2_MAM1_S3_S2F_SHIFT 28u
#define SCM_MATRIX_STATUS2_MAM1_S3_S2F_WIDTH 1u
#define SCM_MATRIX_STATUS2_MAM1_S3_S2F(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_MAM1_S3_S2F_SHIFT))&SCM_MATRIX_STATUS2_MAM1_S3_S2F_MASK)
#define SCM_MATRIX_STATUS2_SRAM2_DEC_MASK 0x4000000u
#define SCM_MATRIX_STATUS2_SRAM2_DEC_SHIFT 26u
#define SCM_MATRIX_STATUS2_SRAM2_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_SRAM2_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_SRAM2_DEC_SHIFT))&SCM_MATRIX_STATUS2_SRAM2_DEC_MASK)
#define SCM_MATRIX_STATUS2_SRAM1_DEC_MASK 0x2000000u
#define SCM_MATRIX_STATUS2_SRAM1_DEC_SHIFT 25u
#define SCM_MATRIX_STATUS2_SRAM1_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_SRAM1_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_SRAM1_DEC_SHIFT))&SCM_MATRIX_STATUS2_SRAM1_DEC_MASK)
#define SCM_MATRIX_STATUS2_SRAM0_DEC_MASK 0x1000000u
#define SCM_MATRIX_STATUS2_SRAM0_DEC_SHIFT 24u
#define SCM_MATRIX_STATUS2_SRAM0_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_SRAM0_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_SRAM0_DEC_SHIFT))&SCM_MATRIX_STATUS2_SRAM0_DEC_MASK)
#define SCM_MATRIX_STATUS2_STCU_ST_MASK 0x200000u
#define SCM_MATRIX_STATUS2_STCU_ST_SHIFT 21u
#define SCM_MATRIX_STATUS2_STCU_ST_WIDTH 1u
#define SCM_MATRIX_STATUS2_STCU_ST(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_STCU_ST_SHIFT))&SCM_MATRIX_STATUS2_STCU_ST_MASK)
#define SCM_MATRIX_STATUS2_FCM_SCAN_MASK 0x100000u
#define SCM_MATRIX_STATUS2_FCM_SCAN_SHIFT 20u
#define SCM_MATRIX_STATUS2_FCM_SCAN_WIDTH 1u
#define SCM_MATRIX_STATUS2_FCM_SCAN(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_FCM_SCAN_SHIFT))&SCM_MATRIX_STATUS2_FCM_SCAN_MASK)
#define SCM_MATRIX_STATUS2_C0_DCACHE_MASK 0x80000u
#define SCM_MATRIX_STATUS2_C0_DCACHE_SHIFT 19u
#define SCM_MATRIX_STATUS2_C0_DCACHE_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_DCACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_DCACHE_SHIFT))&SCM_MATRIX_STATUS2_C0_DCACHE_MASK)
#define SCM_MATRIX_STATUS2_C0_ICACHE_MASK 0x40000u
#define SCM_MATRIX_STATUS2_C0_ICACHE_SHIFT 18u
#define SCM_MATRIX_STATUS2_C0_ICACHE_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_ICACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_ICACHE_SHIFT))&SCM_MATRIX_STATUS2_C0_ICACHE_MASK)
#define SCM_MATRIX_STATUS2_C0_DTCM1_DEC_MASK 0x20000u
#define SCM_MATRIX_STATUS2_C0_DTCM1_DEC_SHIFT 17u
#define SCM_MATRIX_STATUS2_C0_DTCM1_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_DTCM1_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_DTCM1_DEC_SHIFT))&SCM_MATRIX_STATUS2_C0_DTCM1_DEC_MASK)
#define SCM_MATRIX_STATUS2_C0_DTCM0_DEC_MASK 0x10000u
#define SCM_MATRIX_STATUS2_C0_DTCM0_DEC_SHIFT 16u
#define SCM_MATRIX_STATUS2_C0_DTCM0_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_DTCM0_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_DTCM0_DEC_SHIFT))&SCM_MATRIX_STATUS2_C0_DTCM0_DEC_MASK)
#define SCM_MATRIX_STATUS2_C0_ITCM_DEC_MASK 0x8000u
#define SCM_MATRIX_STATUS2_C0_ITCM_DEC_SHIFT 15u
#define SCM_MATRIX_STATUS2_C0_ITCM_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_ITCM_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_ITCM_DEC_SHIFT))&SCM_MATRIX_STATUS2_C0_ITCM_DEC_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBM1_F2S_MASK 0x4000u
#define SCM_MATRIX_STATUS2_C0_AHBM1_F2S_SHIFT 14u
#define SCM_MATRIX_STATUS2_C0_AHBM1_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBM1_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBM1_F2S_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBM1_F2S_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBM0_F2S_MASK 0x2000u
#define SCM_MATRIX_STATUS2_C0_AHBM0_F2S_SHIFT 13u
#define SCM_MATRIX_STATUS2_C0_AHBM0_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBM0_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBM0_F2S_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBM0_F2S_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBP_F2S_MASK 0x1000u
#define SCM_MATRIX_STATUS2_C0_AHBP_F2S_SHIFT 12u
#define SCM_MATRIX_STATUS2_C0_AHBP_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBP_F2S_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBP_F2S_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBM_M_MASK 0x800u
#define SCM_MATRIX_STATUS2_C0_AHBM_M_SHIFT 11u
#define SCM_MATRIX_STATUS2_C0_AHBM_M_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBM_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBM_M_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBM_M_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBM_D_MASK 0x200u
#define SCM_MATRIX_STATUS2_C0_AHBM_D_SHIFT 9u
#define SCM_MATRIX_STATUS2_C0_AHBM_D_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBM_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBM_D_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBM_D_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBM_A_MASK 0x100u
#define SCM_MATRIX_STATUS2_C0_AHBM_A_SHIFT 8u
#define SCM_MATRIX_STATUS2_C0_AHBM_A_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBM_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBM_A_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBM_A_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBS_M_MASK 0x80u
#define SCM_MATRIX_STATUS2_C0_AHBS_M_SHIFT 7u
#define SCM_MATRIX_STATUS2_C0_AHBS_M_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBS_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBS_M_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBS_M_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBS_D_MASK 0x20u
#define SCM_MATRIX_STATUS2_C0_AHBS_D_SHIFT 5u
#define SCM_MATRIX_STATUS2_C0_AHBS_D_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBS_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBS_D_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBS_D_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBS_A_MASK 0x10u
#define SCM_MATRIX_STATUS2_C0_AHBS_A_SHIFT 4u
#define SCM_MATRIX_STATUS2_C0_AHBS_A_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBS_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBS_A_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBS_A_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBP_M_MASK 0x8u
#define SCM_MATRIX_STATUS2_C0_AHBP_M_SHIFT 3u
#define SCM_MATRIX_STATUS2_C0_AHBP_M_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBP_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBP_M_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBP_M_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBP_D_MASK 0x2u
#define SCM_MATRIX_STATUS2_C0_AHBP_D_SHIFT 1u
#define SCM_MATRIX_STATUS2_C0_AHBP_D_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBP_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBP_D_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBP_D_MASK)
#define SCM_MATRIX_STATUS2_C0_AHBP_A_MASK 0x1u
#define SCM_MATRIX_STATUS2_C0_AHBP_A_SHIFT 0u
#define SCM_MATRIX_STATUS2_C0_AHBP_A_WIDTH 1u
#define SCM_MATRIX_STATUS2_C0_AHBP_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS2_C0_AHBP_A_SHIFT))&SCM_MATRIX_STATUS2_C0_AHBP_A_MASK)
/* MATRIX_STATUS2 Reg Mask */
#define SCM_MATRIX_STATUS2_MASK        0xF73FFBBBu

/* MATRIX_STATUS3 Bit Fields */
#define SCM_MATRIX_STATUS3_SRAM1_M_MASK 0x80000000u
#define SCM_MATRIX_STATUS3_SRAM1_M_SHIFT 31u
#define SCM_MATRIX_STATUS3_SRAM1_M_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM1_M(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM1_M_SHIFT))&SCM_MATRIX_STATUS3_SRAM1_M_MASK)
#define SCM_MATRIX_STATUS3_SRAM1_D_MASK 0x20000000u
#define SCM_MATRIX_STATUS3_SRAM1_D_SHIFT 29u
#define SCM_MATRIX_STATUS3_SRAM1_D_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM1_D(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM1_D_SHIFT))&SCM_MATRIX_STATUS3_SRAM1_D_MASK)
#define SCM_MATRIX_STATUS3_SRAM1_S_MASK 0x10000000u
#define SCM_MATRIX_STATUS3_SRAM1_S_SHIFT 28u
#define SCM_MATRIX_STATUS3_SRAM1_S_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM1_S(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM1_S_SHIFT))&SCM_MATRIX_STATUS3_SRAM1_S_MASK)
#define SCM_MATRIX_STATUS3_SRAM0_M_MASK 0x8000000u
#define SCM_MATRIX_STATUS3_SRAM0_M_SHIFT 27u
#define SCM_MATRIX_STATUS3_SRAM0_M_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM0_M(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM0_M_SHIFT))&SCM_MATRIX_STATUS3_SRAM0_M_MASK)
#define SCM_MATRIX_STATUS3_SRAM0_D_MASK 0x2000000u
#define SCM_MATRIX_STATUS3_SRAM0_D_SHIFT 25u
#define SCM_MATRIX_STATUS3_SRAM0_D_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM0_D(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM0_D_SHIFT))&SCM_MATRIX_STATUS3_SRAM0_D_MASK)
#define SCM_MATRIX_STATUS3_SRAM0_S_MASK 0x1000000u
#define SCM_MATRIX_STATUS3_SRAM0_S_SHIFT 24u
#define SCM_MATRIX_STATUS3_SRAM0_S_WIDTH 1u
#define SCM_MATRIX_STATUS3_SRAM0_S(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_SRAM0_S_SHIFT))&SCM_MATRIX_STATUS3_SRAM0_S_MASK)
#define SCM_MATRIX_STATUS3_C1_DCACHE_MASK 0x80000u
#define SCM_MATRIX_STATUS3_C1_DCACHE_SHIFT 19u
#define SCM_MATRIX_STATUS3_C1_DCACHE_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_DCACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_DCACHE_SHIFT))&SCM_MATRIX_STATUS3_C1_DCACHE_MASK)
#define SCM_MATRIX_STATUS3_C1_ICACHE_MASK 0x40000u
#define SCM_MATRIX_STATUS3_C1_ICACHE_SHIFT 18u
#define SCM_MATRIX_STATUS3_C1_ICACHE_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_ICACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_ICACHE_SHIFT))&SCM_MATRIX_STATUS3_C1_ICACHE_MASK)
#define SCM_MATRIX_STATUS3_C1_DTCM1_DEC_MASK 0x20000u
#define SCM_MATRIX_STATUS3_C1_DTCM1_DEC_SHIFT 17u
#define SCM_MATRIX_STATUS3_C1_DTCM1_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_DTCM1_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_DTCM1_DEC_SHIFT))&SCM_MATRIX_STATUS3_C1_DTCM1_DEC_MASK)
#define SCM_MATRIX_STATUS3_C1_DTCM0_DEC_MASK 0x10000u
#define SCM_MATRIX_STATUS3_C1_DTCM0_DEC_SHIFT 16u
#define SCM_MATRIX_STATUS3_C1_DTCM0_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_DTCM0_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_DTCM0_DEC_SHIFT))&SCM_MATRIX_STATUS3_C1_DTCM0_DEC_MASK)
#define SCM_MATRIX_STATUS3_C1_ITCM_DEC_MASK 0x8000u
#define SCM_MATRIX_STATUS3_C1_ITCM_DEC_SHIFT 15u
#define SCM_MATRIX_STATUS3_C1_ITCM_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_ITCM_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_ITCM_DEC_SHIFT))&SCM_MATRIX_STATUS3_C1_ITCM_DEC_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBM1_F2S_MASK 0x4000u
#define SCM_MATRIX_STATUS3_C1_AHBM1_F2S_SHIFT 14u
#define SCM_MATRIX_STATUS3_C1_AHBM1_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBM1_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBM1_F2S_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBM1_F2S_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBM0_F2S_MASK 0x2000u
#define SCM_MATRIX_STATUS3_C1_AHBM0_F2S_SHIFT 13u
#define SCM_MATRIX_STATUS3_C1_AHBM0_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBM0_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBM0_F2S_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBM0_F2S_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBP_F2S_MASK 0x1000u
#define SCM_MATRIX_STATUS3_C1_AHBP_F2S_SHIFT 12u
#define SCM_MATRIX_STATUS3_C1_AHBP_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBP_F2S_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBP_F2S_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBM_M_MASK 0x800u
#define SCM_MATRIX_STATUS3_C1_AHBM_M_SHIFT 11u
#define SCM_MATRIX_STATUS3_C1_AHBM_M_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBM_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBM_M_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBM_M_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBM_D_MASK 0x200u
#define SCM_MATRIX_STATUS3_C1_AHBM_D_SHIFT 9u
#define SCM_MATRIX_STATUS3_C1_AHBM_D_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBM_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBM_D_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBM_D_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBM_A_MASK 0x100u
#define SCM_MATRIX_STATUS3_C1_AHBM_A_SHIFT 8u
#define SCM_MATRIX_STATUS3_C1_AHBM_A_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBM_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBM_A_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBM_A_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBS_M_MASK 0x80u
#define SCM_MATRIX_STATUS3_C1_AHBS_M_SHIFT 7u
#define SCM_MATRIX_STATUS3_C1_AHBS_M_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBS_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBS_M_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBS_M_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBS_D_MASK 0x20u
#define SCM_MATRIX_STATUS3_C1_AHBS_D_SHIFT 5u
#define SCM_MATRIX_STATUS3_C1_AHBS_D_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBS_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBS_D_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBS_D_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBS_A_MASK 0x10u
#define SCM_MATRIX_STATUS3_C1_AHBS_A_SHIFT 4u
#define SCM_MATRIX_STATUS3_C1_AHBS_A_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBS_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBS_A_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBS_A_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBP_M_MASK 0x8u
#define SCM_MATRIX_STATUS3_C1_AHBP_M_SHIFT 3u
#define SCM_MATRIX_STATUS3_C1_AHBP_M_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBP_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBP_M_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBP_M_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBP_D_MASK 0x2u
#define SCM_MATRIX_STATUS3_C1_AHBP_D_SHIFT 1u
#define SCM_MATRIX_STATUS3_C1_AHBP_D_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBP_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBP_D_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBP_D_MASK)
#define SCM_MATRIX_STATUS3_C1_AHBP_A_MASK 0x1u
#define SCM_MATRIX_STATUS3_C1_AHBP_A_SHIFT 0u
#define SCM_MATRIX_STATUS3_C1_AHBP_A_WIDTH 1u
#define SCM_MATRIX_STATUS3_C1_AHBP_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS3_C1_AHBP_A_SHIFT))&SCM_MATRIX_STATUS3_C1_AHBP_A_MASK)
/* MATRIX_STATUS3 Reg Mask */
#define SCM_MATRIX_STATUS3_MASK        0xBB0FFBBBu

/* MATRIX_STATUS4 Bit Fields */
#define SCM_MATRIX_STATUS4_SRAM2_M_MASK 0x8000000u
#define SCM_MATRIX_STATUS4_SRAM2_M_SHIFT 27u
#define SCM_MATRIX_STATUS4_SRAM2_M_WIDTH 1u
#define SCM_MATRIX_STATUS4_SRAM2_M(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_SRAM2_M_SHIFT))&SCM_MATRIX_STATUS4_SRAM2_M_MASK)
#define SCM_MATRIX_STATUS4_SRAM2_D_MASK 0x2000000u
#define SCM_MATRIX_STATUS4_SRAM2_D_SHIFT 25u
#define SCM_MATRIX_STATUS4_SRAM2_D_WIDTH 1u
#define SCM_MATRIX_STATUS4_SRAM2_D(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_SRAM2_D_SHIFT))&SCM_MATRIX_STATUS4_SRAM2_D_MASK)
#define SCM_MATRIX_STATUS4_SRAM2_S_MASK 0x1000000u
#define SCM_MATRIX_STATUS4_SRAM2_S_SHIFT 24u
#define SCM_MATRIX_STATUS4_SRAM2_S_WIDTH 1u
#define SCM_MATRIX_STATUS4_SRAM2_S(x)  (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_SRAM2_S_SHIFT))&SCM_MATRIX_STATUS4_SRAM2_S_MASK)
#define SCM_MATRIX_STATUS4_C2_DCACHE_MASK 0x80000u
#define SCM_MATRIX_STATUS4_C2_DCACHE_SHIFT 19u
#define SCM_MATRIX_STATUS4_C2_DCACHE_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_DCACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_DCACHE_SHIFT))&SCM_MATRIX_STATUS4_C2_DCACHE_MASK)
#define SCM_MATRIX_STATUS4_C2_ICACHE_MASK 0x40000u
#define SCM_MATRIX_STATUS4_C2_ICACHE_SHIFT 18u
#define SCM_MATRIX_STATUS4_C2_ICACHE_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_ICACHE(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_ICACHE_SHIFT))&SCM_MATRIX_STATUS4_C2_ICACHE_MASK)
#define SCM_MATRIX_STATUS4_C2_DTCM1_DEC_MASK 0x20000u
#define SCM_MATRIX_STATUS4_C2_DTCM1_DEC_SHIFT 17u
#define SCM_MATRIX_STATUS4_C2_DTCM1_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_DTCM1_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_DTCM1_DEC_SHIFT))&SCM_MATRIX_STATUS4_C2_DTCM1_DEC_MASK)
#define SCM_MATRIX_STATUS4_C2_DTCM0_DEC_MASK 0x10000u
#define SCM_MATRIX_STATUS4_C2_DTCM0_DEC_SHIFT 16u
#define SCM_MATRIX_STATUS4_C2_DTCM0_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_DTCM0_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_DTCM0_DEC_SHIFT))&SCM_MATRIX_STATUS4_C2_DTCM0_DEC_MASK)
#define SCM_MATRIX_STATUS4_C2_ITCM_DEC_MASK 0x8000u
#define SCM_MATRIX_STATUS4_C2_ITCM_DEC_SHIFT 15u
#define SCM_MATRIX_STATUS4_C2_ITCM_DEC_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_ITCM_DEC(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_ITCM_DEC_SHIFT))&SCM_MATRIX_STATUS4_C2_ITCM_DEC_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBM1_F2S_MASK 0x4000u
#define SCM_MATRIX_STATUS4_C2_AHBM1_F2S_SHIFT 14u
#define SCM_MATRIX_STATUS4_C2_AHBM1_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBM1_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBM1_F2S_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBM1_F2S_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBM0_F2S_MASK 0x2000u
#define SCM_MATRIX_STATUS4_C2_AHBM0_F2S_SHIFT 13u
#define SCM_MATRIX_STATUS4_C2_AHBM0_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBM0_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBM0_F2S_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBM0_F2S_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBP_F2S_MASK 0x1000u
#define SCM_MATRIX_STATUS4_C2_AHBP_F2S_SHIFT 12u
#define SCM_MATRIX_STATUS4_C2_AHBP_F2S_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBP_F2S_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBP_F2S_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBM_M_MASK 0x800u
#define SCM_MATRIX_STATUS4_C2_AHBM_M_SHIFT 11u
#define SCM_MATRIX_STATUS4_C2_AHBM_M_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBM_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBM_M_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBM_M_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBM_D_MASK 0x200u
#define SCM_MATRIX_STATUS4_C2_AHBM_D_SHIFT 9u
#define SCM_MATRIX_STATUS4_C2_AHBM_D_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBM_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBM_D_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBM_D_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBM_A_MASK 0x100u
#define SCM_MATRIX_STATUS4_C2_AHBM_A_SHIFT 8u
#define SCM_MATRIX_STATUS4_C2_AHBM_A_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBM_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBM_A_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBM_A_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBS_M_MASK 0x80u
#define SCM_MATRIX_STATUS4_C2_AHBS_M_SHIFT 7u
#define SCM_MATRIX_STATUS4_C2_AHBS_M_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBS_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBS_M_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBS_M_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBS_D_MASK 0x20u
#define SCM_MATRIX_STATUS4_C2_AHBS_D_SHIFT 5u
#define SCM_MATRIX_STATUS4_C2_AHBS_D_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBS_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBS_D_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBS_D_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBS_A_MASK 0x10u
#define SCM_MATRIX_STATUS4_C2_AHBS_A_SHIFT 4u
#define SCM_MATRIX_STATUS4_C2_AHBS_A_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBS_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBS_A_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBS_A_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBP_M_MASK 0x8u
#define SCM_MATRIX_STATUS4_C2_AHBP_M_SHIFT 3u
#define SCM_MATRIX_STATUS4_C2_AHBP_M_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBP_M(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBP_M_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBP_M_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBP_D_MASK 0x2u
#define SCM_MATRIX_STATUS4_C2_AHBP_D_SHIFT 1u
#define SCM_MATRIX_STATUS4_C2_AHBP_D_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBP_D(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBP_D_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBP_D_MASK)
#define SCM_MATRIX_STATUS4_C2_AHBP_A_MASK 0x1u
#define SCM_MATRIX_STATUS4_C2_AHBP_A_SHIFT 0u
#define SCM_MATRIX_STATUS4_C2_AHBP_A_WIDTH 1u
#define SCM_MATRIX_STATUS4_C2_AHBP_A(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS4_C2_AHBP_A_SHIFT))&SCM_MATRIX_STATUS4_C2_AHBP_A_MASK)
/* MATRIX_STATUS4 Reg Mask */
#define SCM_MATRIX_STATUS4_MASK        0x0B0FFBBBu

/* MATRIX_STATUS5 Bit Fields */
#define SCM_MATRIX_STATUS5_EDC_MASK    0x10000u
#define SCM_MATRIX_STATUS5_EDC_SHIFT   16u
#define SCM_MATRIX_STATUS5_EDC_WIDTH   1u
#define SCM_MATRIX_STATUS5_EDC(x)      (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_EDC_SHIFT))&SCM_MATRIX_STATUS5_EDC_MASK)
#define SCM_MATRIX_STATUS5_P2_D_M_MASK 0x4000u
#define SCM_MATRIX_STATUS5_P2_D_M_SHIFT 14u
#define SCM_MATRIX_STATUS5_P2_D_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P2_D_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P2_D_M_SHIFT))&SCM_MATRIX_STATUS5_P2_D_M_MASK)
#define SCM_MATRIX_STATUS5_P1_D_M_MASK 0x2000u
#define SCM_MATRIX_STATUS5_P1_D_M_SHIFT 13u
#define SCM_MATRIX_STATUS5_P1_D_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P1_D_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P1_D_M_SHIFT))&SCM_MATRIX_STATUS5_P1_D_M_MASK)
#define SCM_MATRIX_STATUS5_P0_D_M_MASK 0x1000u
#define SCM_MATRIX_STATUS5_P0_D_M_SHIFT 12u
#define SCM_MATRIX_STATUS5_P0_D_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P0_D_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P0_D_M_SHIFT))&SCM_MATRIX_STATUS5_P0_D_M_MASK)
#define SCM_MATRIX_STATUS5_P2_C_M_MASK 0x400u
#define SCM_MATRIX_STATUS5_P2_C_M_SHIFT 10u
#define SCM_MATRIX_STATUS5_P2_C_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P2_C_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P2_C_M_SHIFT))&SCM_MATRIX_STATUS5_P2_C_M_MASK)
#define SCM_MATRIX_STATUS5_P1_C_M_MASK 0x200u
#define SCM_MATRIX_STATUS5_P1_C_M_SHIFT 9u
#define SCM_MATRIX_STATUS5_P1_C_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P1_C_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P1_C_M_SHIFT))&SCM_MATRIX_STATUS5_P1_C_M_MASK)
#define SCM_MATRIX_STATUS5_P0_C_M_MASK 0x100u
#define SCM_MATRIX_STATUS5_P0_C_M_SHIFT 8u
#define SCM_MATRIX_STATUS5_P0_C_M_WIDTH 1u
#define SCM_MATRIX_STATUS5_P0_C_M(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P0_C_M_SHIFT))&SCM_MATRIX_STATUS5_P0_C_M_MASK)
#define SCM_MATRIX_STATUS5_P2_D_S_MASK 0x40u
#define SCM_MATRIX_STATUS5_P2_D_S_SHIFT 6u
#define SCM_MATRIX_STATUS5_P2_D_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P2_D_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P2_D_S_SHIFT))&SCM_MATRIX_STATUS5_P2_D_S_MASK)
#define SCM_MATRIX_STATUS5_P1_D_S_MASK 0x20u
#define SCM_MATRIX_STATUS5_P1_D_S_SHIFT 5u
#define SCM_MATRIX_STATUS5_P1_D_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P1_D_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P1_D_S_SHIFT))&SCM_MATRIX_STATUS5_P1_D_S_MASK)
#define SCM_MATRIX_STATUS5_P0_D_S_MASK 0x10u
#define SCM_MATRIX_STATUS5_P0_D_S_SHIFT 4u
#define SCM_MATRIX_STATUS5_P0_D_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P0_D_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P0_D_S_SHIFT))&SCM_MATRIX_STATUS5_P0_D_S_MASK)
#define SCM_MATRIX_STATUS5_P2_C_S_MASK 0x4u
#define SCM_MATRIX_STATUS5_P2_C_S_SHIFT 2u
#define SCM_MATRIX_STATUS5_P2_C_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P2_C_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P2_C_S_SHIFT))&SCM_MATRIX_STATUS5_P2_C_S_MASK)
#define SCM_MATRIX_STATUS5_P1_C_S_MASK 0x2u
#define SCM_MATRIX_STATUS5_P1_C_S_SHIFT 1u
#define SCM_MATRIX_STATUS5_P1_C_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P1_C_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P1_C_S_SHIFT))&SCM_MATRIX_STATUS5_P1_C_S_MASK)
#define SCM_MATRIX_STATUS5_P0_C_S_MASK 0x1u
#define SCM_MATRIX_STATUS5_P0_C_S_SHIFT 0u
#define SCM_MATRIX_STATUS5_P0_C_S_WIDTH 1u
#define SCM_MATRIX_STATUS5_P0_C_S(x)   (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_STATUS5_P0_C_S_SHIFT))&SCM_MATRIX_STATUS5_P0_C_S_MASK)
/* MATRIX_STATUS5 Reg Mask */
#define SCM_MATRIX_STATUS5_MASK        0x00017777u

/* MATRIX_ID_STATUS0 Bit Fields */
#define SCM_MATRIX_ID_STATUS0_SRAM2_ID_MASK 0xF000000u
#define SCM_MATRIX_ID_STATUS0_SRAM2_ID_SHIFT 24u
#define SCM_MATRIX_ID_STATUS0_SRAM2_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_SRAM2_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_SRAM2_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_SRAM2_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_SRAM1_ID_MASK 0xF00000u
#define SCM_MATRIX_ID_STATUS0_SRAM1_ID_SHIFT 20u
#define SCM_MATRIX_ID_STATUS0_SRAM1_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_SRAM1_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_SRAM1_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_SRAM1_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_SRAM0_ID_MASK 0xF0000u
#define SCM_MATRIX_ID_STATUS0_SRAM0_ID_SHIFT 16u
#define SCM_MATRIX_ID_STATUS0_SRAM0_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_SRAM0_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_SRAM0_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_SRAM0_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_MAM1_S3_ID_MASK 0xF000u
#define SCM_MATRIX_ID_STATUS0_MAM1_S3_ID_SHIFT 12u
#define SCM_MATRIX_ID_STATUS0_MAM1_S3_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_MAM1_S3_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_MAM1_S3_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_MAM1_S3_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_MAM1_S2_ID_MASK 0xF00u
#define SCM_MATRIX_ID_STATUS0_MAM1_S2_ID_SHIFT 8u
#define SCM_MATRIX_ID_STATUS0_MAM1_S2_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_MAM1_S2_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_MAM1_S2_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_MAM1_S2_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_MAM1_S1_ID_MASK 0xF0u
#define SCM_MATRIX_ID_STATUS0_MAM1_S1_ID_SHIFT 4u
#define SCM_MATRIX_ID_STATUS0_MAM1_S1_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_MAM1_S1_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_MAM1_S1_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_MAM1_S1_ID_MASK)
#define SCM_MATRIX_ID_STATUS0_MAM1_S0_ID_MASK 0xFu
#define SCM_MATRIX_ID_STATUS0_MAM1_S0_ID_SHIFT 0u
#define SCM_MATRIX_ID_STATUS0_MAM1_S0_ID_WIDTH 4u
#define SCM_MATRIX_ID_STATUS0_MAM1_S0_ID(x) (((uint32_t)(((uint32_t)(x))<<SCM_MATRIX_ID_STATUS0_MAM1_S0_ID_SHIFT))&SCM_MATRIX_ID_STATUS0_MAM1_S0_ID_MASK)
/* MATRIX_ID_STATUS0 Reg Mask */
#define SCM_MATRIX_ID_STATUS0_MASK     0x0FFFFFFFu

/* CPU0_TXRX_EN Bit Fields */
#define SCM_CPU0_TXRX_EN_WPB_LOCK_MASK 0x80000000u
#define SCM_CPU0_TXRX_EN_WPB_LOCK_SHIFT 31u
#define SCM_CPU0_TXRX_EN_WPB_LOCK_WIDTH 1u
#define SCM_CPU0_TXRX_EN_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<SCM_CPU0_TXRX_EN_WPB_LOCK_SHIFT))&SCM_CPU0_TXRX_EN_WPB_LOCK_MASK)
#define SCM_CPU0_TXRX_EN_WPB_MASK      0x70000000u
#define SCM_CPU0_TXRX_EN_WPB_SHIFT     28u
#define SCM_CPU0_TXRX_EN_WPB_WIDTH     3u
#define SCM_CPU0_TXRX_EN_WPB(x)        (((uint32_t)(((uint32_t)(x))<<SCM_CPU0_TXRX_EN_WPB_SHIFT))&SCM_CPU0_TXRX_EN_WPB_MASK)
#define SCM_CPU0_TXRX_EN_CPU2_EN_MASK  0x4u
#define SCM_CPU0_TXRX_EN_CPU2_EN_SHIFT 2u
#define SCM_CPU0_TXRX_EN_CPU2_EN_WIDTH 1u
#define SCM_CPU0_TXRX_EN_CPU2_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU0_TXRX_EN_CPU2_EN_SHIFT))&SCM_CPU0_TXRX_EN_CPU2_EN_MASK)
#define SCM_CPU0_TXRX_EN_CPU1_EN_MASK  0x2u
#define SCM_CPU0_TXRX_EN_CPU1_EN_SHIFT 1u
#define SCM_CPU0_TXRX_EN_CPU1_EN_WIDTH 1u
#define SCM_CPU0_TXRX_EN_CPU1_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU0_TXRX_EN_CPU1_EN_SHIFT))&SCM_CPU0_TXRX_EN_CPU1_EN_MASK)
/* CPU0_TXRX_EN Reg Mask */
#define SCM_CPU0_TXRX_EN_MASK          0xF0000006u

/* CPU1_TXRX_EN Bit Fields */
#define SCM_CPU1_TXRX_EN_WPB_LOCK_MASK 0x80000000u
#define SCM_CPU1_TXRX_EN_WPB_LOCK_SHIFT 31u
#define SCM_CPU1_TXRX_EN_WPB_LOCK_WIDTH 1u
#define SCM_CPU1_TXRX_EN_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<SCM_CPU1_TXRX_EN_WPB_LOCK_SHIFT))&SCM_CPU1_TXRX_EN_WPB_LOCK_MASK)
#define SCM_CPU1_TXRX_EN_WPB_MASK      0x70000000u
#define SCM_CPU1_TXRX_EN_WPB_SHIFT     28u
#define SCM_CPU1_TXRX_EN_WPB_WIDTH     3u
#define SCM_CPU1_TXRX_EN_WPB(x)        (((uint32_t)(((uint32_t)(x))<<SCM_CPU1_TXRX_EN_WPB_SHIFT))&SCM_CPU1_TXRX_EN_WPB_MASK)
#define SCM_CPU1_TXRX_EN_CPU2_EN_MASK  0x4u
#define SCM_CPU1_TXRX_EN_CPU2_EN_SHIFT 2u
#define SCM_CPU1_TXRX_EN_CPU2_EN_WIDTH 1u
#define SCM_CPU1_TXRX_EN_CPU2_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU1_TXRX_EN_CPU2_EN_SHIFT))&SCM_CPU1_TXRX_EN_CPU2_EN_MASK)
#define SCM_CPU1_TXRX_EN_CPU0_EN_MASK  0x1u
#define SCM_CPU1_TXRX_EN_CPU0_EN_SHIFT 0u
#define SCM_CPU1_TXRX_EN_CPU0_EN_WIDTH 1u
#define SCM_CPU1_TXRX_EN_CPU0_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU1_TXRX_EN_CPU0_EN_SHIFT))&SCM_CPU1_TXRX_EN_CPU0_EN_MASK)
/* CPU1_TXRX_EN Reg Mask */
#define SCM_CPU1_TXRX_EN_MASK          0xF0000005u

/* CPU2_TXRX_EN Bit Fields */
#define SCM_CPU2_TXRX_EN_WPB_LOCK_MASK 0x80000000u
#define SCM_CPU2_TXRX_EN_WPB_LOCK_SHIFT 31u
#define SCM_CPU2_TXRX_EN_WPB_LOCK_WIDTH 1u
#define SCM_CPU2_TXRX_EN_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<SCM_CPU2_TXRX_EN_WPB_LOCK_SHIFT))&SCM_CPU2_TXRX_EN_WPB_LOCK_MASK)
#define SCM_CPU2_TXRX_EN_WPB_MASK      0x70000000u
#define SCM_CPU2_TXRX_EN_WPB_SHIFT     28u
#define SCM_CPU2_TXRX_EN_WPB_WIDTH     3u
#define SCM_CPU2_TXRX_EN_WPB(x)        (((uint32_t)(((uint32_t)(x))<<SCM_CPU2_TXRX_EN_WPB_SHIFT))&SCM_CPU2_TXRX_EN_WPB_MASK)
#define SCM_CPU2_TXRX_EN_CPU1_EN_MASK  0x2u
#define SCM_CPU2_TXRX_EN_CPU1_EN_SHIFT 1u
#define SCM_CPU2_TXRX_EN_CPU1_EN_WIDTH 1u
#define SCM_CPU2_TXRX_EN_CPU1_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU2_TXRX_EN_CPU1_EN_SHIFT))&SCM_CPU2_TXRX_EN_CPU1_EN_MASK)
#define SCM_CPU2_TXRX_EN_CPU0_EN_MASK  0x1u
#define SCM_CPU2_TXRX_EN_CPU0_EN_SHIFT 0u
#define SCM_CPU2_TXRX_EN_CPU0_EN_WIDTH 1u
#define SCM_CPU2_TXRX_EN_CPU0_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_CPU2_TXRX_EN_CPU0_EN_SHIFT))&SCM_CPU2_TXRX_EN_CPU0_EN_MASK)
/* CPU2_TXRX_EN Reg Mask */
#define SCM_CPU2_TXRX_EN_MASK          0xF0000003u

/* SYSAP_MDO Bit Fields */
#define SCM_SYSAP_MDO_SYSAP_MDO_MASK   0xFFFFFFFFu
#define SCM_SYSAP_MDO_SYSAP_MDO_SHIFT  0u
#define SCM_SYSAP_MDO_SYSAP_MDO_WIDTH  32u
#define SCM_SYSAP_MDO_SYSAP_MDO(x)     (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_MDO_SYSAP_MDO_SHIFT))&SCM_SYSAP_MDO_SYSAP_MDO_MASK)
/* SYSAP_MDO Reg Mask */
#define SCM_SYSAP_MDO_MASK             0xFFFFFFFFu

/* SYSAP_MDI Bit Fields */
#define SCM_SYSAP_MDI_SYSAP_MDI_MASK   0xFFFFFFFFu
#define SCM_SYSAP_MDI_SYSAP_MDI_SHIFT  0u
#define SCM_SYSAP_MDI_SYSAP_MDI_WIDTH  32u
#define SCM_SYSAP_MDI_SYSAP_MDI(x)     (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_MDI_SYSAP_MDI_SHIFT))&SCM_SYSAP_MDI_SYSAP_MDI_MASK)
/* SYSAP_MDI Reg Mask */
#define SCM_SYSAP_MDI_MASK             0xFFFFFFFFu

/* SYSAP_CTRL Bit Fields */
#define SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_MASK 0x20000u
#define SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_SHIFT 17u
#define SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_WIDTH 1u
#define SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_SHIFT))&SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_MASK)
#define SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN_MASK 0x10000u
#define SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN_SHIFT 16u
#define SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN_WIDTH 1u
#define SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN_SHIFT))&SCM_SYSAP_CTRL_MASS_ERASE_CHIP_ERASE_EN_MASK)
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_MASK 0x4000u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_SHIFT 14u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_WIDTH 1u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_SHIFT))&SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_MASK)
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_MASK 0x2000u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_SHIFT 13u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_WIDTH 1u
#define SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_SHIFT))&SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_MASK)
#define SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_MASK 0x1000u
#define SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_SHIFT 12u
#define SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_WIDTH 1u
#define SCM_SYSAP_CTRL_SYSTEM_RESET_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_SHIFT))&SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_MASK)
#define SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_MASK 0x800u
#define SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_SHIFT 11u
#define SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_WIDTH 1u
#define SCM_SYSAP_CTRL_CPU_DEBUG_RESTART(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_SHIFT))&SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_MASK)
#define SCM_SYSAP_CTRL_CPU_DEBUG_REQ_MASK 0x3FCu
#define SCM_SYSAP_CTRL_CPU_DEBUG_REQ_SHIFT 2u
#define SCM_SYSAP_CTRL_CPU_DEBUG_REQ_WIDTH 8u
#define SCM_SYSAP_CTRL_CPU_DEBUG_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_CPU_DEBUG_REQ_SHIFT))&SCM_SYSAP_CTRL_CPU_DEBUG_REQ_MASK)
#define SCM_SYSAP_CTRL_DEBUG_DIS_MASK  0x2u
#define SCM_SYSAP_CTRL_DEBUG_DIS_SHIFT 1u
#define SCM_SYSAP_CTRL_DEBUG_DIS_WIDTH 1u
#define SCM_SYSAP_CTRL_DEBUG_DIS(x)    (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_DEBUG_DIS_SHIFT))&SCM_SYSAP_CTRL_DEBUG_DIS_MASK)
#define SCM_SYSAP_CTRL_FLASH_MASS_ERASE_MASK 0x1u
#define SCM_SYSAP_CTRL_FLASH_MASS_ERASE_SHIFT 0u
#define SCM_SYSAP_CTRL_FLASH_MASS_ERASE_WIDTH 1u
#define SCM_SYSAP_CTRL_FLASH_MASS_ERASE(x) (((uint32_t)(((uint32_t)(x))<<SCM_SYSAP_CTRL_FLASH_MASS_ERASE_SHIFT))&SCM_SYSAP_CTRL_FLASH_MASS_ERASE_MASK)
/* SYSAP_CTRL Reg Mask */
#define SCM_SYSAP_CTRL_MASK            0x00037BFFu

/* HSM_PCC Bit Fields */
#define SCM_HSM_PCC_WPB_LOCK_MASK      0x80000000u
#define SCM_HSM_PCC_WPB_LOCK_SHIFT     31u
#define SCM_HSM_PCC_WPB_LOCK_WIDTH     1u
#define SCM_HSM_PCC_WPB_LOCK(x)        (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_WPB_LOCK_SHIFT))&SCM_HSM_PCC_WPB_LOCK_MASK)
#define SCM_HSM_PCC_WPB_MASK           0x70000000u
#define SCM_HSM_PCC_WPB_SHIFT          28u
#define SCM_HSM_PCC_WPB_WIDTH          3u
#define SCM_HSM_PCC_WPB(x)             (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_WPB_SHIFT))&SCM_HSM_PCC_WPB_MASK)
#define SCM_HSM_PCC_CLKEN_MASK         0x800000u
#define SCM_HSM_PCC_CLKEN_SHIFT        23u
#define SCM_HSM_PCC_CLKEN_WIDTH        1u
#define SCM_HSM_PCC_CLKEN(x)           (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_CLKEN_SHIFT))&SCM_HSM_PCC_CLKEN_MASK)
#define SCM_HSM_PCC_SWRST_MASK         0x10000u
#define SCM_HSM_PCC_SWRST_SHIFT        16u
#define SCM_HSM_PCC_SWRST_WIDTH        1u
#define SCM_HSM_PCC_SWRST(x)           (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_SWRST_SHIFT))&SCM_HSM_PCC_SWRST_MASK)
#define SCM_HSM_PCC_WDG_RSTEN_MASK     0x10u
#define SCM_HSM_PCC_WDG_RSTEN_SHIFT    4u
#define SCM_HSM_PCC_WDG_RSTEN_WIDTH    1u
#define SCM_HSM_PCC_WDG_RSTEN(x)       (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_WDG_RSTEN_SHIFT))&SCM_HSM_PCC_WDG_RSTEN_MASK)
#define SCM_HSM_PCC_STOP_REQ_MASK      0x1u
#define SCM_HSM_PCC_STOP_REQ_SHIFT     0u
#define SCM_HSM_PCC_STOP_REQ_WIDTH     1u
#define SCM_HSM_PCC_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x))<<SCM_HSM_PCC_STOP_REQ_SHIFT))&SCM_HSM_PCC_STOP_REQ_MASK)
/* HSM_PCC Reg Mask */
#define SCM_HSM_PCC_MASK               0xF0810011u

/* HSM_STATUS Bit Fields */
#define SCM_HSM_STATUS_HSM_RST_MASK    0x40u
#define SCM_HSM_STATUS_HSM_RST_SHIFT   6u
#define SCM_HSM_STATUS_HSM_RST_WIDTH   1u
#define SCM_HSM_STATUS_HSM_RST(x)      (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_HSM_RST_SHIFT))&SCM_HSM_STATUS_HSM_RST_MASK)
#define SCM_HSM_STATUS_HSM_SYS_ERR_INT_MASK 0x20u
#define SCM_HSM_STATUS_HSM_SYS_ERR_INT_SHIFT 5u
#define SCM_HSM_STATUS_HSM_SYS_ERR_INT_WIDTH 1u
#define SCM_HSM_STATUS_HSM_SYS_ERR_INT(x) (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_HSM_SYS_ERR_INT_SHIFT))&SCM_HSM_STATUS_HSM_SYS_ERR_INT_MASK)
#define SCM_HSM_STATUS_WDG_RST_MASK    0x10u
#define SCM_HSM_STATUS_WDG_RST_SHIFT   4u
#define SCM_HSM_STATUS_WDG_RST_WIDTH   1u
#define SCM_HSM_STATUS_WDG_RST(x)      (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_WDG_RST_SHIFT))&SCM_HSM_STATUS_WDG_RST_MASK)
#define SCM_HSM_STATUS_INIT_DONE_MASK  0x8u
#define SCM_HSM_STATUS_INIT_DONE_SHIFT 3u
#define SCM_HSM_STATUS_INIT_DONE_WIDTH 1u
#define SCM_HSM_STATUS_INIT_DONE(x)    (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_INIT_DONE_SHIFT))&SCM_HSM_STATUS_INIT_DONE_MASK)
#define SCM_HSM_STATUS_ISP_TOGGLE_MASK 0x4u
#define SCM_HSM_STATUS_ISP_TOGGLE_SHIFT 2u
#define SCM_HSM_STATUS_ISP_TOGGLE_WIDTH 1u
#define SCM_HSM_STATUS_ISP_TOGGLE(x)   (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_ISP_TOGGLE_SHIFT))&SCM_HSM_STATUS_ISP_TOGGLE_MASK)
#define SCM_HSM_STATUS_HSM_SLEEP_MASK  0x2u
#define SCM_HSM_STATUS_HSM_SLEEP_SHIFT 1u
#define SCM_HSM_STATUS_HSM_SLEEP_WIDTH 1u
#define SCM_HSM_STATUS_HSM_SLEEP(x)    (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_HSM_SLEEP_SHIFT))&SCM_HSM_STATUS_HSM_SLEEP_MASK)
#define SCM_HSM_STATUS_STOP_ACK_MASK   0x1u
#define SCM_HSM_STATUS_STOP_ACK_SHIFT  0u
#define SCM_HSM_STATUS_STOP_ACK_WIDTH  1u
#define SCM_HSM_STATUS_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x))<<SCM_HSM_STATUS_STOP_ACK_SHIFT))&SCM_HSM_STATUS_STOP_ACK_MASK)
/* HSM_STATUS Reg Mask */
#define SCM_HSM_STATUS_MASK            0x0000007Fu

/* MDO_FLAG Bit Fields */
#define SCM_MDO_FLAG_MDO_FLAG_MASK     0x1u
#define SCM_MDO_FLAG_MDO_FLAG_SHIFT    0u
#define SCM_MDO_FLAG_MDO_FLAG_WIDTH    1u
#define SCM_MDO_FLAG_MDO_FLAG(x)       (((uint32_t)(((uint32_t)(x))<<SCM_MDO_FLAG_MDO_FLAG_SHIFT))&SCM_MDO_FLAG_MDO_FLAG_MASK)
/* MDO_FLAG Reg Mask */
#define SCM_MDO_FLAG_MASK              0x00000001u

/* MASTER_HALT_REQ Bit Fields */
#define SCM_MASTER_HALT_REQ_WPB_LOCK_MASK 0x80000000u
#define SCM_MASTER_HALT_REQ_WPB_LOCK_SHIFT 31u
#define SCM_MASTER_HALT_REQ_WPB_LOCK_WIDTH 1u
#define SCM_MASTER_HALT_REQ_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_WPB_LOCK_SHIFT))&SCM_MASTER_HALT_REQ_WPB_LOCK_MASK)
#define SCM_MASTER_HALT_REQ_WPB_MASK   0x70000000u
#define SCM_MASTER_HALT_REQ_WPB_SHIFT  28u
#define SCM_MASTER_HALT_REQ_WPB_WIDTH  3u
#define SCM_MASTER_HALT_REQ_WPB(x)     (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_WPB_SHIFT))&SCM_MASTER_HALT_REQ_WPB_MASK)
#define SCM_MASTER_HALT_REQ_DMA1_REQ_MASK 0x1000000u
#define SCM_MASTER_HALT_REQ_DMA1_REQ_SHIFT 24u
#define SCM_MASTER_HALT_REQ_DMA1_REQ_WIDTH 1u
#define SCM_MASTER_HALT_REQ_DMA1_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_DMA1_REQ_SHIFT))&SCM_MASTER_HALT_REQ_DMA1_REQ_MASK)
#define SCM_MASTER_HALT_REQ_DMA0_REQ_MASK 0x10000u
#define SCM_MASTER_HALT_REQ_DMA0_REQ_SHIFT 16u
#define SCM_MASTER_HALT_REQ_DMA0_REQ_WIDTH 1u
#define SCM_MASTER_HALT_REQ_DMA0_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_DMA0_REQ_SHIFT))&SCM_MASTER_HALT_REQ_DMA0_REQ_MASK)
#define SCM_MASTER_HALT_REQ_ENET_REQ_MASK 0x100u
#define SCM_MASTER_HALT_REQ_ENET_REQ_SHIFT 8u
#define SCM_MASTER_HALT_REQ_ENET_REQ_WIDTH 1u
#define SCM_MASTER_HALT_REQ_ENET_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_ENET_REQ_SHIFT))&SCM_MASTER_HALT_REQ_ENET_REQ_MASK)
#define SCM_MASTER_HALT_REQ_HSM_REQ_MASK 0x1u
#define SCM_MASTER_HALT_REQ_HSM_REQ_SHIFT 0u
#define SCM_MASTER_HALT_REQ_HSM_REQ_WIDTH 1u
#define SCM_MASTER_HALT_REQ_HSM_REQ(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_REQ_HSM_REQ_SHIFT))&SCM_MASTER_HALT_REQ_HSM_REQ_MASK)
/* MASTER_HALT_REQ Reg Mask */
#define SCM_MASTER_HALT_REQ_MASK       0xF1010101u

/* MASTER_HALT_ACK Bit Fields */
#define SCM_MASTER_HALT_ACK_DMA1_ACK_MASK 0x7000000u
#define SCM_MASTER_HALT_ACK_DMA1_ACK_SHIFT 24u
#define SCM_MASTER_HALT_ACK_DMA1_ACK_WIDTH 3u
#define SCM_MASTER_HALT_ACK_DMA1_ACK(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_ACK_DMA1_ACK_SHIFT))&SCM_MASTER_HALT_ACK_DMA1_ACK_MASK)
#define SCM_MASTER_HALT_ACK_DMA0_ACK_MASK 0x70000u
#define SCM_MASTER_HALT_ACK_DMA0_ACK_SHIFT 16u
#define SCM_MASTER_HALT_ACK_DMA0_ACK_WIDTH 3u
#define SCM_MASTER_HALT_ACK_DMA0_ACK(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_ACK_DMA0_ACK_SHIFT))&SCM_MASTER_HALT_ACK_DMA0_ACK_MASK)
#define SCM_MASTER_HALT_ACK_ENET_ACK_MASK 0x700u
#define SCM_MASTER_HALT_ACK_ENET_ACK_SHIFT 8u
#define SCM_MASTER_HALT_ACK_ENET_ACK_WIDTH 3u
#define SCM_MASTER_HALT_ACK_ENET_ACK(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_ACK_ENET_ACK_SHIFT))&SCM_MASTER_HALT_ACK_ENET_ACK_MASK)
#define SCM_MASTER_HALT_ACK_HSM_ACK_MASK 0x7u
#define SCM_MASTER_HALT_ACK_HSM_ACK_SHIFT 0u
#define SCM_MASTER_HALT_ACK_HSM_ACK_WIDTH 3u
#define SCM_MASTER_HALT_ACK_HSM_ACK(x) (((uint32_t)(((uint32_t)(x))<<SCM_MASTER_HALT_ACK_HSM_ACK_SHIFT))&SCM_MASTER_HALT_ACK_HSM_ACK_MASK)
/* MASTER_HALT_ACK Reg Mask */
#define SCM_MASTER_HALT_ACK_MASK       0x07070707u

/* INT_ROUTER_NMI Bit Fields */
#define SCM_INT_ROUTER_NMI_C2_EN_MASK  0x4000000u
#define SCM_INT_ROUTER_NMI_C2_EN_SHIFT 26u
#define SCM_INT_ROUTER_NMI_C2_EN_WIDTH 1u
#define SCM_INT_ROUTER_NMI_C2_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_NMI_C2_EN_SHIFT))&SCM_INT_ROUTER_NMI_C2_EN_MASK)
#define SCM_INT_ROUTER_NMI_C1_EN_MASK  0x2000000u
#define SCM_INT_ROUTER_NMI_C1_EN_SHIFT 25u
#define SCM_INT_ROUTER_NMI_C1_EN_WIDTH 1u
#define SCM_INT_ROUTER_NMI_C1_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_NMI_C1_EN_SHIFT))&SCM_INT_ROUTER_NMI_C1_EN_MASK)
#define SCM_INT_ROUTER_NMI_C0_EN_MASK  0x1000000u
#define SCM_INT_ROUTER_NMI_C0_EN_SHIFT 24u
#define SCM_INT_ROUTER_NMI_C0_EN_WIDTH 1u
#define SCM_INT_ROUTER_NMI_C0_EN(x)    (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_NMI_C0_EN_SHIFT))&SCM_INT_ROUTER_NMI_C0_EN_MASK)
#define SCM_INT_ROUTER_NMI_LOCK_MASK   0x1u
#define SCM_INT_ROUTER_NMI_LOCK_SHIFT  0u
#define SCM_INT_ROUTER_NMI_LOCK_WIDTH  1u
#define SCM_INT_ROUTER_NMI_LOCK(x)     (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_NMI_LOCK_SHIFT))&SCM_INT_ROUTER_NMI_LOCK_MASK)
/* INT_ROUTER_NMI Reg Mask */
#define SCM_INT_ROUTER_NMI_MASK        0x07000001u

/* INT_ROUTER Bit Fields */
#define SCM_INT_ROUTER_C2_EN_MASK      0x4000000u
#define SCM_INT_ROUTER_C2_EN_SHIFT     26u
#define SCM_INT_ROUTER_C2_EN_WIDTH     1u
#define SCM_INT_ROUTER_C2_EN(x)        (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_C2_EN_SHIFT))&SCM_INT_ROUTER_C2_EN_MASK)
#define SCM_INT_ROUTER_C1_EN_MASK      0x2000000u
#define SCM_INT_ROUTER_C1_EN_SHIFT     25u
#define SCM_INT_ROUTER_C1_EN_WIDTH     1u
#define SCM_INT_ROUTER_C1_EN(x)        (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_C1_EN_SHIFT))&SCM_INT_ROUTER_C1_EN_MASK)
#define SCM_INT_ROUTER_C0_EN_MASK      0x1000000u
#define SCM_INT_ROUTER_C0_EN_SHIFT     24u
#define SCM_INT_ROUTER_C0_EN_WIDTH     1u
#define SCM_INT_ROUTER_C0_EN(x)        (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_C0_EN_SHIFT))&SCM_INT_ROUTER_C0_EN_MASK)
#define SCM_INT_ROUTER_LOCK_MASK       0x1u
#define SCM_INT_ROUTER_LOCK_SHIFT      0u
#define SCM_INT_ROUTER_LOCK_WIDTH      1u
#define SCM_INT_ROUTER_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<SCM_INT_ROUTER_LOCK_SHIFT))&SCM_INT_ROUTER_LOCK_MASK)
/* INT_ROUTER0 Reg Mask */
#define SCM_INT_ROUTER_MASK            0x07000001u

/* CRCCSR Bit Fields */
#define SCM_CRCCSR_ERR_MASK            0x20u
#define SCM_CRCCSR_ERR_SHIFT           5u
#define SCM_CRCCSR_ERR_WIDTH           1u
#define SCM_CRCCSR_ERR(x)              (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_ERR_SHIFT))&SCM_CRCCSR_ERR_MASK)
#define SCM_CRCCSR_BUY_MASK            0x10u
#define SCM_CRCCSR_BUY_SHIFT           4u
#define SCM_CRCCSR_BUY_WIDTH           1u
#define SCM_CRCCSR_BUY(x)              (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_BUY_SHIFT))&SCM_CRCCSR_BUY_MASK)
#define SCM_CRCCSR_EOEN_MASK           0x8u
#define SCM_CRCCSR_EOEN_SHIFT          3u
#define SCM_CRCCSR_EOEN_WIDTH          1u
#define SCM_CRCCSR_EOEN(x)             (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_EOEN_SHIFT))&SCM_CRCCSR_EOEN_MASK)
#define SCM_CRCCSR_CHKEN_MASK          0x4u
#define SCM_CRCCSR_CHKEN_SHIFT         2u
#define SCM_CRCCSR_CHKEN_WIDTH         1u
#define SCM_CRCCSR_CHKEN(x)            (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_CHKEN_SHIFT))&SCM_CRCCSR_CHKEN_MASK)
#define SCM_CRCCSR_TRGEN_MASK          0x2u
#define SCM_CRCCSR_TRGEN_SHIFT         1u
#define SCM_CRCCSR_TRGEN_WIDTH         1u
#define SCM_CRCCSR_TRGEN(x)            (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_TRGEN_SHIFT))&SCM_CRCCSR_TRGEN_MASK)
#define SCM_CRCCSR_GEN_MASK            0x1u
#define SCM_CRCCSR_GEN_SHIFT           0u
#define SCM_CRCCSR_GEN_WIDTH           1u
#define SCM_CRCCSR_GEN(x)              (((uint32_t)(((uint32_t)(x))<<SCM_CRCCSR_GEN_SHIFT))&SCM_CRCCSR_GEN_MASK)
/* CRCCSR Reg Mask */
#define SCM_CRCCSR_MASK                0x0000003Fu

/* CRCRES Bit Fields */
#define SCM_CRCRES_RESULT_MASK         0xFFFFFFFFu
#define SCM_CRCRES_RESULT_SHIFT        0u
#define SCM_CRCRES_RESULT_WIDTH        32u
#define SCM_CRCRES_RESULT(x)           (((uint32_t)(((uint32_t)(x))<<SCM_CRCRES_RESULT_SHIFT))&SCM_CRCRES_RESULT_MASK)
/* CRCRES Reg Mask */
#define SCM_CRCRES_MASK                0xFFFFFFFFu


/*!
 * @}
 */ /* end of group SCM_Register_Masks */

/*!
 * @}
 */ /* end of group SCM_Peripheral_Access_Layer */

#endif
