#ifndef _MODULE_MB_gmbhdijq129_REGS_H_MB_H_
#define _MODULE_MB_gmbhdijq129_REGS_H_MB_H_

/* ----------------------------------------------------------------------------
   -- MB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MB_Peripheral_Access_Layer MB Peripheral Access Layer
 * @{
 */

/** MB - Size of Registers Arrays */

/** MB - Register Layout Typedef */
typedef struct {
	struct
	{
		__I  uint32_t CCn_SEMA                   ; /* MB_CCn_SEMA, offset: 0x000 */
		__IO uint32_t CCn_SEMA_UNLK              ; /* CCn_SEMA_UNLK, offset: 0x004 */
		__O  uint32_t CCn_REQUEST                ; /* CCn_REQUEST, offset: 0x008 */
		__IO uint32_t CCn_DONE                   ; /* CCn_DONE, offset: 0x00C */
		__IO uint32_t CCn_DONE_MASK              ; /* MB_CCn_DONE_MASK, offset: 0x010 */
		__IO uint32_t CCn_DATA0                  ; /* CCn_DATA0, offset: 0x014 */
		__IO uint32_t CCn_DATA1                  ; /* CCn_DATA1, offset: 0x018 */
		__I  uint32_t CCn_STAT                   ; /* CCn_STAT, offset: 0x01C */
		__O  uint32_t CCn_CLR                    ; /* CCn_CLR, offset: 0x020 */
			 uint8_t  RESERVED_0[12];
	} CHANNEL[8];
	uint8_t  RESERVED_15[1664];
	struct
	{
		__IO uint32_t CCn_FLG                    ; /* CCn_FLG, offset: 0x800 */
		__IO uint32_t CCn_FLG_MASK               ; /* CCn_FLG_MASK, offset: 0x804 */
		__IO uint32_t CCn_INTEN                  ; /* CCn_INTEN, offset: 0x808 */
		__IO uint32_t CCn_FLG_STAT               ; /* CCn_FLG_STAT, offset: 0x80C */
		__IO uint32_t CCn_CTRL                   ; /* CCn_CTRL, offset: 0x810 */
		   	 uint8_t  RESERVED_18[12];
	} INTR[3];
		 uint8_t  RESERVED_20[672];
	__IO uint32_t SEMAn_STATUS[16]; /* Semaphore Status Register, offset: 0xb00 */
	   	 uint8_t  RESERVED_21[128];
	__IO uint32_t SEMA_GLOBAL_STATUS            ; /* Semaphore Global Status Register, offset: 0xBC0 */
	   	 uint8_t  RESERVED_22[12];
	__IO uint32_t SEMA_CTRL                     ; /* Semaphore Control Register, offset: 0xBD0 */
	__IO uint32_t SEMA_ERROR_STATUS             ; /* Semaphore Error Status Register, offset: 0xBD4 */
	__IO uint32_t SEMA_SW_RESET                 ; /* Semaphore Software Reset Register, offset: 0xBD8 */
	   	 uint8_t  RESERVED_23[4];
	__IO uint32_t SEMA_RELEASE                  ; /* Semaphore Release Register, offset: 0xBE0 */
	   	 uint8_t  RESERVED_24[28];
	__IO uint32_t SEMA_RSRC[256] ; /* Semaphore Resource Register, offset: 0xc00 */
} MB_Type, *MB_MemMapPtr;


/* MB - Peripheral instance base addresses */
/** Peripheral MB base address */
#define MB_BASE                                  (0x40058000u)
/** Peripheral MB base pointer */
#define MB                                       ((MB_Type *)MB_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the MB module. */
//#define MB_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the MB module. */
//#define MB_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the MB peripheral type */
//#define MB_IRQS                                  {MB0_IRQn}


/* ----------------------------------------------------------------------------
   -- MB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MB_Register_Masks MB Register Masks
 * @{
 */

/* CCn_SEMA Bit Fields */
#define MB_CCn_SEMA_LOCK_MASK          0x80000000u
#define MB_CCn_SEMA_LOCK_SHIFT         31u
#define MB_CCn_SEMA_LOCK_WIDTH         1u
#define MB_CCn_SEMA_LOCK(x)            (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_SHIFT))&MB_CCn_SEMA_LOCK_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_ID_MASK 0xF0u
#define MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT 4u
#define MB_CCn_SEMA_LOCK_MASTER_ID_WIDTH 4u
#define MB_CCn_SEMA_LOCK_MASTER_ID(x)  (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_ID_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_SEC_MASK 0x2u
#define MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT 1u
#define MB_CCn_SEMA_LOCK_MASTER_SEC_WIDTH 1u
#define MB_CCn_SEMA_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SEC_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK 0x1u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT 0u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_WIDTH 1u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK)
/* CC0_SEMA Reg Mask */
#define MB_CCn_SEMA_MASK               0x800000F3u

/* CCn_SEMA_UNLK Bit Fields */
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2_MASK 0x4u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2_SHIFT 2u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2_WIDTH 1u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2_SHIFT))&MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN2_MASK)
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1_MASK 0x2u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1_SHIFT 1u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1_WIDTH 1u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1_SHIFT))&MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN1_MASK)
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0_MASK 0x1u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0_SHIFT 0u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0_WIDTH 1u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0_SHIFT))&MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN0_MASK)
/* CC0_SEMA_UNLK Reg Mask */
#define MB_CCn_SEMA_UNLK_MASK          0x00000007u

/* CCn_REQUEST Bit Fields */
#define MB_CCn_REQUEST_REQ2_MASK       0x4u
#define MB_CCn_REQUEST_REQ2_SHIFT      2u
#define MB_CCn_REQUEST_REQ2_WIDTH      1u
#define MB_CCn_REQUEST_REQ2(x)         (((uint32_t)(((uint32_t)(x))<<MB_CCn_REQUEST_REQ2_SHIFT))&MB_CCn_REQUEST_REQ2_MASK)
#define MB_CCn_REQUEST_REQ1_MASK       0x2u
#define MB_CCn_REQUEST_REQ1_SHIFT      1u
#define MB_CCn_REQUEST_REQ1_WIDTH      1u
#define MB_CCn_REQUEST_REQ1(x)         (((uint32_t)(((uint32_t)(x))<<MB_CCn_REQUEST_REQ1_SHIFT))&MB_CCn_REQUEST_REQ1_MASK)
#define MB_CCn_REQUEST_REQ0_MASK       0x1u
#define MB_CCn_REQUEST_REQ0_SHIFT      0u
#define MB_CCn_REQUEST_REQ0_WIDTH      1u
#define MB_CCn_REQUEST_REQ0(x)         (((uint32_t)(((uint32_t)(x))<<MB_CCn_REQUEST_REQ0_SHIFT))&MB_CCn_REQUEST_REQ0_MASK)
/* CC0_REQUEST Reg Mask */
#define MB_CCn_REQUEST_MASK            0x00000007u

/* CCn_DONE Bit Fields */
#define MB_CCn_DONE_DONE2_MASK         0x4u
#define MB_CCn_DONE_DONE2_SHIFT        2u
#define MB_CCn_DONE_DONE2_WIDTH        1u
#define MB_CCn_DONE_DONE2(x)           (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_DONE2_SHIFT))&MB_CCn_DONE_DONE2_MASK)
#define MB_CCn_DONE_DONE1_MASK         0x2u
#define MB_CCn_DONE_DONE1_SHIFT        1u
#define MB_CCn_DONE_DONE1_WIDTH        1u
#define MB_CCn_DONE_DONE1(x)           (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_DONE1_SHIFT))&MB_CCn_DONE_DONE1_MASK)
#define MB_CCn_DONE_DONE0_MASK         0x1u
#define MB_CCn_DONE_DONE0_SHIFT        0u
#define MB_CCn_DONE_DONE0_WIDTH        1u
#define MB_CCn_DONE_DONE0(x)           (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_DONE0_SHIFT))&MB_CCn_DONE_DONE0_MASK)
/* CC0_DONE Reg Mask */
#define MB_CCn_DONE_MASK               0x00000007u

/* CCn_DONE_MASK Bit Fields */
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK 0xF0000u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT 16u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_WIDTH 4u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT))&MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)
#define MB_CCn_DONE_MASK_DONE_MASK2_MASK 0x4u
#define MB_CCn_DONE_MASK_DONE_MASK2_SHIFT 2u
#define MB_CCn_DONE_MASK_DONE_MASK2_WIDTH 1u
#define MB_CCn_DONE_MASK_DONE_MASK2(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASK2_SHIFT))&MB_CCn_DONE_MASK_DONE_MASK2_MASK)
#define MB_CCn_DONE_MASK_DONE_MASK1_MASK 0x2u
#define MB_CCn_DONE_MASK_DONE_MASK1_SHIFT 1u
#define MB_CCn_DONE_MASK_DONE_MASK1_WIDTH 1u
#define MB_CCn_DONE_MASK_DONE_MASK1(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASK1_SHIFT))&MB_CCn_DONE_MASK_DONE_MASK1_MASK)
#define MB_CCn_DONE_MASK_DONE_MASK0_MASK 0x1u
#define MB_CCn_DONE_MASK_DONE_MASK0_SHIFT 0u
#define MB_CCn_DONE_MASK_DONE_MASK0_WIDTH 1u
#define MB_CCn_DONE_MASK_DONE_MASK0(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASK0_SHIFT))&MB_CCn_DONE_MASK_DONE_MASK0_MASK)
/* CC0_DONE_MASK Reg Mask */
#define MB_CCn_DONE_MASK_MASK          0x000F0007u

/* CCn_DATA0 Bit Fields */
#define MB_CCn_DATA0_DATA0_MASK        0xFFFFFFFFu
#define MB_CCn_DATA0_DATA0_SHIFT       0u
#define MB_CCn_DATA0_DATA0_WIDTH       32u
#define MB_CCn_DATA0_DATA0(x)          (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA0_DATA0_SHIFT))&MB_CCn_DATA0_DATA0_MASK)
/* CC0_DATA0 Reg Mask */
#define MB_CCn_DATA0_MASK              0xFFFFFFFFu

/* CCn_DATA1 Bit Fields */
#define MB_CCn_DATA1_DATA1_MASK        0xFFFFFFFFu
#define MB_CCn_DATA1_DATA1_SHIFT       0u
#define MB_CCn_DATA1_DATA1_WIDTH       32u
#define MB_CCn_DATA1_DATA1(x)          (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA1_DATA1_SHIFT))&MB_CCn_DATA1_DATA1_MASK)
/* CC0_DATA1 Reg Mask */
#define MB_CCn_DATA1_MASK              0xFFFFFFFFu

/* CCn_STAT Bit Fields */
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK 0x80000000u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT 31u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK 0xF0u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT 4u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_WIDTH 4u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK 0x2u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK 0x1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT 0u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK)
/* CC0_STAT Reg Mask */
#define MB_CCn_STAT_MASK               0x800000F3u

/* CCn_CLR Bit Fields */
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK 0xFFFFFFFFu
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT 0u
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_WIDTH 32u
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT))&MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK)
/* CC0_CLR Reg Mask */
#define MB_CCn_CLR_MASK                0xFFFFFFFFu

/* INTn_FLG Bit Fields */
#define MB_INTn_FLG_DONE_FLAG_MASK     0xFF0000u
#define MB_INTn_FLG_DONE_FLAG_SHIFT    16u
#define MB_INTn_FLG_DONE_FLAG_WIDTH    8u
#define MB_INTn_FLG_DONE_FLAG(x)       (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_DONE_FLAG_SHIFT))&MB_INTn_FLG_DONE_FLAG_MASK)
#define MB_INTn_FLG_REQ_FLAG_MASK      0xFFu
#define MB_INTn_FLG_REQ_FLAG_SHIFT     0u
#define MB_INTn_FLG_REQ_FLAG_WIDTH     8u
#define MB_INTn_FLG_REQ_FLAG(x)        (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_REQ_FLAG_SHIFT))&MB_INTn_FLG_REQ_FLAG_MASK)
/* INT0_FLG Reg Mask */
#define MB_INTn_FLG_MASK               0x00FF00FFu

/* INTn_FLG_MASK Bit Fields */
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK 0xFF0000u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT 16u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_WIDTH 8u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK)
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK 0xFFu
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT 0u
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_WIDTH 8u
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK)
/* INT0_FLG_MASK Reg Mask */
#define MB_INTn_FLG_MASK_MASK          0x00FF00FFu

/* INTn_INTEN Bit Fields */
#define MB_INTn_INTEN_DONE_INT_EN_MASK 0xFF0000u
#define MB_INTn_INTEN_DONE_INT_EN_SHIFT 16u
#define MB_INTn_INTEN_DONE_INT_EN_WIDTH 8u
#define MB_INTn_INTEN_DONE_INT_EN(x)   (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_DONE_INT_EN_SHIFT))&MB_INTn_INTEN_DONE_INT_EN_MASK)
#define MB_INTn_INTEN_REQ_INT_EN_MASK  0xFFu
#define MB_INTn_INTEN_REQ_INT_EN_SHIFT 0u
#define MB_INTn_INTEN_REQ_INT_EN_WIDTH 8u
#define MB_INTn_INTEN_REQ_INT_EN(x)    (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_REQ_INT_EN_SHIFT))&MB_INTn_INTEN_REQ_INT_EN_MASK)
/* INT0_INTEN Reg Mask */
#define MB_INTn_INTEN_MASK             0x00FF00FFu

/* INTn_FLG_STAT Bit Fields */
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK 0xFF0000u
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT 16u
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_WIDTH 8u
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK)
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK 0xFFu
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT 0u
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_WIDTH 8u
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK)
/* INT0_FLG_STAT Reg Mask */
#define MB_INTn_FLG_STAT_MASK          0x00FF00FFu

/* INTn_CTRL Bit Fields */
#define MB_INTn_CTRL_INTEN_LOCK_MASK   0x4u
#define MB_INTn_CTRL_INTEN_LOCK_SHIFT  2u
#define MB_INTn_CTRL_INTEN_LOCK_WIDTH  1u
#define MB_INTn_CTRL_INTEN_LOCK(x)     (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_INTEN_LOCK_SHIFT))&MB_INTn_CTRL_INTEN_LOCK_MASK)
#define MB_INTn_CTRL_FLG_MASK_LOCK_MASK 0x2u
#define MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT 1u
#define MB_INTn_CTRL_FLG_MASK_LOCK_WIDTH 1u
#define MB_INTn_CTRL_FLG_MASK_LOCK(x)  (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT))&MB_INTn_CTRL_FLG_MASK_LOCK_MASK)
#define MB_INTn_CTRL_FLG_LOCK_MASK     0x1u
#define MB_INTn_CTRL_FLG_LOCK_SHIFT    0u
#define MB_INTn_CTRL_FLG_LOCK_WIDTH    1u
#define MB_INTn_CTRL_FLG_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_LOCK_SHIFT))&MB_INTn_CTRL_FLG_LOCK_MASK)
/* INT0_CTRL Reg Mask */
#define MB_INTn_CTRL_MASK              0x00000007u

/* SEMAn_STATUS Bit Fields */
#define MB_SEMAn_STATUS_SEMA_RSRC_ID_MASK 0xFF0u
#define MB_SEMAn_STATUS_SEMA_RSRC_ID_SHIFT 4u
#define MB_SEMAn_STATUS_SEMA_RSRC_ID_WIDTH 8u
#define MB_SEMAn_STATUS_SEMA_RSRC_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMAn_STATUS_SEMA_RSRC_ID_SHIFT))&MB_SEMAn_STATUS_SEMA_RSRC_ID_MASK)
#define MB_SEMAn_STATUS_SEMA_MID_MASK  0xEu
#define MB_SEMAn_STATUS_SEMA_MID_SHIFT 1u
#define MB_SEMAn_STATUS_SEMA_MID_WIDTH 3u
#define MB_SEMAn_STATUS_SEMA_MID(x)    (((uint32_t)(((uint32_t)(x))<<MB_SEMAn_STATUS_SEMA_MID_SHIFT))&MB_SEMAn_STATUS_SEMA_MID_MASK)
#define MB_SEMAn_STATUS_SEMA_FLG_MASK  0x1u
#define MB_SEMAn_STATUS_SEMA_FLG_SHIFT 0u
#define MB_SEMAn_STATUS_SEMA_FLG_WIDTH 1u
#define MB_SEMAn_STATUS_SEMA_FLG(x)    (((uint32_t)(((uint32_t)(x))<<MB_SEMAn_STATUS_SEMA_FLG_SHIFT))&MB_SEMAn_STATUS_SEMA_FLG_MASK)
/* SEMA0_STATUS Reg Mask */
#define MB_SEMAn_STATUS_MASK           0x00000FFFu

/* SEMA_GLOBAL_STATUS Bit Fields */
#define MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS_MASK 0x8000u
#define MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS_SHIFT 15u
#define MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA15_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS_MASK 0x4000u
#define MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS_SHIFT 14u
#define MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA14_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS_MASK 0x2000u
#define MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS_SHIFT 13u
#define MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA13_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS_MASK 0x1000u
#define MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS_SHIFT 12u
#define MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA12_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS_MASK 0x800u
#define MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS_SHIFT 11u
#define MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA11_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS_MASK 0x400u
#define MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS_SHIFT 10u
#define MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA10_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS_MASK 0x200u
#define MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS_SHIFT 9u
#define MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA9_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS_MASK 0x100u
#define MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS_SHIFT 8u
#define MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA8_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS_MASK 0x80u
#define MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS_SHIFT 7u
#define MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA7_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS_MASK 0x40u
#define MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS_SHIFT 6u
#define MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA6_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS_MASK 0x20u
#define MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS_SHIFT 5u
#define MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA5_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS_MASK 0x10u
#define MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS_SHIFT 4u
#define MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA4_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS_MASK 0x8u
#define MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS_SHIFT 3u
#define MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA3_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS_MASK 0x4u
#define MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS_SHIFT 2u
#define MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA2_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS_MASK 0x2u
#define MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS_SHIFT 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA1_STATUS_MASK)
#define MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS_MASK 0x1u
#define MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS_SHIFT 0u
#define MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS_WIDTH 1u
#define MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS_SHIFT))&MB_SEMA_GLOBAL_STATUS_SEMA0_STATUS_MASK)
/* SEMA_GLOBAL_STATUS Reg Mask */
#define MB_SEMA_GLOBAL_STATUS_MASK     0x0000FFFFu

/* SEMA_CTRL Bit Fields */
#define MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL_MASK 0x1u
#define MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL_SHIFT 0u
#define MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL_WIDTH 1u
#define MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL_SHIFT))&MB_SEMA_CTRL_SEMA_LOCK_CHECK_CTRL_MASK)
/* SEMA_CTRL Reg Mask */
#define MB_SEMA_CTRL_MASK              0x00000001u

/* SEMA_ERROR_STATUS Bit Fields */
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_MASK 0x1FE0u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_SHIFT 5u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_WIDTH 8u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_SHIFT))&MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_MASK)
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_MASK 0x1Cu
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_SHIFT 2u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_WIDTH 3u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_MID(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_SHIFT))&MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_MASK)
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY_MASK 0x2u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY_SHIFT 1u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY_WIDTH 1u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY_SHIFT))&MB_SEMA_ERROR_STATUS_SEMA_ERR_KEY_MASK)
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_ST_MASK 0x1u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_ST_SHIFT 0u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_ST_WIDTH 1u
#define MB_SEMA_ERROR_STATUS_SEMA_ERR_ST(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_ERROR_STATUS_SEMA_ERR_ST_SHIFT))&MB_SEMA_ERROR_STATUS_SEMA_ERR_ST_MASK)
/* SEMA_ERROR_STATUS Reg Mask */
#define MB_SEMA_ERROR_STATUS_MASK      0x00001FFFu

/* SEMA_SW_RESET Bit Fields */
#define MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL_MASK 0xFFFFFFFFu
#define MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL_SHIFT 0u
#define MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL_WIDTH 32u
#define MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL_SHIFT))&MB_SEMA_SW_RESET_SEMA_SW_RESET_CTRL_MASK)
/* SEMA_SW_RESET Reg Mask */
#define MB_SEMA_SW_RESET_MASK          0xFFFFFFFFu

/* SEMA_RELEASE Bit Fields */
#define MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL_MASK 0xFFFFFFFFu
#define MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL_SHIFT 0u
#define MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL_WIDTH 32u
#define MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL(x) (((uint32_t)(((uint32_t)(x))<<MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL_SHIFT))&MB_SEMA_RELEASE_SEMA_RELEASE_CTRLL_MASK)
/* SEMA_RELEASE Reg Mask */
#define MB_SEMA_RELEASE_MASK           0xFFFFFFFFu

/* SEMA_RSRC Bit Fields */
#define MB_SEMA_RSRC_SEMA_RSRC_ID_MASK 0xFF0u
#define MB_SEMA_RSRC_SEMA_RSRC_ID_SHIFT 4u
#define MB_SEMA_RSRC_SEMA_RSRC_ID_WIDTH 8u
#define MB_SEMA_RSRC_SEMA_RSRC_ID(x)   (((uint32_t)(((uint32_t)(x))<<MB_SEMA_RSRC_SEMA_RSRC_ID_SHIFT))&MB_SEMA_RSRC_SEMA_RSRC_ID_MASK)
#define MB_SEMA_RSRC_SEMA_MID_MASK     0xEu
#define MB_SEMA_RSRC_SEMA_MID_SHIFT    1u
#define MB_SEMA_RSRC_SEMA_MID_WIDTH    3u
#define MB_SEMA_RSRC_SEMA_MID(x)       (((uint32_t)(((uint32_t)(x))<<MB_SEMA_RSRC_SEMA_MID_SHIFT))&MB_SEMA_RSRC_SEMA_MID_MASK)
#define MB_SEMA_RSRC_SEMA_FLG_MASK     0x1u
#define MB_SEMA_RSRC_SEMA_FLG_SHIFT    0u
#define MB_SEMA_RSRC_SEMA_FLG_WIDTH    1u
#define MB_SEMA_RSRC_SEMA_FLG(x)       (((uint32_t)(((uint32_t)(x))<<MB_SEMA_RSRC_SEMA_FLG_SHIFT))&MB_SEMA_RSRC_SEMA_FLG_MASK)
/* SEMA_RSRC0 Reg Mask */
#define MB_SEMA_RSRC_MASK              0x00000FFFu

/* SEMA Keys */
#define MB_SEMA_KEY_UNLOCK             	0xFCA05F00u
#define MB_SEMA_KEY_RELEASE            	0xFC50A05Fu
#define MB_SEMA_KEY_CLEAR_ERROR        	0xA05FFC00u
#define MB_SEMA_KEY_SW_RESET           	0xA05F50FCu
#define MB_SEMA_KEY_RELEASE_ALL			0xFC500000u

/*!
 * @}
 */ /* end of group MB_Register_Masks */

/*!
 * @}
 */ /* end of group MB_Peripheral_Access_Layer */

#endif
