#ifndef _DEVICE_FEATURES_FC7240F2MDS2_PCC_COMMON_H_
#define _DEVICE_FEATURES_FC7240F2MDS2_PCC_COMMON_H_

/* PCC property MACRO, defines every peripheral clock system architecture */
#define PCC_CLK_NOT_APPLY               (0U)
#define PCC_CGC_AVAILABLE               (1U << 0U)
#define PCC_FUNCCLK_MUXDIVH_USED        (1U << 1U)
#define PCC_FUNCCLK_MUXDIVM_USED        (1U << 2U)
#define PCC_FUNCCLK_MUXDIVL_USED        (1U << 3U)
#define PCC_FUNCCLK_MUXDIVHPIN_USED     (1U << 4U)
#define PCC_MOUDULE_DIV_USED            (1U << 5U)
#define PCC_CLK_DOMAIN_CORE             (1U << 6U)
#define PCC_CLK_DOMAIN_BUS              (1U << 7U)
#define PCC_CLK_DOMAIN_SLOW             (1U << 8U)
#define PCC_DWP_SWR_AVAILABLE           (1U << 9U)

#define PCC_PROPERTY_MUXDIV_MASK           (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED)
#define PCC_PROPERTY_MUXDIV_ALL_MASK       (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED | PCC_FUNCCLK_MUXDIVHPIN_USED)

/************ PCC Clock Limits **************/
#define PCC_FUNCTION_CLOCK_MAX   160000000U
#define PCC_DWP_SUPPORT          (0u)
#define PCC_DWPLK_SUPPORT        (0u)
#define PCC_PLLX_CLK1_SUPPORT    (0u)
#define PCC_PLLX_CLK2_SUPPORT    (0u)
#define PCC_PLL1_CLK_SUPPORT     (1u)

/************ PCC Peripheral Features **************/
#define PCC_CLOCK_MAP_INFO \
{ \
    {0x20, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* DMA0 */    \
    {0x28, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* DMAMUX0 */ \
    {0x4C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* ROMC */    \
    {0x60, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* ERM0 */    \
    {0x64, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* EIM0 */    \
    {0x68, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* INTM0 */   \
    {0x6C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* ISM0 */    \
    {0x88, PCC_CLK_DOMAIN_SLOW },                     /* WDOG0 */   \
    {0x98, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL0 */ \
    {0x9C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL1 */ \
    {0xA0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL2 */ \
    {0xA4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL3 */ \
    {0xA8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* CRC0 */    \
    {0xB0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* TSTMP0 */  \
    {0xB4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* TSTMP1 */  \
    {0xB8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED }, /* FCPIT0 */  \
    {0xBC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED | PCC_MOUDULE_DIV_USED },  /* AONTIMER0 */  \
    {0xC0, PCC_CLK_DOMAIN_SLOW },                     /* RTC */     \
    {0xC4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* CMU0 */    \
    {0xC8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* CMU1 */    \
    {0xCC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* CMU2 */    \
    {0xD0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* CMU3 */    \
    {0xD4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* CMU4 */    \
    {0xDC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS  },  /* PTIMER0 */ \
    {0xE0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* PTIMER1 */ \
    {0xEC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED },  /* ADC0 */  \
    {0xF0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED },  /* ADC1 */  \
    {0xFC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* WKU0 */    \
    {0x100, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW },/* CMP0 */    \
    {0x104, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW },/* CMP1 */    \
    {0x10C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED },  /* TMU0 */  \
    {0x160, PCC_CLK_DOMAIN_BUS },                     /* MB0 */     \
    {0x170, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU0 */  \
    {0x174, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU1 */  \
    {0x178, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU2 */  \
    {0x17C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU3 */  \
    {0x188, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCSPI0 */  \
    {0x18C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCSPI1 */  \
    {0x190, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCSPI2 */  \
    {0x198, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCIIC0 */  \
    {0x1A0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART0 */ \
    {0x1A4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART1 */ \
    {0x1A8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART2 */ \
    {0x1AC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART3 */ \
    {0x1C0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* LU0 */    \
    {0x1E0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS },  /* FREQM */  \
    {0x1FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE },    /* STCU */   \
    {0x200, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED },   /* FLEXCAN0 */  \
    {0x210, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED },   /* FLEXCAN1 */  \
    {0x34C, PCC_CLK_DOMAIN_SLOW },                     /* WDOG1 */  \
    {0x36C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL4 */\
    {0x370, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW }, /* TRGSEL5 */\
	{0x37C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCSPI3 */  \
    {0x3FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU4 */  \
    {0x400, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU5 */  \
    {0x404, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU6 */  \
    {0x408, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED },  /* FTU7 */  \
	{0x41C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCIIC1 */  \
    {0x420, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART4 */ \
    {0x424, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART5 */ \
    {0x428, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART6 */ \
    {0x42C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED },  /* FCUART7 */ \
    {0x480, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED }, /* FLEXCAN2 */ \
    {0x490, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED }, /* FLEXCAN3 */ \
};

/** @brief PCC clock list */
typedef enum
{
    PCC_CLK_DMA0 = 0U,
    PCC_CLK_DMAMUX0,
    PCC_CLK_ROMC,
    PCC_CLK_ERM0,
    PCC_CLK_EIM0,
    PCC_CLK_INTM0,
    PCC_CLK_ISM0,
    PCC_CLK_WDOG0,
    PCC_CLK_TRGSEL0,
    PCC_CLK_TRGSEL1,
    PCC_CLK_TRGSEL2,
    PCC_CLK_TRGSEL3,
    PCC_CLK_CRC0,
    PCC_CLK_TSTMP0,
    PCC_CLK_TSTMP1,
    PCC_CLK_FCPIT0,
    PCC_CLK_AONTIMER0,
    PCC_CLK_RTC,
    PCC_CLK_CMU0,
    PCC_CLK_CMU1,
    PCC_CLK_CMU2,
    PCC_CLK_CMU3,
    PCC_CLK_CMU4,
    PCC_CLK_PTIMER0,
    PCC_CLK_PTIMER1,
    PCC_CLK_ADC0,
    PCC_CLK_ADC1,
    PCC_CLK_WKU0,
    PCC_CLK_CMP0,
    PCC_CLK_CMP1,
    PCC_CLK_TMU0,
    PCC_CLK_MB0,
    PCC_CLK_FTU0,
    PCC_CLK_FTU1,
    PCC_CLK_FTU2,
    PCC_CLK_FTU3,
    PCC_CLK_FCSPI0,
    PCC_CLK_FCSPI1,
    PCC_CLK_FCSPI2,
    PCC_CLK_FCIIC0,
    PCC_CLK_FCUART0,
    PCC_CLK_FCUART1,
    PCC_CLK_FCUART2,
    PCC_CLK_FCUART3,
    PCC_CLK_LU0,
    PCC_CLK_FREQM,
    PCC_CLK_STCU,
    PCC_CLK_FLEXCAN0,
    PCC_CLK_FLEXCAN1,
    PCC_CLK_WDOG1,
    PCC_CLK_TRGSEL4,
    PCC_CLK_TRGSEL5,
	PCC_CLK_FCSPI3,
	PCC_CLK_FTU4,
	PCC_CLK_FTU5,
    PCC_CLK_FTU6,
    PCC_CLK_FTU7,
    PCC_CLK_FCIIC1,
    PCC_CLK_FCUART4,
    PCC_CLK_FCUART5,
    PCC_CLK_FCUART6,
    PCC_CLK_FCUART7,
    PCC_CLK_FLEXCAN2,
    PCC_CLK_FLEXCAN3,
    PCC_END_OF_CLOCKS
} PCC_ClkSrcType;


#endif /* _DEVICE_FEATURES_FC7240F2MDS2_PCC_COMMON_H_ */
