#ifndef _MODULE_EFTU_TOM_gmbhdijq14_REGS_H_EFTU_TOM_H_
#define _MODULE_EFTU_TOM_gmbhdijq14_REGS_H_EFTU_TOM_H_

/* ----------------------------------------------------------------------------
   -- EFTU_TOM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EFTU_TOM_Peripheral_Access_Layer EFTU_TOM Peripheral Access Layer
 * @{
 */

/** EFTU_TOM - Size of Registers Arrays */

/** EFTU_TOM - Register Layout Typedef */

typedef struct {

       uint8_t  RESERVED_0[4];
       struct
	   {
    	   __IO uint32_t CH_CTRL                      ; /* Channel [x] Control Register, offset: 0x4 */
    	   __IO uint32_t CH_SR0                       ; /* Channel [x] CCU0 Compare Shadow Register, offset: 0x8 */
    	   __IO uint32_t CH_SR1                       ; /* Channel [x] CCU1 Compare Shadow Register, offset: 0xc */
		   __IO uint32_t CH_CM0                       ; /* Channel [x] CCU0 Compare Register, offset: 0x10 */
		   __IO uint32_t CH_CM1                       ; /* Channel [x] CCU1 Compare Register, offset: 0x14 */
		   __IO uint32_t CH_CN0                       ; /* Channel [x] CCU0 Counter Register, offset: 0x18 */
		   __IO uint32_t CH_STAT                      ; /* Channel [x] Status Register, offset: 0x1c */
		   __IO uint32_t CH_IRQ_ST                    ; /* Channel [x] Interrupt Notification Register, offset: 0x20 */
		   __IO uint32_t CH_IRQ_EN                    ; /* Channel [x] Interrupt Enable Register, offset: 0x24 */
			    uint8_t  RESERVED_1[12];
		   __IO uint32_t CH_CTRL_SR                   ; /* Channel [x] Control Shadow Register, offset: 0x34 */
			    uint8_t  RESERVED_2[76];
	   } Channel[8];
       uint8_t  RESERVED_16[60];
  __IO uint32_t TGC_GLB_CTRL                  ; /* TGC Global Control Register, offset: 0x440 */
  __IO uint32_t TGC_ENDIS_CTRL                ; /* TGC Enable/Disable Control Register, offset: 0x444 */
  __IO uint32_t TGC_ENDIS_STAT                ; /* TGC Enable/Disable Status Register, offset: 0x448 */
  __IO uint32_t TGC_ACT_TB                    ; /* TGC Action Time Base Register, offset: 0x44C */
  __IO uint32_t TGC_OUTEN_CTRL                ; /* TGC Output Enable Control Register, offset: 0x450 */
  __IO uint32_t TGC_OUTEN_STAT                ; /* TGC Output Enable Status Register, offset: 0x454 */
  __IO uint32_t TGC_FUPD_CTRL                 ; /* TGC Force Update Control Register, offset: 0x458 */
  __IO uint32_t TGC_INT_TRIG                  ; /* TGC Internal Trigger Control Register, offset: 0x45C */
  __IO uint32_t TGC_SPEC_LOCK                 ; /* TGC Special Lock Register, offset: 0x460 */

} EFTU_TOM_Type, *EFTU_TOM_MemMapPtr;


/* EFTU_TOM - Peripheral instance base addresses */
/** Peripheral EFTU_TOM0 base address */
#define EFTU_TOM0_BASE                           (0x1000u)
/** Peripheral EFTU_TOM0 base pointer */
#define EFTU_TOM0                                ((EFTU_TOM_Type *)EFTU_TOM0_BASE)
/** Peripheral EFTU_TOM1 base address */
#define EFTU_TOM1_BASE                           (0x1800u)
/** Peripheral EFTU_TOM1 base pointer */
#define EFTU_TOM1                                ((EFTU_TOM_Type *)EFTU_TOM1_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the EFTU_TOM module. */
//#define EFTU_TOM_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the EFTU_TOM module. */
//#define EFTU_TOM_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the EFTU_TOM peripheral type */
//#define EFTU_TOM_IRQS                            {EFTU_TOM0_IRQn, EFTU_TOM1_IRQn}


/* ----------------------------------------------------------------------------
   -- EFTU_TOM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EFTU_TOM_Register_Masks EFTU_TOM Register Masks
 * @{
 */

/* TGC_GLB_CTRL Bit Fields */
#define EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_MASK 0x1u
#define EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_SHIFT 0u
#define EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_WIDTH 1u
#define EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_MASK 0x2u
#define EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_SHIFT 1u
#define EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_WIDTH 1u
#define EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_RST_CH_MASK 0xFF00u
#define EFTU_TOM_TGC_GLB_CTRL_RST_CH_SHIFT 8u
#define EFTU_TOM_TGC_GLB_CTRL_RST_CH_WIDTH 8u
#define EFTU_TOM_TGC_GLB_CTRL_RST_CH(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_RST_CH_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_RST_CH_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_MASK 0x30000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_SHIFT 16u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1_MASK 0xC0000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1_SHIFT 18u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL1_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2_MASK 0x300000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2_SHIFT 20u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL2_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3_MASK 0xC00000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3_SHIFT 22u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL3_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4_MASK 0x3000000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4_SHIFT 24u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL4_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5_MASK 0xC000000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5_SHIFT 26u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL5_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6_MASK 0x30000000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6_SHIFT 28u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL6_MASK)
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7_MASK 0xC0000000u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7_SHIFT 30u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7_WIDTH 2u
#define EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7_SHIFT))&EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL7_MASK)
/* TGC_GLB_CTRL Reg Mask */
#define EFTU_TOM_TGC_GLB_CTRL_MASK     0xFFFFFF03u

/* TGC_ENDIS_CTRL Bit Fields */
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_MASK 0x3u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT 0u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1_MASK 0xCu
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL1_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2_MASK 0x30u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT 4u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL2_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3_MASK 0xC0u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT 6u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL3_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4_MASK 0x300u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT 8u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL4_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5_MASK 0xC00u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT 10u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL5_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6_MASK 0x3000u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT 12u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL6_MASK)
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7_MASK 0xC000u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT 14u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT))&EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL7_MASK)
/* TGC_ENDIS_CTRL Reg Mask */
#define EFTU_TOM_TGC_ENDIS_CTRL_MASK   0x0000FFFFu

/* TGC_ENDIS_STAT Bit Fields */
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_MASK 0x3u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_SHIFT 0u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1_MASK 0xCu
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1_SHIFT 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT1_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2_MASK 0x30u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2_SHIFT 4u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT2_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3_MASK 0xC0u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3_SHIFT 6u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT3_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4_MASK 0x300u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4_SHIFT 8u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT4_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5_MASK 0xC00u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5_SHIFT 10u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT5_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6_MASK 0x3000u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6_SHIFT 12u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT6_MASK)
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7_MASK 0xC000u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7_SHIFT 14u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7_WIDTH 2u
#define EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7_SHIFT))&EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT7_MASK)
/* TGC_ENDIS_STAT Reg Mask */
#define EFTU_TOM_TGC_ENDIS_STAT_MASK   0x0000FFFFu

/* TGC_ACT_TB Bit Fields */
#define EFTU_TOM_TGC_ACT_TB_ACT_TB_MASK 0xFFFFFFu
#define EFTU_TOM_TGC_ACT_TB_ACT_TB_SHIFT 0u
#define EFTU_TOM_TGC_ACT_TB_ACT_TB_WIDTH 24u
#define EFTU_TOM_TGC_ACT_TB_ACT_TB(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ACT_TB_ACT_TB_SHIFT))&EFTU_TOM_TGC_ACT_TB_ACT_TB_MASK)
#define EFTU_TOM_TGC_ACT_TB_TB_TRIG_MASK 0x1000000u
#define EFTU_TOM_TGC_ACT_TB_TB_TRIG_SHIFT 24u
#define EFTU_TOM_TGC_ACT_TB_TB_TRIG_WIDTH 1u
#define EFTU_TOM_TGC_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ACT_TB_TB_TRIG_SHIFT))&EFTU_TOM_TGC_ACT_TB_TB_TRIG_MASK)
#define EFTU_TOM_TGC_ACT_TB_TBU_SEL_MASK 0x6000000u
#define EFTU_TOM_TGC_ACT_TB_TBU_SEL_SHIFT 25u
#define EFTU_TOM_TGC_ACT_TB_TBU_SEL_WIDTH 2u
#define EFTU_TOM_TGC_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_ACT_TB_TBU_SEL_SHIFT))&EFTU_TOM_TGC_ACT_TB_TBU_SEL_MASK)
/* TGC_ACT_TB Reg Mask */
#define EFTU_TOM_TGC_ACT_TB_MASK       0x07FFFFFFu

/* TGC_OUTEN_CTRL Bit Fields */
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_MASK 0x3u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT 0u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1_MASK 0xCu
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL1_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2_MASK 0x30u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT 4u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL2_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3_MASK 0xC0u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT 6u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL3_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4_MASK 0x300u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT 8u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL4_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5_MASK 0xC00u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT 10u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL5_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6_MASK 0x3000u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT 12u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL6_MASK)
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7_MASK 0xC000u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT 14u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT))&EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL7_MASK)
/* TGC_OUTEN_CTRL Reg Mask */
#define EFTU_TOM_TGC_OUTEN_CTRL_MASK   0x0000FFFFu

/* TGC_OUTEN_STAT Bit Fields */
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_MASK 0x3u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_SHIFT 0u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1_MASK 0xCu
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1_SHIFT 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT1_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2_MASK 0x30u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2_SHIFT 4u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT2_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3_MASK 0xC0u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3_SHIFT 6u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT3_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4_MASK 0x300u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4_SHIFT 8u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT4_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5_MASK 0xC00u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5_SHIFT 10u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT5_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6_MASK 0x3000u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6_SHIFT 12u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT6_MASK)
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7_MASK 0xC000u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7_SHIFT 14u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7_WIDTH 2u
#define EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7_SHIFT))&EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT7_MASK)
/* TGC_OUTEN_STAT Reg Mask */
#define EFTU_TOM_TGC_OUTEN_STAT_MASK   0x0000FFFFu

/* TGC_FUPD_CTRL Bit Fields */
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_MASK 0x3u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_SHIFT 0u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1_MASK 0xCu
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1_SHIFT 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL1_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2_MASK 0x30u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2_SHIFT 4u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL2_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3_MASK 0xC0u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3_SHIFT 6u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL3_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4_MASK 0x300u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4_SHIFT 8u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL4_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5_MASK 0xC00u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5_SHIFT 10u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL5_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6_MASK 0x3000u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6_SHIFT 12u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL6_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7_MASK 0xC000u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7_SHIFT 14u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL7_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_MASK 0x30000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_SHIFT 16u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1_MASK 0xC0000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1_SHIFT 18u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH1_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2_MASK 0x300000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2_SHIFT 20u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH2_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3_MASK 0xC00000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3_SHIFT 22u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH3_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4_MASK 0x3000000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4_SHIFT 24u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH4_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5_MASK 0xC000000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5_SHIFT 26u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH5_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6_MASK 0x30000000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6_SHIFT 28u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH6_MASK)
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7_MASK 0xC0000000u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7_SHIFT 30u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7_WIDTH 2u
#define EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7_SHIFT))&EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH7_MASK)
/* TGC_FUPD_CTRL Reg Mask */
#define EFTU_TOM_TGC_FUPD_CTRL_MASK    0xFFFFFFFFu

/* TGC_INT_TRIG Bit Fields */
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_MASK 0x3u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_SHIFT 0u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG1_MASK 0xCu
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG1_SHIFT 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG1_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG1_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG1_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG2_MASK 0x30u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG2_SHIFT 4u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG2_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG2_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG2_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG3_MASK 0xC0u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG3_SHIFT 6u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG3_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG3_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG3_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG4_MASK 0x300u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG4_SHIFT 8u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG4_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG4_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG4_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG5_MASK 0xC00u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG5_SHIFT 10u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG5_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG5_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG5_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG6_MASK 0x3000u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG6_SHIFT 12u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG6_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG6_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG6_MASK)
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG7_MASK 0xC000u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG7_SHIFT 14u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG7_WIDTH 2u
#define EFTU_TOM_TGC_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_INT_TRIG_INT_TRIG7_SHIFT))&EFTU_TOM_TGC_INT_TRIG_INT_TRIG7_MASK)
/* TGC_INT_TRIG Reg Mask */
#define EFTU_TOM_TGC_INT_TRIG_MASK     0x0000FFFFu

/* TGC_SPEC_LOCK Bit Fields */
#define EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK_MASK 0xFFFFFFFFu
#define EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK_SHIFT 0u
#define EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK_WIDTH 32u
#define EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK_SHIFT))&EFTU_TOM_TGC_SPEC_LOCK_SPEC_LOCK_MASK)
/* TGC_SPEC_LOCK Reg Mask */
#define EFTU_TOM_TGC_SPEC_LOCK_MASK    0xFFFFFFFFu

/* CHn_CTRL Bit Fields */
#define EFTU_TOM_CHn_CTRL_MODE_MASK    0x7u
#define EFTU_TOM_CHn_CTRL_MODE_SHIFT   0u
#define EFTU_TOM_CHn_CTRL_MODE_WIDTH   3u
#define EFTU_TOM_CHn_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_MODE_SHIFT))&EFTU_TOM_CHn_CTRL_MODE_MASK)
#define EFTU_TOM_CHn_CTRL_TMCB_MASK    0x1F0u
#define EFTU_TOM_CHn_CTRL_TMCB_SHIFT   4u
#define EFTU_TOM_CHn_CTRL_TMCB_WIDTH   5u
#define EFTU_TOM_CHn_CTRL_TMCB(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TMCB_SHIFT))&EFTU_TOM_CHn_CTRL_TMCB_MASK)
#define EFTU_TOM_CHn_CTRL_EUPM_MASK    0x400u
#define EFTU_TOM_CHn_CTRL_EUPM_SHIFT   10u
#define EFTU_TOM_CHn_CTRL_EUPM_WIDTH   1u
#define EFTU_TOM_CHn_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_EUPM_SHIFT))&EFTU_TOM_CHn_CTRL_EUPM_MASK)
#define EFTU_TOM_CHn_CTRL_SL_MASK      0x800u
#define EFTU_TOM_CHn_CTRL_SL_SHIFT     11u
#define EFTU_TOM_CHn_CTRL_SL_WIDTH     1u
#define EFTU_TOM_CHn_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_SL_SHIFT))&EFTU_TOM_CHn_CTRL_SL_MASK)
#define EFTU_TOM_CHn_CTRL_CLK_SRC_MASK 0xF000u
#define EFTU_TOM_CHn_CTRL_CLK_SRC_SHIFT 12u
#define EFTU_TOM_CHn_CTRL_CLK_SRC_WIDTH 4u
#define EFTU_TOM_CHn_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_CLK_SRC_SHIFT))&EFTU_TOM_CHn_CTRL_CLK_SRC_MASK)
#define EFTU_TOM_CHn_CTRL_TRIG_PULSE_MASK 0x20000u
#define EFTU_TOM_CHn_CTRL_TRIG_PULSE_SHIFT 17u
#define EFTU_TOM_CHn_CTRL_TRIG_PULSE_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TRIG_PULSE_SHIFT))&EFTU_TOM_CHn_CTRL_TRIG_PULSE_MASK)
#define EFTU_TOM_CHn_CTRL_UDMODE_MASK  0xC0000u
#define EFTU_TOM_CHn_CTRL_UDMODE_SHIFT 18u
#define EFTU_TOM_CHn_CTRL_UDMODE_WIDTH 2u
#define EFTU_TOM_CHn_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_UDMODE_SHIFT))&EFTU_TOM_CHn_CTRL_UDMODE_MASK)
#define EFTU_TOM_CHn_CTRL_RST_CCU0_MASK 0x100000u
#define EFTU_TOM_CHn_CTRL_RST_CCU0_SHIFT 20u
#define EFTU_TOM_CHn_CTRL_RST_CCU0_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_RST_CCU0_SHIFT))&EFTU_TOM_CHn_CTRL_RST_CCU0_MASK)
#define EFTU_TOM_CHn_CTRL_OSM_TRIG_MASK 0x200000u
#define EFTU_TOM_CHn_CTRL_OSM_TRIG_SHIFT 21u
#define EFTU_TOM_CHn_CTRL_OSM_TRIG_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_OSM_TRIG_SHIFT))&EFTU_TOM_CHn_CTRL_OSM_TRIG_MASK)
#define EFTU_TOM_CHn_CTRL_TRIGOUT_MASK 0x1000000u
#define EFTU_TOM_CHn_CTRL_TRIGOUT_SHIFT 24u
#define EFTU_TOM_CHn_CTRL_TRIGOUT_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TRIGOUT_SHIFT))&EFTU_TOM_CHn_CTRL_TRIGOUT_MASK)
#define EFTU_TOM_CHn_CTRL_OSM_MASK     0x4000000u
#define EFTU_TOM_CHn_CTRL_OSM_SHIFT    26u
#define EFTU_TOM_CHn_CTRL_OSM_WIDTH    1u
#define EFTU_TOM_CHn_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_OSM_SHIFT))&EFTU_TOM_CHn_CTRL_OSM_MASK)
#define EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_MASK 0x8000000u
#define EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_SHIFT 27u
#define EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_SHIFT))&EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_MASK)
#define EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_MASK 0x10000000u
#define EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_SHIFT 28u
#define EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_SHIFT))&EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_MASK)
#define EFTU_TOM_CHn_CTRL_EXT_FUPD_MASK 0x20000000u
#define EFTU_TOM_CHn_CTRL_EXT_FUPD_SHIFT 29u
#define EFTU_TOM_CHn_CTRL_EXT_FUPD_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_EXT_FUPD_SHIFT))&EFTU_TOM_CHn_CTRL_EXT_FUPD_MASK)
#define EFTU_TOM_CHn_CTRL_TB12_SEL_MASK 0x40000000u
#define EFTU_TOM_CHn_CTRL_TB12_SEL_SHIFT 30u
#define EFTU_TOM_CHn_CTRL_TB12_SEL_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_TB12_SEL_SHIFT))&EFTU_TOM_CHn_CTRL_TB12_SEL_MASK)
/* CH0_CTRL Reg Mask */
#define EFTU_TOM_CHn_CTRL_MASK         0x7D3EFDF7u

/* CHn_CTRL_SR Bit Fields */
#define EFTU_TOM_CHn_CTRL_SR_SL_SR_MASK 0x800u
#define EFTU_TOM_CHn_CTRL_SR_SL_SR_SHIFT 11u
#define EFTU_TOM_CHn_CTRL_SR_SL_SR_WIDTH 1u
#define EFTU_TOM_CHn_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_SR_SL_SR_SHIFT))&EFTU_TOM_CHn_CTRL_SR_SL_SR_MASK)
#define EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_MASK 0xF000u
#define EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_SHIFT 12u
#define EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_WIDTH 4u
#define EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_SHIFT))&EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_MASK)
/* CH0_CTRL_SR Reg Mask */
#define EFTU_TOM_CHn_CTRL_SR_MASK      0x0000F800u

/* CHn_STAT Bit Fields */
#define EFTU_TOM_CHn_STAT_OL_MASK      0x1u
#define EFTU_TOM_CHn_STAT_OL_SHIFT     0u
#define EFTU_TOM_CHn_STAT_OL_WIDTH     1u
#define EFTU_TOM_CHn_STAT_OL(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_STAT_OL_SHIFT))&EFTU_TOM_CHn_STAT_OL_MASK)
#define EFTU_TOM_CHn_STAT_CCU_MATCH_MASK 0x18000000u
#define EFTU_TOM_CHn_STAT_CCU_MATCH_SHIFT 27u
#define EFTU_TOM_CHn_STAT_CCU_MATCH_WIDTH 2u
#define EFTU_TOM_CHn_STAT_CCU_MATCH(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_STAT_CCU_MATCH_SHIFT))&EFTU_TOM_CHn_STAT_CCU_MATCH_MASK)
#define EFTU_TOM_CHn_STAT_OSM_RTF_MASK 0x20000000u
#define EFTU_TOM_CHn_STAT_OSM_RTF_SHIFT 29u
#define EFTU_TOM_CHn_STAT_OSM_RTF_WIDTH 1u
#define EFTU_TOM_CHn_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_STAT_OSM_RTF_SHIFT))&EFTU_TOM_CHn_STAT_OSM_RTF_MASK)
/* CH0_STAT Reg Mask */
#define EFTU_TOM_CHn_STAT_MASK         0x38000001u

/* CHn_CN0 Bit Fields */
#define EFTU_TOM_CHn_CN0_CN0_MASK      0xFFFFFFu
#define EFTU_TOM_CHn_CN0_CN0_SHIFT     0u
#define EFTU_TOM_CHn_CN0_CN0_WIDTH     24u
#define EFTU_TOM_CHn_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CN0_CN0_SHIFT))&EFTU_TOM_CHn_CN0_CN0_MASK)
/* CH0_CN0 Reg Mask */
#define EFTU_TOM_CHn_CN0_MASK          0x00FFFFFFu

/* CHn_CM0 Bit Fields */
#define EFTU_TOM_CHn_CM0_CM0_MASK      0xFFFFFFu
#define EFTU_TOM_CHn_CM0_CM0_SHIFT     0u
#define EFTU_TOM_CHn_CM0_CM0_WIDTH     24u
#define EFTU_TOM_CHn_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CM0_CM0_SHIFT))&EFTU_TOM_CHn_CM0_CM0_MASK)
/* CH0_CM0 Reg Mask */
#define EFTU_TOM_CHn_CM0_MASK          0x00FFFFFFu

/* CHn_SR0 Bit Fields */
#define EFTU_TOM_CHn_SR0_SR0_MASK      0xFFFFFFu
#define EFTU_TOM_CHn_SR0_SR0_SHIFT     0u
#define EFTU_TOM_CHn_SR0_SR0_WIDTH     24u
#define EFTU_TOM_CHn_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_SR0_SR0_SHIFT))&EFTU_TOM_CHn_SR0_SR0_MASK)
/* CH0_SR0 Reg Mask */
#define EFTU_TOM_CHn_SR0_MASK          0x00FFFFFFu

/* CHn_CM1 Bit Fields */
#define EFTU_TOM_CHn_CM1_CM1_MASK      0xFFFFFFu
#define EFTU_TOM_CHn_CM1_CM1_SHIFT     0u
#define EFTU_TOM_CHn_CM1_CM1_WIDTH     24u
#define EFTU_TOM_CHn_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_CM1_CM1_SHIFT))&EFTU_TOM_CHn_CM1_CM1_MASK)
/* CH0_CM1 Reg Mask */
#define EFTU_TOM_CHn_CM1_MASK          0x00FFFFFFu

/* CHn_SR1 Bit Fields */
#define EFTU_TOM_CHn_SR1_SR1_MASK      0xFFFFFFu
#define EFTU_TOM_CHn_SR1_SR1_SHIFT     0u
#define EFTU_TOM_CHn_SR1_SR1_WIDTH     24u
#define EFTU_TOM_CHn_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_SR1_SR1_SHIFT))&EFTU_TOM_CHn_SR1_SR1_MASK)
/* CH0_SR1 Reg Mask */
#define EFTU_TOM_CHn_SR1_MASK          0x00FFFFFFu

/* CHn_IRQ_ST Bit Fields */
#define EFTU_TOM_CHn_IRQ_ST_CCU0TC_MASK 0x1u
#define EFTU_TOM_CHn_IRQ_ST_CCU0TC_SHIFT 0u
#define EFTU_TOM_CHn_IRQ_ST_CCU0TC_WIDTH 1u
#define EFTU_TOM_CHn_IRQ_ST_CCU0TC(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_IRQ_ST_CCU0TC_SHIFT))&EFTU_TOM_CHn_IRQ_ST_CCU0TC_MASK)
#define EFTU_TOM_CHn_IRQ_ST_CCU1TC_MASK 0x2u
#define EFTU_TOM_CHn_IRQ_ST_CCU1TC_SHIFT 1u
#define EFTU_TOM_CHn_IRQ_ST_CCU1TC_WIDTH 1u
#define EFTU_TOM_CHn_IRQ_ST_CCU1TC(x)  (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_IRQ_ST_CCU1TC_SHIFT))&EFTU_TOM_CHn_IRQ_ST_CCU1TC_MASK)
/* CH0_IRQ_ST Reg Mask */
#define EFTU_TOM_CHn_IRQ_ST_MASK       0x00000003u

/* CHn_IRQ_EN Bit Fields */
#define EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_MASK 0x1u
#define EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_SHIFT 0u
#define EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_WIDTH 1u
#define EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_SHIFT))&EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_MASK)
#define EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_MASK 0x2u
#define EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_SHIFT 1u
#define EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_WIDTH 1u
#define EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_SHIFT))&EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_MASK)
/* CH0_IRQ_EN Reg Mask */
#define EFTU_TOM_CHn_IRQ_EN_MASK       0x00000003u


/*!
 * @}
 */ /* end of group EFTU_TOM_Register_Masks */

/*!
 * @}
 */ /* end of group EFTU_TOM_Peripheral_Access_Layer */

#endif
