#ifndef _MODULE_CSC1_gmbhdijq176_REGS_H_CSC1_H_
#define _MODULE_CSC1_gmbhdijq176_REGS_H_CSC1_H_

/* ----------------------------------------------------------------------------
   -- CSC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSC1_Peripheral_Access_Layer CSC1 Peripheral Access Layer
 * @{
 */

/** CSC1 - Size of Registers Arrays */

/** CSC1 - Register Layout Typedef */

typedef struct {

  __IO uint32_t STOP_MODER0                   ; /* STOP Mode Control Register 0, offset: 0x0 */
  __IO uint32_t STOP_REQR0                    ; /* STOP Request Register 0, offset: 0x4 */
  __I  uint32_t STOP_ACKR0                    ; /* STOP Acknowledge Register 0, offset: 0x8 */
  __IO uint32_t STOP_MODER1                   ; /* STOP Mode Control Register 1, offset: 0xC */
  __IO uint32_t STOP_REQR1                    ; /* STOP Request Register 1, offset: 0x10 */
  __I  uint32_t STOP_ACKR1                    ; /* STOP Acknowledge Register 1, offset: 0x14 */
  __IO uint32_t STOP_MODER2                   ; /* STOP Mode Control Register 2, offset: 0x18 */
  __IO uint32_t STOP_REQR2                    ; /* STOP Request Register2, offset: 0x1C */
  __I  uint32_t STOP_ACKR2                    ; /* STOP Acknowledge Register 2, offset: 0x20 */
  __IO uint32_t CCM1_CFG                       ; /* CCM1 Configuration Register, offset: 0x24 */
       uint8_t  RESERVED_0[8];
  __IO uint32_t CPU1_INT                       ; /* CPU1 Software Interrupt Register, offset: 0x30 */

} CSC1_Type, *CSC1_MemMapPtr;


/* CSC1 - Peripheral instance base addresses */
/** Peripheral CSC1 base address */
#define CSC1_BASE                                (0x4007a000u)
/** Peripheral CSC1 base pointer */
#define CSC1                                     ((CSC1_Type *)CSC1_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the CSC1 module. */
//#define CSC1_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the CSC1 module. */
//#define CSC1_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the CSC1 peripheral type */
//#define CSC1_IRQS                                {CSC1_IRQn}


/* ----------------------------------------------------------------------------
   -- CSC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSC1_Register_Masks CSC1 Register Masks
 * @{
 */

/* STOP_MODER0 Bit Fields */
#define CSC1_STOP_MODER0_WPB_LOCK_MASK 0x80000000u
#define CSC1_STOP_MODER0_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_MODER0_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_MODER0_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_WPB_LOCK_SHIFT))&CSC1_STOP_MODER0_WPB_LOCK_MASK)
#define CSC1_STOP_MODER0_WPB_MASK      0x70000000u
#define CSC1_STOP_MODER0_WPB_SHIFT     28u
#define CSC1_STOP_MODER0_WPB_WIDTH     3u
#define CSC1_STOP_MODER0_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_WPB_SHIFT))&CSC1_STOP_MODER0_WPB_MASK)
#define CSC1_STOP_MODER0_ADC3_MASK     0x8000000u
#define CSC1_STOP_MODER0_ADC3_SHIFT    27u
#define CSC1_STOP_MODER0_ADC3_WIDTH    1u
#define CSC1_STOP_MODER0_ADC3(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_ADC3_SHIFT))&CSC1_STOP_MODER0_ADC3_MASK)
#define CSC1_STOP_MODER0_ADC2_MASK     0x4000000u
#define CSC1_STOP_MODER0_ADC2_SHIFT    26u
#define CSC1_STOP_MODER0_ADC2_WIDTH    1u
#define CSC1_STOP_MODER0_ADC2(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_ADC2_SHIFT))&CSC1_STOP_MODER0_ADC2_MASK)
#define CSC1_STOP_MODER0_FLEXCAN4_MASK 0x2000000u
#define CSC1_STOP_MODER0_FLEXCAN4_SHIFT 25u
#define CSC1_STOP_MODER0_FLEXCAN4_WIDTH 1u
#define CSC1_STOP_MODER0_FLEXCAN4(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FLEXCAN4_SHIFT))&CSC1_STOP_MODER0_FLEXCAN4_MASK)
#define CSC1_STOP_MODER0_FLEXCAN3_MASK 0x1000000u
#define CSC1_STOP_MODER0_FLEXCAN3_SHIFT 24u
#define CSC1_STOP_MODER0_FLEXCAN3_WIDTH 1u
#define CSC1_STOP_MODER0_FLEXCAN3(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FLEXCAN3_SHIFT))&CSC1_STOP_MODER0_FLEXCAN3_MASK)
#define CSC1_STOP_MODER0_FLEXCAN2_MASK 0x800000u
#define CSC1_STOP_MODER0_FLEXCAN2_SHIFT 23u
#define CSC1_STOP_MODER0_FLEXCAN2_WIDTH 1u
#define CSC1_STOP_MODER0_FLEXCAN2(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FLEXCAN2_SHIFT))&CSC1_STOP_MODER0_FLEXCAN2_MASK)
#define CSC1_STOP_MODER0_FLEXCAN1_MASK 0x400000u
#define CSC1_STOP_MODER0_FLEXCAN1_SHIFT 22u
#define CSC1_STOP_MODER0_FLEXCAN1_WIDTH 1u
#define CSC1_STOP_MODER0_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FLEXCAN1_SHIFT))&CSC1_STOP_MODER0_FLEXCAN1_MASK)
#define CSC1_STOP_MODER0_FLEXCAN0_MASK 0x200000u
#define CSC1_STOP_MODER0_FLEXCAN0_SHIFT 21u
#define CSC1_STOP_MODER0_FLEXCAN0_WIDTH 1u
#define CSC1_STOP_MODER0_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FLEXCAN0_SHIFT))&CSC1_STOP_MODER0_FLEXCAN0_MASK)
#define CSC1_STOP_MODER0_FCUART7_MASK  0x100000u
#define CSC1_STOP_MODER0_FCUART7_SHIFT 20u
#define CSC1_STOP_MODER0_FCUART7_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART7(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART7_SHIFT))&CSC1_STOP_MODER0_FCUART7_MASK)
#define CSC1_STOP_MODER0_FCUART6_MASK  0x80000u
#define CSC1_STOP_MODER0_FCUART6_SHIFT 19u
#define CSC1_STOP_MODER0_FCUART6_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART6(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART6_SHIFT))&CSC1_STOP_MODER0_FCUART6_MASK)
#define CSC1_STOP_MODER0_FCUART5_MASK  0x40000u
#define CSC1_STOP_MODER0_FCUART5_SHIFT 18u
#define CSC1_STOP_MODER0_FCUART5_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART5(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART5_SHIFT))&CSC1_STOP_MODER0_FCUART5_MASK)
#define CSC1_STOP_MODER0_FCUART4_MASK  0x20000u
#define CSC1_STOP_MODER0_FCUART4_SHIFT 17u
#define CSC1_STOP_MODER0_FCUART4_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART4(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART4_SHIFT))&CSC1_STOP_MODER0_FCUART4_MASK)
#define CSC1_STOP_MODER0_FCUART3_MASK  0x10000u
#define CSC1_STOP_MODER0_FCUART3_SHIFT 16u
#define CSC1_STOP_MODER0_FCUART3_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART3(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART3_SHIFT))&CSC1_STOP_MODER0_FCUART3_MASK)
#define CSC1_STOP_MODER0_FCUART2_MASK  0x8000u
#define CSC1_STOP_MODER0_FCUART2_SHIFT 15u
#define CSC1_STOP_MODER0_FCUART2_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART2(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART2_SHIFT))&CSC1_STOP_MODER0_FCUART2_MASK)
#define CSC1_STOP_MODER0_FCUART1_MASK  0x4000u
#define CSC1_STOP_MODER0_FCUART1_SHIFT 14u
#define CSC1_STOP_MODER0_FCUART1_WIDTH 1u
#define CSC1_STOP_MODER0_FCUART1(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCUART1_SHIFT))&CSC1_STOP_MODER0_FCUART1_MASK)
#define CSC1_STOP_MODER0_FCSPI3_MASK   0x2000u
#define CSC1_STOP_MODER0_FCSPI3_SHIFT  13u
#define CSC1_STOP_MODER0_FCSPI3_WIDTH  1u
#define CSC1_STOP_MODER0_FCSPI3(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCSPI3_SHIFT))&CSC1_STOP_MODER0_FCSPI3_MASK)
#define CSC1_STOP_MODER0_FCSPI2_MASK   0x1000u
#define CSC1_STOP_MODER0_FCSPI2_SHIFT  12u
#define CSC1_STOP_MODER0_FCSPI2_WIDTH  1u
#define CSC1_STOP_MODER0_FCSPI2(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCSPI2_SHIFT))&CSC1_STOP_MODER0_FCSPI2_MASK)
#define CSC1_STOP_MODER0_FCSPI1_MASK   0x800u
#define CSC1_STOP_MODER0_FCSPI1_SHIFT  11u
#define CSC1_STOP_MODER0_FCSPI1_WIDTH  1u
#define CSC1_STOP_MODER0_FCSPI1(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_FCSPI1_SHIFT))&CSC1_STOP_MODER0_FCSPI1_MASK)
#define CSC1_STOP_MODER0_SENT0_MASK    0x400u
#define CSC1_STOP_MODER0_SENT0_SHIFT   10u
#define CSC1_STOP_MODER0_SENT0_WIDTH   1u
#define CSC1_STOP_MODER0_SENT0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_SENT0_SHIFT))&CSC1_STOP_MODER0_SENT0_MASK)
#define CSC1_STOP_MODER0_TMU_MASK      0x200u
#define CSC1_STOP_MODER0_TMU_SHIFT     9u
#define CSC1_STOP_MODER0_TMU_WIDTH     1u
#define CSC1_STOP_MODER0_TMU(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_TMU_SHIFT))&CSC1_STOP_MODER0_TMU_MASK)
#define CSC1_STOP_MODER0_ADC1_MASK     0x80u
#define CSC1_STOP_MODER0_ADC1_SHIFT    7u
#define CSC1_STOP_MODER0_ADC1_WIDTH    1u
#define CSC1_STOP_MODER0_ADC1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_ADC1_SHIFT))&CSC1_STOP_MODER0_ADC1_MASK)
#define CSC1_STOP_MODER0_ADC0_MASK     0x40u
#define CSC1_STOP_MODER0_ADC0_SHIFT    6u
#define CSC1_STOP_MODER0_ADC0_WIDTH    1u
#define CSC1_STOP_MODER0_ADC0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_ADC0_SHIFT))&CSC1_STOP_MODER0_ADC0_MASK)
#define CSC1_STOP_MODER0_CMU4_MASK     0x20u
#define CSC1_STOP_MODER0_CMU4_SHIFT    5u
#define CSC1_STOP_MODER0_CMU4_WIDTH    1u
#define CSC1_STOP_MODER0_CMU4(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_CMU4_SHIFT))&CSC1_STOP_MODER0_CMU4_MASK)
#define CSC1_STOP_MODER0_WDOG0_MASK    0x10u
#define CSC1_STOP_MODER0_WDOG0_SHIFT   4u
#define CSC1_STOP_MODER0_WDOG0_WIDTH   1u
#define CSC1_STOP_MODER0_WDOG0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_WDOG0_SHIFT))&CSC1_STOP_MODER0_WDOG0_MASK)
#define CSC1_STOP_MODER0_ISM0_MASK     0x2u
#define CSC1_STOP_MODER0_ISM0_SHIFT    1u
#define CSC1_STOP_MODER0_ISM0_WIDTH    1u
#define CSC1_STOP_MODER0_ISM0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_ISM0_SHIFT))&CSC1_STOP_MODER0_ISM0_MASK)
#define CSC1_STOP_MODER0_DMA0_MASK     0x1u
#define CSC1_STOP_MODER0_DMA0_SHIFT    0u
#define CSC1_STOP_MODER0_DMA0_WIDTH    1u
#define CSC1_STOP_MODER0_DMA0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER0_DMA0_SHIFT))&CSC1_STOP_MODER0_DMA0_MASK)
/* STOP_MODER0 Reg Mask */
#define CSC1_STOP_MODER0_MASK          0xFFFFFEF3u

/* STOP_REQR0 Bit Fields */
#define CSC1_STOP_REQR0_WPB_LOCK_MASK  0x80000000u
#define CSC1_STOP_REQR0_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_REQR0_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_REQR0_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_WPB_LOCK_SHIFT))&CSC1_STOP_REQR0_WPB_LOCK_MASK)
#define CSC1_STOP_REQR0_WPB_MASK       0x70000000u
#define CSC1_STOP_REQR0_WPB_SHIFT      28u
#define CSC1_STOP_REQR0_WPB_WIDTH      3u
#define CSC1_STOP_REQR0_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_WPB_SHIFT))&CSC1_STOP_REQR0_WPB_MASK)
#define CSC1_STOP_REQR0_ADC3_MASK      0x8000000u
#define CSC1_STOP_REQR0_ADC3_SHIFT     27u
#define CSC1_STOP_REQR0_ADC3_WIDTH     1u
#define CSC1_STOP_REQR0_ADC3(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_ADC3_SHIFT))&CSC1_STOP_REQR0_ADC3_MASK)
#define CSC1_STOP_REQR0_ADC2_MASK      0x4000000u
#define CSC1_STOP_REQR0_ADC2_SHIFT     26u
#define CSC1_STOP_REQR0_ADC2_WIDTH     1u
#define CSC1_STOP_REQR0_ADC2(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_ADC2_SHIFT))&CSC1_STOP_REQR0_ADC2_MASK)
#define CSC1_STOP_REQR0_FLEXCAN4_MASK  0x2000000u
#define CSC1_STOP_REQR0_FLEXCAN4_SHIFT 25u
#define CSC1_STOP_REQR0_FLEXCAN4_WIDTH 1u
#define CSC1_STOP_REQR0_FLEXCAN4(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLEXCAN4_SHIFT))&CSC1_STOP_REQR0_FLEXCAN4_MASK)
#define CSC1_STOP_REQR0_FLEXCAN3_MASK  0x1000000u
#define CSC1_STOP_REQR0_FLEXCAN3_SHIFT 24u
#define CSC1_STOP_REQR0_FLEXCAN3_WIDTH 1u
#define CSC1_STOP_REQR0_FLEXCAN3(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLEXCAN3_SHIFT))&CSC1_STOP_REQR0_FLEXCAN3_MASK)
#define CSC1_STOP_REQR0_FLEXCAN2_MASK  0x800000u
#define CSC1_STOP_REQR0_FLEXCAN2_SHIFT 23u
#define CSC1_STOP_REQR0_FLEXCAN2_WIDTH 1u
#define CSC1_STOP_REQR0_FLEXCAN2(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLEXCAN2_SHIFT))&CSC1_STOP_REQR0_FLEXCAN2_MASK)
#define CSC1_STOP_REQR0_FLEXCAN1_MASK  0x400000u
#define CSC1_STOP_REQR0_FLEXCAN1_SHIFT 22u
#define CSC1_STOP_REQR0_FLEXCAN1_WIDTH 1u
#define CSC1_STOP_REQR0_FLEXCAN1(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLEXCAN1_SHIFT))&CSC1_STOP_REQR0_FLEXCAN1_MASK)
#define CSC1_STOP_REQR0_FLEXCAN0_MASK  0x200000u
#define CSC1_STOP_REQR0_FLEXCAN0_SHIFT 21u
#define CSC1_STOP_REQR0_FLEXCAN0_WIDTH 1u
#define CSC1_STOP_REQR0_FLEXCAN0(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLEXCAN0_SHIFT))&CSC1_STOP_REQR0_FLEXCAN0_MASK)
#define CSC1_STOP_REQR0_FCUART7_MASK   0x100000u
#define CSC1_STOP_REQR0_FCUART7_SHIFT  20u
#define CSC1_STOP_REQR0_FCUART7_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART7(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART7_SHIFT))&CSC1_STOP_REQR0_FCUART7_MASK)
#define CSC1_STOP_REQR0_FCUART6_MASK   0x80000u
#define CSC1_STOP_REQR0_FCUART6_SHIFT  19u
#define CSC1_STOP_REQR0_FCUART6_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART6(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART6_SHIFT))&CSC1_STOP_REQR0_FCUART6_MASK)
#define CSC1_STOP_REQR0_FCUART5_MASK   0x40000u
#define CSC1_STOP_REQR0_FCUART5_SHIFT  18u
#define CSC1_STOP_REQR0_FCUART5_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART5(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART5_SHIFT))&CSC1_STOP_REQR0_FCUART5_MASK)
#define CSC1_STOP_REQR0_FCUART4_MASK   0x20000u
#define CSC1_STOP_REQR0_FCUART4_SHIFT  17u
#define CSC1_STOP_REQR0_FCUART4_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART4(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART4_SHIFT))&CSC1_STOP_REQR0_FCUART4_MASK)
#define CSC1_STOP_REQR0_FCUART3_MASK   0x10000u
#define CSC1_STOP_REQR0_FCUART3_SHIFT  16u
#define CSC1_STOP_REQR0_FCUART3_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART3(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART3_SHIFT))&CSC1_STOP_REQR0_FCUART3_MASK)
#define CSC1_STOP_REQR0_FCUART2_MASK   0x8000u
#define CSC1_STOP_REQR0_FCUART2_SHIFT  15u
#define CSC1_STOP_REQR0_FCUART2_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART2(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART2_SHIFT))&CSC1_STOP_REQR0_FCUART2_MASK)
#define CSC1_STOP_REQR0_FCUART1_MASK   0x4000u
#define CSC1_STOP_REQR0_FCUART1_SHIFT  14u
#define CSC1_STOP_REQR0_FCUART1_WIDTH  1u
#define CSC1_STOP_REQR0_FCUART1(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCUART1_SHIFT))&CSC1_STOP_REQR0_FCUART1_MASK)
#define CSC1_STOP_REQR0_FCSPI3_MASK    0x2000u
#define CSC1_STOP_REQR0_FCSPI3_SHIFT   13u
#define CSC1_STOP_REQR0_FCSPI3_WIDTH   1u
#define CSC1_STOP_REQR0_FCSPI3(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCSPI3_SHIFT))&CSC1_STOP_REQR0_FCSPI3_MASK)
#define CSC1_STOP_REQR0_FCSPI2_MASK    0x1000u
#define CSC1_STOP_REQR0_FCSPI2_SHIFT   12u
#define CSC1_STOP_REQR0_FCSPI2_WIDTH   1u
#define CSC1_STOP_REQR0_FCSPI2(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCSPI2_SHIFT))&CSC1_STOP_REQR0_FCSPI2_MASK)
#define CSC1_STOP_REQR0_FCSPI1_MASK    0x800u
#define CSC1_STOP_REQR0_FCSPI1_SHIFT   11u
#define CSC1_STOP_REQR0_FCSPI1_WIDTH   1u
#define CSC1_STOP_REQR0_FCSPI1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FCSPI1_SHIFT))&CSC1_STOP_REQR0_FCSPI1_MASK)
#define CSC1_STOP_REQR0_SENT0_MASK     0x400u
#define CSC1_STOP_REQR0_SENT0_SHIFT    10u
#define CSC1_STOP_REQR0_SENT0_WIDTH    1u
#define CSC1_STOP_REQR0_SENT0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_SENT0_SHIFT))&CSC1_STOP_REQR0_SENT0_MASK)
#define CSC1_STOP_REQR0_TMU_MASK       0x200u
#define CSC1_STOP_REQR0_TMU_SHIFT      9u
#define CSC1_STOP_REQR0_TMU_WIDTH      1u
#define CSC1_STOP_REQR0_TMU(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_TMU_SHIFT))&CSC1_STOP_REQR0_TMU_MASK)
#define CSC1_STOP_REQR0_ADC1_MASK      0x80u
#define CSC1_STOP_REQR0_ADC1_SHIFT     7u
#define CSC1_STOP_REQR0_ADC1_WIDTH     1u
#define CSC1_STOP_REQR0_ADC1(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_ADC1_SHIFT))&CSC1_STOP_REQR0_ADC1_MASK)
#define CSC1_STOP_REQR0_ADC0_MASK      0x40u
#define CSC1_STOP_REQR0_ADC0_SHIFT     6u
#define CSC1_STOP_REQR0_ADC0_WIDTH     1u
#define CSC1_STOP_REQR0_ADC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_ADC0_SHIFT))&CSC1_STOP_REQR0_ADC0_MASK)
#define CSC1_STOP_REQR0_CMU4_MASK      0x20u
#define CSC1_STOP_REQR0_CMU4_SHIFT     5u
#define CSC1_STOP_REQR0_CMU4_WIDTH     1u
#define CSC1_STOP_REQR0_CMU4(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_CMU4_SHIFT))&CSC1_STOP_REQR0_CMU4_MASK)
#define CSC1_STOP_REQR0_WDOG0_MASK     0x10u
#define CSC1_STOP_REQR0_WDOG0_SHIFT    4u
#define CSC1_STOP_REQR0_WDOG0_WIDTH    1u
#define CSC1_STOP_REQR0_WDOG0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_WDOG0_SHIFT))&CSC1_STOP_REQR0_WDOG0_MASK)
#define CSC1_STOP_REQR0_FLASH_MASK     0x4u
#define CSC1_STOP_REQR0_FLASH_SHIFT    2u
#define CSC1_STOP_REQR0_FLASH_WIDTH    1u
#define CSC1_STOP_REQR0_FLASH(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_FLASH_SHIFT))&CSC1_STOP_REQR0_FLASH_MASK)
#define CSC1_STOP_REQR0_ISM0_MASK      0x2u
#define CSC1_STOP_REQR0_ISM0_SHIFT     1u
#define CSC1_STOP_REQR0_ISM0_WIDTH     1u
#define CSC1_STOP_REQR0_ISM0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_ISM0_SHIFT))&CSC1_STOP_REQR0_ISM0_MASK)
#define CSC1_STOP_REQR0_DMA0_MASK      0x1u
#define CSC1_STOP_REQR0_DMA0_SHIFT     0u
#define CSC1_STOP_REQR0_DMA0_WIDTH     1u
#define CSC1_STOP_REQR0_DMA0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR0_DMA0_SHIFT))&CSC1_STOP_REQR0_DMA0_MASK)
/* STOP_REQR0 Reg Mask */
#define CSC1_STOP_REQR0_MASK           0xFFFFFEF7u

/* STOP_ACKR0 Bit Fields */
#define CSC1_STOP_ACKR0_ADC3_MASK      0x8000000u
#define CSC1_STOP_ACKR0_ADC3_SHIFT     27u
#define CSC1_STOP_ACKR0_ADC3_WIDTH     1u
#define CSC1_STOP_ACKR0_ADC3(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_ADC3_SHIFT))&CSC1_STOP_ACKR0_ADC3_MASK)
#define CSC1_STOP_ACKR0_ADC2_MASK      0x4000000u
#define CSC1_STOP_ACKR0_ADC2_SHIFT     26u
#define CSC1_STOP_ACKR0_ADC2_WIDTH     1u
#define CSC1_STOP_ACKR0_ADC2(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_ADC2_SHIFT))&CSC1_STOP_ACKR0_ADC2_MASK)
#define CSC1_STOP_ACKR0_FLEXCAN4_MASK  0x2000000u
#define CSC1_STOP_ACKR0_FLEXCAN4_SHIFT 25u
#define CSC1_STOP_ACKR0_FLEXCAN4_WIDTH 1u
#define CSC1_STOP_ACKR0_FLEXCAN4(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLEXCAN4_SHIFT))&CSC1_STOP_ACKR0_FLEXCAN4_MASK)
#define CSC1_STOP_ACKR0_FLEXCAN3_MASK  0x1000000u
#define CSC1_STOP_ACKR0_FLEXCAN3_SHIFT 24u
#define CSC1_STOP_ACKR0_FLEXCAN3_WIDTH 1u
#define CSC1_STOP_ACKR0_FLEXCAN3(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLEXCAN3_SHIFT))&CSC1_STOP_ACKR0_FLEXCAN3_MASK)
#define CSC1_STOP_ACKR0_FLEXCAN2_MASK  0x800000u
#define CSC1_STOP_ACKR0_FLEXCAN2_SHIFT 23u
#define CSC1_STOP_ACKR0_FLEXCAN2_WIDTH 1u
#define CSC1_STOP_ACKR0_FLEXCAN2(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLEXCAN2_SHIFT))&CSC1_STOP_ACKR0_FLEXCAN2_MASK)
#define CSC1_STOP_ACKR0_FLEXCAN1_MASK  0x400000u
#define CSC1_STOP_ACKR0_FLEXCAN1_SHIFT 22u
#define CSC1_STOP_ACKR0_FLEXCAN1_WIDTH 1u
#define CSC1_STOP_ACKR0_FLEXCAN1(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLEXCAN1_SHIFT))&CSC1_STOP_ACKR0_FLEXCAN1_MASK)
#define CSC1_STOP_ACKR0_FLEXCAN0_MASK  0x200000u
#define CSC1_STOP_ACKR0_FLEXCAN0_SHIFT 21u
#define CSC1_STOP_ACKR0_FLEXCAN0_WIDTH 1u
#define CSC1_STOP_ACKR0_FLEXCAN0(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLEXCAN0_SHIFT))&CSC1_STOP_ACKR0_FLEXCAN0_MASK)
#define CSC1_STOP_ACKR0_FCUART7_MASK   0x100000u
#define CSC1_STOP_ACKR0_FCUART7_SHIFT  20u
#define CSC1_STOP_ACKR0_FCUART7_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART7(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART7_SHIFT))&CSC1_STOP_ACKR0_FCUART7_MASK)
#define CSC1_STOP_ACKR0_FCUART6_MASK   0x80000u
#define CSC1_STOP_ACKR0_FCUART6_SHIFT  19u
#define CSC1_STOP_ACKR0_FCUART6_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART6(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART6_SHIFT))&CSC1_STOP_ACKR0_FCUART6_MASK)
#define CSC1_STOP_ACKR0_FCUART5_MASK   0x40000u
#define CSC1_STOP_ACKR0_FCUART5_SHIFT  18u
#define CSC1_STOP_ACKR0_FCUART5_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART5(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART5_SHIFT))&CSC1_STOP_ACKR0_FCUART5_MASK)
#define CSC1_STOP_ACKR0_FCUART4_MASK   0x20000u
#define CSC1_STOP_ACKR0_FCUART4_SHIFT  17u
#define CSC1_STOP_ACKR0_FCUART4_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART4(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART4_SHIFT))&CSC1_STOP_ACKR0_FCUART4_MASK)
#define CSC1_STOP_ACKR0_FCUART3_MASK   0x10000u
#define CSC1_STOP_ACKR0_FCUART3_SHIFT  16u
#define CSC1_STOP_ACKR0_FCUART3_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART3(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART3_SHIFT))&CSC1_STOP_ACKR0_FCUART3_MASK)
#define CSC1_STOP_ACKR0_FCUART2_MASK   0x8000u
#define CSC1_STOP_ACKR0_FCUART2_SHIFT  15u
#define CSC1_STOP_ACKR0_FCUART2_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART2(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART2_SHIFT))&CSC1_STOP_ACKR0_FCUART2_MASK)
#define CSC1_STOP_ACKR0_FCUART1_MASK   0x4000u
#define CSC1_STOP_ACKR0_FCUART1_SHIFT  14u
#define CSC1_STOP_ACKR0_FCUART1_WIDTH  1u
#define CSC1_STOP_ACKR0_FCUART1(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCUART1_SHIFT))&CSC1_STOP_ACKR0_FCUART1_MASK)
#define CSC1_STOP_ACKR0_FCSPI3_MASK    0x2000u
#define CSC1_STOP_ACKR0_FCSPI3_SHIFT   13u
#define CSC1_STOP_ACKR0_FCSPI3_WIDTH   1u
#define CSC1_STOP_ACKR0_FCSPI3(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCSPI3_SHIFT))&CSC1_STOP_ACKR0_FCSPI3_MASK)
#define CSC1_STOP_ACKR0_FCSPI2_MASK    0x1000u
#define CSC1_STOP_ACKR0_FCSPI2_SHIFT   12u
#define CSC1_STOP_ACKR0_FCSPI2_WIDTH   1u
#define CSC1_STOP_ACKR0_FCSPI2(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCSPI2_SHIFT))&CSC1_STOP_ACKR0_FCSPI2_MASK)
#define CSC1_STOP_ACKR0_FCSPI1_MASK    0x800u
#define CSC1_STOP_ACKR0_FCSPI1_SHIFT   11u
#define CSC1_STOP_ACKR0_FCSPI1_WIDTH   1u
#define CSC1_STOP_ACKR0_FCSPI1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FCSPI1_SHIFT))&CSC1_STOP_ACKR0_FCSPI1_MASK)
#define CSC1_STOP_ACKR0_SENT0_MASK     0x400u
#define CSC1_STOP_ACKR0_SENT0_SHIFT    10u
#define CSC1_STOP_ACKR0_SENT0_WIDTH    1u
#define CSC1_STOP_ACKR0_SENT0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_SENT0_SHIFT))&CSC1_STOP_ACKR0_SENT0_MASK)
#define CSC1_STOP_ACKR0_TMU_MASK       0x200u
#define CSC1_STOP_ACKR0_TMU_SHIFT      9u
#define CSC1_STOP_ACKR0_TMU_WIDTH      1u
#define CSC1_STOP_ACKR0_TMU(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_TMU_SHIFT))&CSC1_STOP_ACKR0_TMU_MASK)
#define CSC1_STOP_ACKR0_ADC1_MASK      0x80u
#define CSC1_STOP_ACKR0_ADC1_SHIFT     7u
#define CSC1_STOP_ACKR0_ADC1_WIDTH     1u
#define CSC1_STOP_ACKR0_ADC1(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_ADC1_SHIFT))&CSC1_STOP_ACKR0_ADC1_MASK)
#define CSC1_STOP_ACKR0_ADC0_MASK      0x40u
#define CSC1_STOP_ACKR0_ADC0_SHIFT     6u
#define CSC1_STOP_ACKR0_ADC0_WIDTH     1u
#define CSC1_STOP_ACKR0_ADC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_ADC0_SHIFT))&CSC1_STOP_ACKR0_ADC0_MASK)
#define CSC1_STOP_ACKR0_CMU4_MASK      0x20u
#define CSC1_STOP_ACKR0_CMU4_SHIFT     5u
#define CSC1_STOP_ACKR0_CMU4_WIDTH     1u
#define CSC1_STOP_ACKR0_CMU4(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_CMU4_SHIFT))&CSC1_STOP_ACKR0_CMU4_MASK)
#define CSC1_STOP_ACKR0_WDOG0_MASK     0x10u
#define CSC1_STOP_ACKR0_WDOG0_SHIFT    4u
#define CSC1_STOP_ACKR0_WDOG0_WIDTH    1u
#define CSC1_STOP_ACKR0_WDOG0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_WDOG0_SHIFT))&CSC1_STOP_ACKR0_WDOG0_MASK)
#define CSC1_STOP_ACKR0_FLASH_MASK     0x4u
#define CSC1_STOP_ACKR0_FLASH_SHIFT    2u
#define CSC1_STOP_ACKR0_FLASH_WIDTH    1u
#define CSC1_STOP_ACKR0_FLASH(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_FLASH_SHIFT))&CSC1_STOP_ACKR0_FLASH_MASK)
#define CSC1_STOP_ACKR0_ISM0_MASK      0x2u
#define CSC1_STOP_ACKR0_ISM0_SHIFT     1u
#define CSC1_STOP_ACKR0_ISM0_WIDTH     1u
#define CSC1_STOP_ACKR0_ISM0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_ISM0_SHIFT))&CSC1_STOP_ACKR0_ISM0_MASK)
#define CSC1_STOP_ACKR0_DMA0_MASK      0x1u
#define CSC1_STOP_ACKR0_DMA0_SHIFT     0u
#define CSC1_STOP_ACKR0_DMA0_WIDTH     1u
#define CSC1_STOP_ACKR0_DMA0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR0_DMA0_SHIFT))&CSC1_STOP_ACKR0_DMA0_MASK)
/* STOP_ACKR0 Reg Mask */
#define CSC1_STOP_ACKR0_MASK           0x0FFFFEF7u

/* STOP_MODER1 Bit Fields */
#define CSC1_STOP_MODER1_WPB_LOCK_MASK 0x80000000u
#define CSC1_STOP_MODER1_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_MODER1_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_MODER1_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_WPB_LOCK_SHIFT))&CSC1_STOP_MODER1_WPB_LOCK_MASK)
#define CSC1_STOP_MODER1_WPB_MASK      0x70000000u
#define CSC1_STOP_MODER1_WPB_SHIFT     28u
#define CSC1_STOP_MODER1_WPB_WIDTH     3u
#define CSC1_STOP_MODER1_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_WPB_SHIFT))&CSC1_STOP_MODER1_WPB_MASK)
#define CSC1_STOP_MODER1_FLEXCAN7_MASK 0x2000000u
#define CSC1_STOP_MODER1_FLEXCAN7_SHIFT 25u
#define CSC1_STOP_MODER1_FLEXCAN7_WIDTH 1u
#define CSC1_STOP_MODER1_FLEXCAN7(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FLEXCAN7_SHIFT))&CSC1_STOP_MODER1_FLEXCAN7_MASK)
#define CSC1_STOP_MODER1_FLEXCAN6_MASK 0x1000000u
#define CSC1_STOP_MODER1_FLEXCAN6_SHIFT 24u
#define CSC1_STOP_MODER1_FLEXCAN6_WIDTH 1u
#define CSC1_STOP_MODER1_FLEXCAN6(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FLEXCAN6_SHIFT))&CSC1_STOP_MODER1_FLEXCAN6_MASK)
#define CSC1_STOP_MODER1_FLEXCAN5_MASK 0x800000u
#define CSC1_STOP_MODER1_FLEXCAN5_SHIFT 23u
#define CSC1_STOP_MODER1_FLEXCAN5_WIDTH 1u
#define CSC1_STOP_MODER1_FLEXCAN5(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FLEXCAN5_SHIFT))&CSC1_STOP_MODER1_FLEXCAN5_MASK)
#define CSC1_STOP_MODER1_MSC0_MASK     0x200000u
#define CSC1_STOP_MODER1_MSC0_SHIFT    21u
#define CSC1_STOP_MODER1_MSC0_WIDTH    1u
#define CSC1_STOP_MODER1_MSC0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_MSC0_SHIFT))&CSC1_STOP_MODER1_MSC0_MASK)
#define CSC1_STOP_MODER1_FCSPI5_MASK   0x100000u
#define CSC1_STOP_MODER1_FCSPI5_SHIFT  20u
#define CSC1_STOP_MODER1_FCSPI5_WIDTH  1u
#define CSC1_STOP_MODER1_FCSPI5(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FCSPI5_SHIFT))&CSC1_STOP_MODER1_FCSPI5_MASK)
#define CSC1_STOP_MODER1_FCSPI4_MASK   0x80000u
#define CSC1_STOP_MODER1_FCSPI4_SHIFT  19u
#define CSC1_STOP_MODER1_FCSPI4_WIDTH  1u
#define CSC1_STOP_MODER1_FCSPI4(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FCSPI4_SHIFT))&CSC1_STOP_MODER1_FCSPI4_MASK)
#define CSC1_STOP_MODER1_FCIIC1_MASK   0x400u
#define CSC1_STOP_MODER1_FCIIC1_SHIFT  10u
#define CSC1_STOP_MODER1_FCIIC1_WIDTH  1u
#define CSC1_STOP_MODER1_FCIIC1(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_FCIIC1_SHIFT))&CSC1_STOP_MODER1_FCIIC1_MASK)
#define CSC1_STOP_MODER1_SENT1_MASK    0x200u
#define CSC1_STOP_MODER1_SENT1_SHIFT   9u
#define CSC1_STOP_MODER1_SENT1_WIDTH   1u
#define CSC1_STOP_MODER1_SENT1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_SENT1_SHIFT))&CSC1_STOP_MODER1_SENT1_MASK)
#define CSC1_STOP_MODER1_WDOG1_MASK    0x2u
#define CSC1_STOP_MODER1_WDOG1_SHIFT   1u
#define CSC1_STOP_MODER1_WDOG1_WIDTH   1u
#define CSC1_STOP_MODER1_WDOG1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER1_WDOG1_SHIFT))&CSC1_STOP_MODER1_WDOG1_MASK)
/* STOP_MODER1 Reg Mask */
#define CSC1_STOP_MODER1_MASK          0xF3B80602u

/* STOP_REQR1 Bit Fields */
#define CSC1_STOP_REQR1_WPB_LOCK_MASK  0x80000000u
#define CSC1_STOP_REQR1_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_REQR1_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_REQR1_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_WPB_LOCK_SHIFT))&CSC1_STOP_REQR1_WPB_LOCK_MASK)
#define CSC1_STOP_REQR1_WPB_MASK       0x70000000u
#define CSC1_STOP_REQR1_WPB_SHIFT      28u
#define CSC1_STOP_REQR1_WPB_WIDTH      3u
#define CSC1_STOP_REQR1_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_WPB_SHIFT))&CSC1_STOP_REQR1_WPB_MASK)
#define CSC1_STOP_REQR1_FLEXCAN7_MASK  0x2000000u
#define CSC1_STOP_REQR1_FLEXCAN7_SHIFT 25u
#define CSC1_STOP_REQR1_FLEXCAN7_WIDTH 1u
#define CSC1_STOP_REQR1_FLEXCAN7(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FLEXCAN7_SHIFT))&CSC1_STOP_REQR1_FLEXCAN7_MASK)
#define CSC1_STOP_REQR1_FLEXCAN6_MASK  0x1000000u
#define CSC1_STOP_REQR1_FLEXCAN6_SHIFT 24u
#define CSC1_STOP_REQR1_FLEXCAN6_WIDTH 1u
#define CSC1_STOP_REQR1_FLEXCAN6(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FLEXCAN6_SHIFT))&CSC1_STOP_REQR1_FLEXCAN6_MASK)
#define CSC1_STOP_REQR1_FLEXCAN5_MASK  0x800000u
#define CSC1_STOP_REQR1_FLEXCAN5_SHIFT 23u
#define CSC1_STOP_REQR1_FLEXCAN5_WIDTH 1u
#define CSC1_STOP_REQR1_FLEXCAN5(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FLEXCAN5_SHIFT))&CSC1_STOP_REQR1_FLEXCAN5_MASK)
#define CSC1_STOP_REQR1_MSC0_MASK      0x200000u
#define CSC1_STOP_REQR1_MSC0_SHIFT     21u
#define CSC1_STOP_REQR1_MSC0_WIDTH     1u
#define CSC1_STOP_REQR1_MSC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_MSC0_SHIFT))&CSC1_STOP_REQR1_MSC0_MASK)
#define CSC1_STOP_REQR1_FCSPI5_MASK    0x100000u
#define CSC1_STOP_REQR1_FCSPI5_SHIFT   20u
#define CSC1_STOP_REQR1_FCSPI5_WIDTH   1u
#define CSC1_STOP_REQR1_FCSPI5(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FCSPI5_SHIFT))&CSC1_STOP_REQR1_FCSPI5_MASK)
#define CSC1_STOP_REQR1_FCSPI4_MASK    0x80000u
#define CSC1_STOP_REQR1_FCSPI4_SHIFT   19u
#define CSC1_STOP_REQR1_FCSPI4_WIDTH   1u
#define CSC1_STOP_REQR1_FCSPI4(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FCSPI4_SHIFT))&CSC1_STOP_REQR1_FCSPI4_MASK)
#define CSC1_STOP_REQR1_FCIIC1_MASK    0x400u
#define CSC1_STOP_REQR1_FCIIC1_SHIFT   10u
#define CSC1_STOP_REQR1_FCIIC1_WIDTH   1u
#define CSC1_STOP_REQR1_FCIIC1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_FCIIC1_SHIFT))&CSC1_STOP_REQR1_FCIIC1_MASK)
#define CSC1_STOP_REQR1_SENT1_MASK     0x200u
#define CSC1_STOP_REQR1_SENT1_SHIFT    9u
#define CSC1_STOP_REQR1_SENT1_WIDTH    1u
#define CSC1_STOP_REQR1_SENT1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_SENT1_SHIFT))&CSC1_STOP_REQR1_SENT1_MASK)
#define CSC1_STOP_REQR1_WDOG1_MASK     0x2u
#define CSC1_STOP_REQR1_WDOG1_SHIFT    1u
#define CSC1_STOP_REQR1_WDOG1_WIDTH    1u
#define CSC1_STOP_REQR1_WDOG1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR1_WDOG1_SHIFT))&CSC1_STOP_REQR1_WDOG1_MASK)
/* STOP_REQR1 Reg Mask */
#define CSC1_STOP_REQR1_MASK           0xF3B80602u

/* STOP_ACKR1 Bit Fields */
#define CSC1_STOP_ACKR1_FLEXCAN7_MASK  0x2000000u
#define CSC1_STOP_ACKR1_FLEXCAN7_SHIFT 25u
#define CSC1_STOP_ACKR1_FLEXCAN7_WIDTH 1u
#define CSC1_STOP_ACKR1_FLEXCAN7(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FLEXCAN7_SHIFT))&CSC1_STOP_ACKR1_FLEXCAN7_MASK)
#define CSC1_STOP_ACKR1_FLEXCAN6_MASK  0x1000000u
#define CSC1_STOP_ACKR1_FLEXCAN6_SHIFT 24u
#define CSC1_STOP_ACKR1_FLEXCAN6_WIDTH 1u
#define CSC1_STOP_ACKR1_FLEXCAN6(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FLEXCAN6_SHIFT))&CSC1_STOP_ACKR1_FLEXCAN6_MASK)
#define CSC1_STOP_ACKR1_FLEXCAN5_MASK  0x800000u
#define CSC1_STOP_ACKR1_FLEXCAN5_SHIFT 23u
#define CSC1_STOP_ACKR1_FLEXCAN5_WIDTH 1u
#define CSC1_STOP_ACKR1_FLEXCAN5(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FLEXCAN5_SHIFT))&CSC1_STOP_ACKR1_FLEXCAN5_MASK)
#define CSC1_STOP_ACKR1_MSC0_MASK      0x200000u
#define CSC1_STOP_ACKR1_MSC0_SHIFT     21u
#define CSC1_STOP_ACKR1_MSC0_WIDTH     1u
#define CSC1_STOP_ACKR1_MSC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_MSC0_SHIFT))&CSC1_STOP_ACKR1_MSC0_MASK)
#define CSC1_STOP_ACKR1_FCSPI5_MASK    0x100000u
#define CSC1_STOP_ACKR1_FCSPI5_SHIFT   20u
#define CSC1_STOP_ACKR1_FCSPI5_WIDTH   1u
#define CSC1_STOP_ACKR1_FCSPI5(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FCSPI5_SHIFT))&CSC1_STOP_ACKR1_FCSPI5_MASK)
#define CSC1_STOP_ACKR1_FCSPI4_MASK    0x80000u
#define CSC1_STOP_ACKR1_FCSPI4_SHIFT   19u
#define CSC1_STOP_ACKR1_FCSPI4_WIDTH   1u
#define CSC1_STOP_ACKR1_FCSPI4(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FCSPI4_SHIFT))&CSC1_STOP_ACKR1_FCSPI4_MASK)
#define CSC1_STOP_ACKR1_FCIIC1_MASK    0x400u
#define CSC1_STOP_ACKR1_FCIIC1_SHIFT   10u
#define CSC1_STOP_ACKR1_FCIIC1_WIDTH   1u
#define CSC1_STOP_ACKR1_FCIIC1(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_FCIIC1_SHIFT))&CSC1_STOP_ACKR1_FCIIC1_MASK)
#define CSC1_STOP_ACKR1_SENT1_MASK     0x200u
#define CSC1_STOP_ACKR1_SENT1_SHIFT    9u
#define CSC1_STOP_ACKR1_SENT1_WIDTH    1u
#define CSC1_STOP_ACKR1_SENT1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_SENT1_SHIFT))&CSC1_STOP_ACKR1_SENT1_MASK)
#define CSC1_STOP_ACKR1_WDOG1_MASK     0x2u
#define CSC1_STOP_ACKR1_WDOG1_SHIFT    1u
#define CSC1_STOP_ACKR1_WDOG1_WIDTH    1u
#define CSC1_STOP_ACKR1_WDOG1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR1_WDOG1_SHIFT))&CSC1_STOP_ACKR1_WDOG1_MASK)
/* STOP_ACKR1 Reg Mask */
#define CSC1_STOP_ACKR1_MASK           0x03B80602u

/* STOP_MODER2 Bit Fields */
#define CSC1_STOP_MODER2_WPB_LOCK_MASK 0x80000000u
#define CSC1_STOP_MODER2_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_MODER2_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_MODER2_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_WPB_LOCK_SHIFT))&CSC1_STOP_MODER2_WPB_LOCK_MASK)
#define CSC1_STOP_MODER2_WPB_MASK      0x70000000u
#define CSC1_STOP_MODER2_WPB_SHIFT     28u
#define CSC1_STOP_MODER2_WPB_WIDTH     3u
#define CSC1_STOP_MODER2_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_WPB_SHIFT))&CSC1_STOP_MODER2_WPB_MASK)
#define CSC1_STOP_MODER2_FREQM_MASK    0x8000000u
#define CSC1_STOP_MODER2_FREQM_SHIFT   27u
#define CSC1_STOP_MODER2_FREQM_WIDTH   1u
#define CSC1_STOP_MODER2_FREQM(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_FREQM_SHIFT))&CSC1_STOP_MODER2_FREQM_MASK)
#define CSC1_STOP_MODER2_LDI0_MASK     0x2000000u
#define CSC1_STOP_MODER2_LDI0_SHIFT    25u
#define CSC1_STOP_MODER2_LDI0_WIDTH    1u
#define CSC1_STOP_MODER2_LDI0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_LDI0_SHIFT))&CSC1_STOP_MODER2_LDI0_MASK)
#define CSC1_STOP_MODER2_SSI0_MASK     0x1000000u
#define CSC1_STOP_MODER2_SSI0_SHIFT    24u
#define CSC1_STOP_MODER2_SSI0_WIDTH    1u
#define CSC1_STOP_MODER2_SSI0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_SSI0_SHIFT))&CSC1_STOP_MODER2_SSI0_MASK)
#define CSC1_STOP_MODER2_SDADC0_MASK   0x200000u
#define CSC1_STOP_MODER2_SDADC0_SHIFT  21u
#define CSC1_STOP_MODER2_SDADC0_WIDTH  1u
#define CSC1_STOP_MODER2_SDADC0(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_SDADC0_SHIFT))&CSC1_STOP_MODER2_SDADC0_MASK)
#define CSC1_STOP_MODER2_FCUART0_MASK  0x400u
#define CSC1_STOP_MODER2_FCUART0_SHIFT 10u
#define CSC1_STOP_MODER2_FCUART0_WIDTH 1u
#define CSC1_STOP_MODER2_FCUART0(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_FCUART0_SHIFT))&CSC1_STOP_MODER2_FCUART0_MASK)
#define CSC1_STOP_MODER2_FCIIC0_MASK   0x200u
#define CSC1_STOP_MODER2_FCIIC0_SHIFT  9u
#define CSC1_STOP_MODER2_FCIIC0_WIDTH  1u
#define CSC1_STOP_MODER2_FCIIC0(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_FCIIC0_SHIFT))&CSC1_STOP_MODER2_FCIIC0_MASK)
#define CSC1_STOP_MODER2_FCSPI0_MASK   0x100u
#define CSC1_STOP_MODER2_FCSPI0_SHIFT  8u
#define CSC1_STOP_MODER2_FCSPI0_WIDTH  1u
#define CSC1_STOP_MODER2_FCSPI0(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_FCSPI0_SHIFT))&CSC1_STOP_MODER2_FCSPI0_MASK)
#define CSC1_STOP_MODER2_CMU3_MASK     0x20u
#define CSC1_STOP_MODER2_CMU3_SHIFT    5u
#define CSC1_STOP_MODER2_CMU3_WIDTH    1u
#define CSC1_STOP_MODER2_CMU3(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_CMU3_SHIFT))&CSC1_STOP_MODER2_CMU3_MASK)
#define CSC1_STOP_MODER2_CMU2_MASK     0x10u
#define CSC1_STOP_MODER2_CMU2_SHIFT    4u
#define CSC1_STOP_MODER2_CMU2_WIDTH    1u
#define CSC1_STOP_MODER2_CMU2(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_CMU2_SHIFT))&CSC1_STOP_MODER2_CMU2_MASK)
#define CSC1_STOP_MODER2_CMU1_MASK     0x8u
#define CSC1_STOP_MODER2_CMU1_SHIFT    3u
#define CSC1_STOP_MODER2_CMU1_WIDTH    1u
#define CSC1_STOP_MODER2_CMU1(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_CMU1_SHIFT))&CSC1_STOP_MODER2_CMU1_MASK)
#define CSC1_STOP_MODER2_CMU0_MASK     0x4u
#define CSC1_STOP_MODER2_CMU0_SHIFT    2u
#define CSC1_STOP_MODER2_CMU0_WIDTH    1u
#define CSC1_STOP_MODER2_CMU0(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_MODER2_CMU0_SHIFT))&CSC1_STOP_MODER2_CMU0_MASK)
/* STOP_MODER2 Reg Mask */
#define CSC1_STOP_MODER2_MASK          0xFB20073Cu

/* STOP_REQR2 Bit Fields */
#define CSC1_STOP_REQR2_WPB_LOCK_MASK  0x80000000u
#define CSC1_STOP_REQR2_WPB_LOCK_SHIFT 31u
#define CSC1_STOP_REQR2_WPB_LOCK_WIDTH 1u
#define CSC1_STOP_REQR2_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_WPB_LOCK_SHIFT))&CSC1_STOP_REQR2_WPB_LOCK_MASK)
#define CSC1_STOP_REQR2_WPB_MASK       0x70000000u
#define CSC1_STOP_REQR2_WPB_SHIFT      28u
#define CSC1_STOP_REQR2_WPB_WIDTH      3u
#define CSC1_STOP_REQR2_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_WPB_SHIFT))&CSC1_STOP_REQR2_WPB_MASK)
#define CSC1_STOP_REQR2_FREQM_MASK     0x8000000u
#define CSC1_STOP_REQR2_FREQM_SHIFT    27u
#define CSC1_STOP_REQR2_FREQM_WIDTH    1u
#define CSC1_STOP_REQR2_FREQM(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_FREQM_SHIFT))&CSC1_STOP_REQR2_FREQM_MASK)
#define CSC1_STOP_REQR2_LDI0_MASK      0x2000000u
#define CSC1_STOP_REQR2_LDI0_SHIFT     25u
#define CSC1_STOP_REQR2_LDI0_WIDTH     1u
#define CSC1_STOP_REQR2_LDI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_LDI0_SHIFT))&CSC1_STOP_REQR2_LDI0_MASK)
#define CSC1_STOP_REQR2_SSI0_MASK      0x1000000u
#define CSC1_STOP_REQR2_SSI0_SHIFT     24u
#define CSC1_STOP_REQR2_SSI0_WIDTH     1u
#define CSC1_STOP_REQR2_SSI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_SSI0_SHIFT))&CSC1_STOP_REQR2_SSI0_MASK)
#define CSC1_STOP_REQR2_SDADC0_MASK    0x200000u
#define CSC1_STOP_REQR2_SDADC0_SHIFT   21u
#define CSC1_STOP_REQR2_SDADC0_WIDTH   1u
#define CSC1_STOP_REQR2_SDADC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_SDADC0_SHIFT))&CSC1_STOP_REQR2_SDADC0_MASK)
#define CSC1_STOP_REQR2_FCUART0_MASK   0x400u
#define CSC1_STOP_REQR2_FCUART0_SHIFT  10u
#define CSC1_STOP_REQR2_FCUART0_WIDTH  1u
#define CSC1_STOP_REQR2_FCUART0(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_FCUART0_SHIFT))&CSC1_STOP_REQR2_FCUART0_MASK)
#define CSC1_STOP_REQR2_FCIIC0_MASK    0x200u
#define CSC1_STOP_REQR2_FCIIC0_SHIFT   9u
#define CSC1_STOP_REQR2_FCIIC0_WIDTH   1u
#define CSC1_STOP_REQR2_FCIIC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_FCIIC0_SHIFT))&CSC1_STOP_REQR2_FCIIC0_MASK)
#define CSC1_STOP_REQR2_FCSPI0_MASK    0x100u
#define CSC1_STOP_REQR2_FCSPI0_SHIFT   8u
#define CSC1_STOP_REQR2_FCSPI0_WIDTH   1u
#define CSC1_STOP_REQR2_FCSPI0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_FCSPI0_SHIFT))&CSC1_STOP_REQR2_FCSPI0_MASK)
#define CSC1_STOP_REQR2_CMP0_MASK      0x40u
#define CSC1_STOP_REQR2_CMP0_SHIFT     6u
#define CSC1_STOP_REQR2_CMP0_WIDTH     1u
#define CSC1_STOP_REQR2_CMP0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_CMP0_SHIFT))&CSC1_STOP_REQR2_CMP0_MASK)
#define CSC1_STOP_REQR2_CMU3_MASK      0x20u
#define CSC1_STOP_REQR2_CMU3_SHIFT     5u
#define CSC1_STOP_REQR2_CMU3_WIDTH     1u
#define CSC1_STOP_REQR2_CMU3(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_CMU3_SHIFT))&CSC1_STOP_REQR2_CMU3_MASK)
#define CSC1_STOP_REQR2_CMU2_MASK      0x10u
#define CSC1_STOP_REQR2_CMU2_SHIFT     4u
#define CSC1_STOP_REQR2_CMU2_WIDTH     1u
#define CSC1_STOP_REQR2_CMU2(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_CMU2_SHIFT))&CSC1_STOP_REQR2_CMU2_MASK)
#define CSC1_STOP_REQR2_CMU1_MASK      0x8u
#define CSC1_STOP_REQR2_CMU1_SHIFT     3u
#define CSC1_STOP_REQR2_CMU1_WIDTH     1u
#define CSC1_STOP_REQR2_CMU1(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_CMU1_SHIFT))&CSC1_STOP_REQR2_CMU1_MASK)
#define CSC1_STOP_REQR2_CMU0_MASK      0x4u
#define CSC1_STOP_REQR2_CMU0_SHIFT     2u
#define CSC1_STOP_REQR2_CMU0_WIDTH     1u
#define CSC1_STOP_REQR2_CMU0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_REQR2_CMU0_SHIFT))&CSC1_STOP_REQR2_CMU0_MASK)
/* STOP_REQR2 Reg Mask */
#define CSC1_STOP_REQR2_MASK           0xFB20077Cu

/* STOP_ACKR2 Bit Fields */
#define CSC1_STOP_ACKR2_FREQM_MASK     0x8000000u
#define CSC1_STOP_ACKR2_FREQM_SHIFT    27u
#define CSC1_STOP_ACKR2_FREQM_WIDTH    1u
#define CSC1_STOP_ACKR2_FREQM(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_FREQM_SHIFT))&CSC1_STOP_ACKR2_FREQM_MASK)
#define CSC1_STOP_ACKR2_LDI0_MASK      0x2000000u
#define CSC1_STOP_ACKR2_LDI0_SHIFT     25u
#define CSC1_STOP_ACKR2_LDI0_WIDTH     1u
#define CSC1_STOP_ACKR2_LDI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_LDI0_SHIFT))&CSC1_STOP_ACKR2_LDI0_MASK)
#define CSC1_STOP_ACKR2_SSI0_MASK      0x1000000u
#define CSC1_STOP_ACKR2_SSI0_SHIFT     24u
#define CSC1_STOP_ACKR2_SSI0_WIDTH     1u
#define CSC1_STOP_ACKR2_SSI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_SSI0_SHIFT))&CSC1_STOP_ACKR2_SSI0_MASK)
#define CSC1_STOP_ACKR2_SDADC0_MASK    0x200000u
#define CSC1_STOP_ACKR2_SDADC0_SHIFT   21u
#define CSC1_STOP_ACKR2_SDADC0_WIDTH   1u
#define CSC1_STOP_ACKR2_SDADC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_SDADC0_SHIFT))&CSC1_STOP_ACKR2_SDADC0_MASK)
#define CSC1_STOP_ACKR2_FCUART0_MASK   0x400u
#define CSC1_STOP_ACKR2_FCUART0_SHIFT  10u
#define CSC1_STOP_ACKR2_FCUART0_WIDTH  1u
#define CSC1_STOP_ACKR2_FCUART0(x)     (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_FCUART0_SHIFT))&CSC1_STOP_ACKR2_FCUART0_MASK)
#define CSC1_STOP_ACKR2_FCIIC0_MASK    0x200u
#define CSC1_STOP_ACKR2_FCIIC0_SHIFT   9u
#define CSC1_STOP_ACKR2_FCIIC0_WIDTH   1u
#define CSC1_STOP_ACKR2_FCIIC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_FCIIC0_SHIFT))&CSC1_STOP_ACKR2_FCIIC0_MASK)
#define CSC1_STOP_ACKR2_FCSPI0_MASK    0x100u
#define CSC1_STOP_ACKR2_FCSPI0_SHIFT   8u
#define CSC1_STOP_ACKR2_FCSPI0_WIDTH   1u
#define CSC1_STOP_ACKR2_FCSPI0(x)      (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_FCSPI0_SHIFT))&CSC1_STOP_ACKR2_FCSPI0_MASK)
#define CSC1_STOP_ACKR2_CMU3_MASK      0x20u
#define CSC1_STOP_ACKR2_CMU3_SHIFT     5u
#define CSC1_STOP_ACKR2_CMU3_WIDTH     1u
#define CSC1_STOP_ACKR2_CMU3(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_CMU3_SHIFT))&CSC1_STOP_ACKR2_CMU3_MASK)
#define CSC1_STOP_ACKR2_CMU2_MASK      0x10u
#define CSC1_STOP_ACKR2_CMU2_SHIFT     4u
#define CSC1_STOP_ACKR2_CMU2_WIDTH     1u
#define CSC1_STOP_ACKR2_CMU2(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_CMU2_SHIFT))&CSC1_STOP_ACKR2_CMU2_MASK)
#define CSC1_STOP_ACKR2_CMU1_MASK      0x8u
#define CSC1_STOP_ACKR2_CMU1_SHIFT     3u
#define CSC1_STOP_ACKR2_CMU1_WIDTH     1u
#define CSC1_STOP_ACKR2_CMU1(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_CMU1_SHIFT))&CSC1_STOP_ACKR2_CMU1_MASK)
#define CSC1_STOP_ACKR2_CMU0_MASK      0x4u
#define CSC1_STOP_ACKR2_CMU0_SHIFT     2u
#define CSC1_STOP_ACKR2_CMU0_WIDTH     1u
#define CSC1_STOP_ACKR2_CMU0(x)        (((uint32_t)(((uint32_t)(x))<<CSC1_STOP_ACKR2_CMU0_SHIFT))&CSC1_STOP_ACKR2_CMU0_MASK)
/* STOP_ACKR2 Reg Mask */
#define CSC1_STOP_ACKR2_MASK           0x0B20073Cu

/* CCM_CFG Bit Fields */
#define CSC1_CCM_CFG_WPB_LOCK_MASK     0x80000000u
#define CSC1_CCM_CFG_WPB_LOCK_SHIFT    31u
#define CSC1_CCM_CFG_WPB_LOCK_WIDTH    1u
#define CSC1_CCM_CFG_WPB_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_CCM_CFG_WPB_LOCK_SHIFT))&CSC1_CCM_CFG_WPB_LOCK_MASK)
#define CSC1_CCM_CFG_WPB_MASK          0x70000000u
#define CSC1_CCM_CFG_WPB_SHIFT         28u
#define CSC1_CCM_CFG_WPB_WIDTH         3u
#define CSC1_CCM_CFG_WPB(x)            (((uint32_t)(((uint32_t)(x))<<CSC1_CCM_CFG_WPB_SHIFT))&CSC1_CCM_CFG_WPB_MASK)
#define CSC1_CCM_CFG_CPU1_FORCE_HCLKEN_MASK 0x4u
#define CSC1_CCM_CFG_CPU1_FORCE_HCLKEN_SHIFT 2u
#define CSC1_CCM_CFG_CPU1_FORCE_HCLKEN_WIDTH 1u
#define CSC1_CCM_CFG_CPU1_FORCE_HCLKEN(x) (((uint32_t)(((uint32_t)(x))<<CSC1_CCM_CFG_CPU1_FORCE_HCLKEN_SHIFT))&CSC1_CCM_CFG_CPU1_FORCE_HCLKEN_MASK)
#define CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE_MASK 0x3u
#define CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE_SHIFT 0u
#define CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE_WIDTH 2u
#define CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE(x) (((uint32_t)(((uint32_t)(x))<<CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE_SHIFT))&CSC1_CCM_CFG_CCM1_HANDSHAKE_MODE_MASK)
/* CCM_CFG Reg Mask */
#define CSC1_CCM_CFG_MASK              0xF0000007u

/* CPU_INT Bit Fields */
#define CSC1_CPU1_INT_WPB_LOCK_MASK     0x80000000u
#define CSC1_CPU1_INT_WPB_LOCK_SHIFT    31u
#define CSC1_CPU1_INT_WPB_LOCK_WIDTH    1u
#define CSC1_CPU1_INT_WPB_LOCK(x)       (((uint32_t)(((uint32_t)(x))<<CSC1_CPU_INT_WPB_LOCK_SHIFT))&CSC1_CPU_INT_WPB_LOCK_MASK)
#define CSC1_CPU1_INT_WPB_MASK          0x70000000u
#define CSC1_CPU1_INT_WPB_SHIFT         28u
#define CSC1_CPU1_INT_WPB_WIDTH         3u
#define CSC1_CPU1_INT_WPB(x)            (((uint32_t)(((uint32_t)(x))<<CSC1_CPU_INT_WPB_SHIFT))&CSC1_CPU_INT_WPB_MASK)
#define CSC1_CPU1_INT_SW_INT_MASK       0x1u
#define CSC1_CPU1_INT_SW_INT_SHIFT      0u
#define CSC1_CPU1_INT_SW_INT_WIDTH      1u
#define CSC1_CPU1_INT_SW_INT(x)         (((uint32_t)(((uint32_t)(x))<<CSC1_CPU_INT_SW_INT_SHIFT))&CSC1_CPU_INT_SW_INT_MASK)
/* CPU_INT Reg Mask */
#define CSC1_CPU_INT_MASK              0xF0000001u


/*!
 * @}
 */ /* end of group CSC1_Register_Masks */

/*!
 * @}
 */ /* end of group CSC1_Peripheral_Access_Layer */

#endif
