#ifndef _MODULE_CSC0_gmbhdijq145_REGS_H_CSC0_H_
#define _MODULE_CSC0_gmbhdijq145_REGS_H_CSC0_H_

/* ----------------------------------------------------------------------------
   -- CSC0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSC0_Peripheral_Access_Layer CSC0 Peripheral Access Layer
 * @{
 */

/** CSC0 - Size of Registers Arrays */

/** CSC0 - Register Layout Typedef */

typedef struct {

  __IO uint32_t STOP_MODER0                   ; /* STOP Mode Control Register 0, offset: 0x0 */
  __IO uint32_t STOP_REQR0                    ; /* STOP Request Register 0, offset: 0x4 */
  __I  uint32_t STOP_ACKR0                    ; /* STOP Acknowledge Register 0, offset: 0x8 */
  __IO uint32_t STOP_MODER1                   ; /* STOP Mode Control Register 1, offset: 0xC */
  __IO uint32_t STOP_REQR1                    ; /* STOP Request Register 1, offset: 0x10 */
  __I  uint32_t STOP_ACKR1                    ; /* STOP Acknowledge Register 1, offset: 0x14 */
  __IO uint32_t STOP_MODER2                   ; /* STOP Mode Control Register 2, offset: 0x18 */
  __IO uint32_t STOP_REQR2                    ; /* STOP Request Register2, offset: 0x1C */
  __I  uint32_t STOP_ACKR2                    ; /* STOP Acknowledge Register 2, offset: 0x20 */
  __IO uint32_t CCM0_CFG                      ; /* CCM0 Configuration Register, offset: 0x24 */
       uint8_t  RESERVED_0[4];
  __IO uint32_t SCG_MAM_STALL                 ; /* SCG MAM Stall Request Register, offset: 0x2C */
  __IO uint32_t CPU0_INT                      ; /* CPU0 Software Interrupt Register, offset: 0x30 */
       uint8_t  RESERVED_1[28];
  __IO uint32_t SMU_CTRL0                     ; /* FCSMU Control Register 0, offset: 0x50 */
  __IO uint32_t SMU_CTRL1                     ; /* FCSMU Control Register 1, offset: 0x54 */
  __IO uint32_t SMU_CTRL2                     ; /* FCSMU Control Register 2, offset: 0x58 */
       uint8_t  RESERVED_2[4];
  __IO uint32_t SMU_CTRL4                     ; /* FCSMU Control Register 4, offset: 0x60 */
  __IO uint32_t PERP_CTRL                     ; /* Peripheral Control Register, offset: 0x64 */
  __IO uint32_t SMU_CTRL5                     ; /* FCSMU Control Register 5, offset: 0x68 */
  __IO uint32_t SMU_CTRL6                     ; /* FCSMU Control Register 6, offset: 0x6C */
       uint8_t  RESERVED_3[12];
  __IO uint32_t SMU_CTRL8                     ; /* SMU_CTRL8, offset: 0x7C */
  __IO uint32_t PCC_CFG                       ; /* PCC_CFG, offset: 0x80 */

} CSC0_Type, *CSC0_MemMapPtr;


/* CSC0 - Peripheral instance base addresses */
/** Peripheral CSC0 base address */
#define CSC0_BASE                                (0x40079000u)
/** Peripheral CSC0 base pointer */
#define CSC0                                     ((CSC0_Type *)CSC0_BASE)
// need fill by yourself
///** Number of interrupt vector arrays for the CSC0 module. */
//#define CSC0_IRQS_ARR_COUNT                       (1u)
///** Number of interrupt channels for the CSC0 module. */
//#define CSC0_IRQS_CH_COUNT                        (1u)
///** Interrupt vectors for the CSC0 peripheral type */
//#define CSC0_IRQS                                {CSC0_IRQn}


/* ----------------------------------------------------------------------------
   -- CSC0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSC0_Register_Masks CSC0 Register Masks
 * @{
 */

/* STOP_MODER0 Bit Fields */
#define CSC0_STOP_MODER0_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER0_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER0_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER0_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WPB_LOCK_SHIFT))&CSC0_STOP_MODER0_WPB_LOCK_MASK)
#define CSC0_STOP_MODER0_WPB_MASK      0x70000000u
#define CSC0_STOP_MODER0_WPB_SHIFT     28u
#define CSC0_STOP_MODER0_WPB_WIDTH     3u
#define CSC0_STOP_MODER0_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WPB_SHIFT))&CSC0_STOP_MODER0_WPB_MASK)
#define CSC0_STOP_MODER0_ADC3_MASK     0x8000000u
#define CSC0_STOP_MODER0_ADC3_SHIFT    27u
#define CSC0_STOP_MODER0_ADC3_WIDTH    1u
#define CSC0_STOP_MODER0_ADC3(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC3_SHIFT))&CSC0_STOP_MODER0_ADC3_MASK)
#define CSC0_STOP_MODER0_ADC2_MASK     0x4000000u
#define CSC0_STOP_MODER0_ADC2_SHIFT    26u
#define CSC0_STOP_MODER0_ADC2_WIDTH    1u
#define CSC0_STOP_MODER0_ADC2(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC2_SHIFT))&CSC0_STOP_MODER0_ADC2_MASK)
#define CSC0_STOP_MODER0_FLEXCAN4_MASK 0x2000000u
#define CSC0_STOP_MODER0_FLEXCAN4_SHIFT 25u
#define CSC0_STOP_MODER0_FLEXCAN4_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN4(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN4_SHIFT))&CSC0_STOP_MODER0_FLEXCAN4_MASK)
#define CSC0_STOP_MODER0_FLEXCAN3_MASK 0x1000000u
#define CSC0_STOP_MODER0_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_MODER0_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN3(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN3_SHIFT))&CSC0_STOP_MODER0_FLEXCAN3_MASK)
#define CSC0_STOP_MODER0_FLEXCAN2_MASK 0x800000u
#define CSC0_STOP_MODER0_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_MODER0_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN2(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN2_SHIFT))&CSC0_STOP_MODER0_FLEXCAN2_MASK)
#define CSC0_STOP_MODER0_FLEXCAN1_MASK 0x400000u
#define CSC0_STOP_MODER0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_MODER0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN1_SHIFT))&CSC0_STOP_MODER0_FLEXCAN1_MASK)
#define CSC0_STOP_MODER0_FLEXCAN0_MASK 0x200000u
#define CSC0_STOP_MODER0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_MODER0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN0_SHIFT))&CSC0_STOP_MODER0_FLEXCAN0_MASK)
#define CSC0_STOP_MODER0_FCUART7_MASK  0x100000u
#define CSC0_STOP_MODER0_FCUART7_SHIFT 20u
#define CSC0_STOP_MODER0_FCUART7_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART7(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART7_SHIFT))&CSC0_STOP_MODER0_FCUART7_MASK)
#define CSC0_STOP_MODER0_FCUART6_MASK  0x80000u
#define CSC0_STOP_MODER0_FCUART6_SHIFT 19u
#define CSC0_STOP_MODER0_FCUART6_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART6(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART6_SHIFT))&CSC0_STOP_MODER0_FCUART6_MASK)
#define CSC0_STOP_MODER0_FCUART5_MASK  0x40000u
#define CSC0_STOP_MODER0_FCUART5_SHIFT 18u
#define CSC0_STOP_MODER0_FCUART5_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART5(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART5_SHIFT))&CSC0_STOP_MODER0_FCUART5_MASK)
#define CSC0_STOP_MODER0_FCUART4_MASK  0x20000u
#define CSC0_STOP_MODER0_FCUART4_SHIFT 17u
#define CSC0_STOP_MODER0_FCUART4_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART4(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART4_SHIFT))&CSC0_STOP_MODER0_FCUART4_MASK)
#define CSC0_STOP_MODER0_FCUART3_MASK  0x10000u
#define CSC0_STOP_MODER0_FCUART3_SHIFT 16u
#define CSC0_STOP_MODER0_FCUART3_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART3(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART3_SHIFT))&CSC0_STOP_MODER0_FCUART3_MASK)
#define CSC0_STOP_MODER0_FCUART2_MASK  0x8000u
#define CSC0_STOP_MODER0_FCUART2_SHIFT 15u
#define CSC0_STOP_MODER0_FCUART2_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART2(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART2_SHIFT))&CSC0_STOP_MODER0_FCUART2_MASK)
#define CSC0_STOP_MODER0_FCUART1_MASK  0x4000u
#define CSC0_STOP_MODER0_FCUART1_SHIFT 14u
#define CSC0_STOP_MODER0_FCUART1_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART1(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART1_SHIFT))&CSC0_STOP_MODER0_FCUART1_MASK)
#define CSC0_STOP_MODER0_FCSPI3_MASK   0x2000u
#define CSC0_STOP_MODER0_FCSPI3_SHIFT  13u
#define CSC0_STOP_MODER0_FCSPI3_WIDTH  1u
#define CSC0_STOP_MODER0_FCSPI3(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCSPI3_SHIFT))&CSC0_STOP_MODER0_FCSPI3_MASK)
#define CSC0_STOP_MODER0_FCSPI2_MASK   0x1000u
#define CSC0_STOP_MODER0_FCSPI2_SHIFT  12u
#define CSC0_STOP_MODER0_FCSPI2_WIDTH  1u
#define CSC0_STOP_MODER0_FCSPI2(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCSPI2_SHIFT))&CSC0_STOP_MODER0_FCSPI2_MASK)
#define CSC0_STOP_MODER0_FCSPI1_MASK   0x800u
#define CSC0_STOP_MODER0_FCSPI1_SHIFT  11u
#define CSC0_STOP_MODER0_FCSPI1_WIDTH  1u
#define CSC0_STOP_MODER0_FCSPI1(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCSPI1_SHIFT))&CSC0_STOP_MODER0_FCSPI1_MASK)
#define CSC0_STOP_MODER0_SENT0_MASK    0x400u
#define CSC0_STOP_MODER0_SENT0_SHIFT   10u
#define CSC0_STOP_MODER0_SENT0_WIDTH   1u
#define CSC0_STOP_MODER0_SENT0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_SENT0_SHIFT))&CSC0_STOP_MODER0_SENT0_MASK)
#define CSC0_STOP_MODER0_TMU_MASK      0x200u
#define CSC0_STOP_MODER0_TMU_SHIFT     9u
#define CSC0_STOP_MODER0_TMU_WIDTH     1u
#define CSC0_STOP_MODER0_TMU(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_TMU_SHIFT))&CSC0_STOP_MODER0_TMU_MASK)
#define CSC0_STOP_MODER0_ADC1_MASK     0x80u
#define CSC0_STOP_MODER0_ADC1_SHIFT    7u
#define CSC0_STOP_MODER0_ADC1_WIDTH    1u
#define CSC0_STOP_MODER0_ADC1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC1_SHIFT))&CSC0_STOP_MODER0_ADC1_MASK)
#define CSC0_STOP_MODER0_ADC0_MASK     0x40u
#define CSC0_STOP_MODER0_ADC0_SHIFT    6u
#define CSC0_STOP_MODER0_ADC0_WIDTH    1u
#define CSC0_STOP_MODER0_ADC0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC0_SHIFT))&CSC0_STOP_MODER0_ADC0_MASK)
#define CSC0_STOP_MODER0_CMU4_MASK     0x20u
#define CSC0_STOP_MODER0_CMU4_SHIFT    5u
#define CSC0_STOP_MODER0_CMU4_WIDTH    1u
#define CSC0_STOP_MODER0_CMU4(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_CMU4_SHIFT))&CSC0_STOP_MODER0_CMU4_MASK)
#define CSC0_STOP_MODER0_WDOG0_MASK    0x10u
#define CSC0_STOP_MODER0_WDOG0_SHIFT   4u
#define CSC0_STOP_MODER0_WDOG0_WIDTH   1u
#define CSC0_STOP_MODER0_WDOG0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WDOG0_SHIFT))&CSC0_STOP_MODER0_WDOG0_MASK)
#define CSC0_STOP_MODER0_ISM0_MASK     0x2u
#define CSC0_STOP_MODER0_ISM0_SHIFT    1u
#define CSC0_STOP_MODER0_ISM0_WIDTH    1u
#define CSC0_STOP_MODER0_ISM0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ISM0_SHIFT))&CSC0_STOP_MODER0_ISM0_MASK)
#define CSC0_STOP_MODER0_DMA0_MASK     0x1u
#define CSC0_STOP_MODER0_DMA0_SHIFT    0u
#define CSC0_STOP_MODER0_DMA0_WIDTH    1u
#define CSC0_STOP_MODER0_DMA0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_DMA0_SHIFT))&CSC0_STOP_MODER0_DMA0_MASK)
/* STOP_MODER0 Reg Mask */
#define CSC0_STOP_MODER0_MASK          0xFFFFFEF3u

/* STOP_REQR0 Bit Fields */
#define CSC0_STOP_REQR0_WPB_LOCK_MASK  0x80000000u
#define CSC0_STOP_REQR0_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR0_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR0_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WPB_LOCK_SHIFT))&CSC0_STOP_REQR0_WPB_LOCK_MASK)
#define CSC0_STOP_REQR0_WPB_MASK       0x70000000u
#define CSC0_STOP_REQR0_WPB_SHIFT      28u
#define CSC0_STOP_REQR0_WPB_WIDTH      3u
#define CSC0_STOP_REQR0_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WPB_SHIFT))&CSC0_STOP_REQR0_WPB_MASK)
#define CSC0_STOP_REQR0_ADC3_MASK      0x8000000u
#define CSC0_STOP_REQR0_ADC3_SHIFT     27u
#define CSC0_STOP_REQR0_ADC3_WIDTH     1u
#define CSC0_STOP_REQR0_ADC3(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC3_SHIFT))&CSC0_STOP_REQR0_ADC3_MASK)
#define CSC0_STOP_REQR0_ADC2_MASK      0x4000000u
#define CSC0_STOP_REQR0_ADC2_SHIFT     26u
#define CSC0_STOP_REQR0_ADC2_WIDTH     1u
#define CSC0_STOP_REQR0_ADC2(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC2_SHIFT))&CSC0_STOP_REQR0_ADC2_MASK)
#define CSC0_STOP_REQR0_FLEXCAN4_MASK  0x2000000u
#define CSC0_STOP_REQR0_FLEXCAN4_SHIFT 25u
#define CSC0_STOP_REQR0_FLEXCAN4_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN4(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN4_SHIFT))&CSC0_STOP_REQR0_FLEXCAN4_MASK)
#define CSC0_STOP_REQR0_FLEXCAN3_MASK  0x1000000u
#define CSC0_STOP_REQR0_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_REQR0_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN3(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN3_SHIFT))&CSC0_STOP_REQR0_FLEXCAN3_MASK)
#define CSC0_STOP_REQR0_FLEXCAN2_MASK  0x800000u
#define CSC0_STOP_REQR0_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_REQR0_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN2(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN2_SHIFT))&CSC0_STOP_REQR0_FLEXCAN2_MASK)
#define CSC0_STOP_REQR0_FLEXCAN1_MASK  0x400000u
#define CSC0_STOP_REQR0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_REQR0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN1(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN1_SHIFT))&CSC0_STOP_REQR0_FLEXCAN1_MASK)
#define CSC0_STOP_REQR0_FLEXCAN0_MASK  0x200000u
#define CSC0_STOP_REQR0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_REQR0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN0(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN0_SHIFT))&CSC0_STOP_REQR0_FLEXCAN0_MASK)
#define CSC0_STOP_REQR0_FCUART7_MASK   0x100000u
#define CSC0_STOP_REQR0_FCUART7_SHIFT  20u
#define CSC0_STOP_REQR0_FCUART7_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART7(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART7_SHIFT))&CSC0_STOP_REQR0_FCUART7_MASK)
#define CSC0_STOP_REQR0_FCUART6_MASK   0x80000u
#define CSC0_STOP_REQR0_FCUART6_SHIFT  19u
#define CSC0_STOP_REQR0_FCUART6_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART6(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART6_SHIFT))&CSC0_STOP_REQR0_FCUART6_MASK)
#define CSC0_STOP_REQR0_FCUART5_MASK   0x40000u
#define CSC0_STOP_REQR0_FCUART5_SHIFT  18u
#define CSC0_STOP_REQR0_FCUART5_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART5(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART5_SHIFT))&CSC0_STOP_REQR0_FCUART5_MASK)
#define CSC0_STOP_REQR0_FCUART4_MASK   0x20000u
#define CSC0_STOP_REQR0_FCUART4_SHIFT  17u
#define CSC0_STOP_REQR0_FCUART4_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART4(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART4_SHIFT))&CSC0_STOP_REQR0_FCUART4_MASK)
#define CSC0_STOP_REQR0_FCUART3_MASK   0x10000u
#define CSC0_STOP_REQR0_FCUART3_SHIFT  16u
#define CSC0_STOP_REQR0_FCUART3_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART3(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART3_SHIFT))&CSC0_STOP_REQR0_FCUART3_MASK)
#define CSC0_STOP_REQR0_FCUART2_MASK   0x8000u
#define CSC0_STOP_REQR0_FCUART2_SHIFT  15u
#define CSC0_STOP_REQR0_FCUART2_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART2(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART2_SHIFT))&CSC0_STOP_REQR0_FCUART2_MASK)
#define CSC0_STOP_REQR0_FCUART1_MASK   0x4000u
#define CSC0_STOP_REQR0_FCUART1_SHIFT  14u
#define CSC0_STOP_REQR0_FCUART1_WIDTH  1u
#define CSC0_STOP_REQR0_FCUART1(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART1_SHIFT))&CSC0_STOP_REQR0_FCUART1_MASK)
#define CSC0_STOP_REQR0_FCSPI3_MASK    0x2000u
#define CSC0_STOP_REQR0_FCSPI3_SHIFT   13u
#define CSC0_STOP_REQR0_FCSPI3_WIDTH   1u
#define CSC0_STOP_REQR0_FCSPI3(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCSPI3_SHIFT))&CSC0_STOP_REQR0_FCSPI3_MASK)
#define CSC0_STOP_REQR0_FCSPI2_MASK    0x1000u
#define CSC0_STOP_REQR0_FCSPI2_SHIFT   12u
#define CSC0_STOP_REQR0_FCSPI2_WIDTH   1u
#define CSC0_STOP_REQR0_FCSPI2(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCSPI2_SHIFT))&CSC0_STOP_REQR0_FCSPI2_MASK)
#define CSC0_STOP_REQR0_FCSPI1_MASK    0x800u
#define CSC0_STOP_REQR0_FCSPI1_SHIFT   11u
#define CSC0_STOP_REQR0_FCSPI1_WIDTH   1u
#define CSC0_STOP_REQR0_FCSPI1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCSPI1_SHIFT))&CSC0_STOP_REQR0_FCSPI1_MASK)
#define CSC0_STOP_REQR0_SENT0_MASK     0x400u
#define CSC0_STOP_REQR0_SENT0_SHIFT    10u
#define CSC0_STOP_REQR0_SENT0_WIDTH    1u
#define CSC0_STOP_REQR0_SENT0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_SENT0_SHIFT))&CSC0_STOP_REQR0_SENT0_MASK)
#define CSC0_STOP_REQR0_TMU_MASK       0x200u
#define CSC0_STOP_REQR0_TMU_SHIFT      9u
#define CSC0_STOP_REQR0_TMU_WIDTH      1u
#define CSC0_STOP_REQR0_TMU(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_TMU_SHIFT))&CSC0_STOP_REQR0_TMU_MASK)
#define CSC0_STOP_REQR0_ADC1_MASK      0x80u
#define CSC0_STOP_REQR0_ADC1_SHIFT     7u
#define CSC0_STOP_REQR0_ADC1_WIDTH     1u
#define CSC0_STOP_REQR0_ADC1(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC1_SHIFT))&CSC0_STOP_REQR0_ADC1_MASK)
#define CSC0_STOP_REQR0_ADC0_MASK      0x40u
#define CSC0_STOP_REQR0_ADC0_SHIFT     6u
#define CSC0_STOP_REQR0_ADC0_WIDTH     1u
#define CSC0_STOP_REQR0_ADC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC0_SHIFT))&CSC0_STOP_REQR0_ADC0_MASK)
#define CSC0_STOP_REQR0_CMU4_MASK      0x20u
#define CSC0_STOP_REQR0_CMU4_SHIFT     5u
#define CSC0_STOP_REQR0_CMU4_WIDTH     1u
#define CSC0_STOP_REQR0_CMU4(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_CMU4_SHIFT))&CSC0_STOP_REQR0_CMU4_MASK)
#define CSC0_STOP_REQR0_WDOG0_MASK     0x10u
#define CSC0_STOP_REQR0_WDOG0_SHIFT    4u
#define CSC0_STOP_REQR0_WDOG0_WIDTH    1u
#define CSC0_STOP_REQR0_WDOG0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WDOG0_SHIFT))&CSC0_STOP_REQR0_WDOG0_MASK)
#define CSC0_STOP_REQR0_FLASH_MASK     0x4u
#define CSC0_STOP_REQR0_FLASH_SHIFT    2u
#define CSC0_STOP_REQR0_FLASH_WIDTH    1u
#define CSC0_STOP_REQR0_FLASH(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLASH_SHIFT))&CSC0_STOP_REQR0_FLASH_MASK)
#define CSC0_STOP_REQR0_ISM0_MASK      0x2u
#define CSC0_STOP_REQR0_ISM0_SHIFT     1u
#define CSC0_STOP_REQR0_ISM0_WIDTH     1u
#define CSC0_STOP_REQR0_ISM0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ISM0_SHIFT))&CSC0_STOP_REQR0_ISM0_MASK)
#define CSC0_STOP_REQR0_DMA0_MASK      0x1u
#define CSC0_STOP_REQR0_DMA0_SHIFT     0u
#define CSC0_STOP_REQR0_DMA0_WIDTH     1u
#define CSC0_STOP_REQR0_DMA0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_DMA0_SHIFT))&CSC0_STOP_REQR0_DMA0_MASK)
/* STOP_REQR0 Reg Mask */
#define CSC0_STOP_REQR0_MASK           0xFFFFFEF7u

/* STOP_ACKR0 Bit Fields */
#define CSC0_STOP_ACKR0_ADC3_MASK      0x8000000u
#define CSC0_STOP_ACKR0_ADC3_SHIFT     27u
#define CSC0_STOP_ACKR0_ADC3_WIDTH     1u
#define CSC0_STOP_ACKR0_ADC3(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC3_SHIFT))&CSC0_STOP_ACKR0_ADC3_MASK)
#define CSC0_STOP_ACKR0_ADC2_MASK      0x4000000u
#define CSC0_STOP_ACKR0_ADC2_SHIFT     26u
#define CSC0_STOP_ACKR0_ADC2_WIDTH     1u
#define CSC0_STOP_ACKR0_ADC2(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC2_SHIFT))&CSC0_STOP_ACKR0_ADC2_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN4_MASK  0x2000000u
#define CSC0_STOP_ACKR0_FLEXCAN4_SHIFT 25u
#define CSC0_STOP_ACKR0_FLEXCAN4_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN4(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN4_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN4_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN3_MASK  0x1000000u
#define CSC0_STOP_ACKR0_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_ACKR0_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN3(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN3_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN3_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN2_MASK  0x800000u
#define CSC0_STOP_ACKR0_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_ACKR0_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN2(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN2_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN2_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN1_MASK  0x400000u
#define CSC0_STOP_ACKR0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_ACKR0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN1(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN1_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN1_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN0_MASK  0x200000u
#define CSC0_STOP_ACKR0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_ACKR0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN0(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN0_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN0_MASK)
#define CSC0_STOP_ACKR0_FCUART7_MASK   0x100000u
#define CSC0_STOP_ACKR0_FCUART7_SHIFT  20u
#define CSC0_STOP_ACKR0_FCUART7_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART7(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART7_SHIFT))&CSC0_STOP_ACKR0_FCUART7_MASK)
#define CSC0_STOP_ACKR0_FCUART6_MASK   0x80000u
#define CSC0_STOP_ACKR0_FCUART6_SHIFT  19u
#define CSC0_STOP_ACKR0_FCUART6_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART6(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART6_SHIFT))&CSC0_STOP_ACKR0_FCUART6_MASK)
#define CSC0_STOP_ACKR0_FCUART5_MASK   0x40000u
#define CSC0_STOP_ACKR0_FCUART5_SHIFT  18u
#define CSC0_STOP_ACKR0_FCUART5_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART5(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART5_SHIFT))&CSC0_STOP_ACKR0_FCUART5_MASK)
#define CSC0_STOP_ACKR0_FCUART4_MASK   0x20000u
#define CSC0_STOP_ACKR0_FCUART4_SHIFT  17u
#define CSC0_STOP_ACKR0_FCUART4_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART4(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART4_SHIFT))&CSC0_STOP_ACKR0_FCUART4_MASK)
#define CSC0_STOP_ACKR0_FCUART3_MASK   0x10000u
#define CSC0_STOP_ACKR0_FCUART3_SHIFT  16u
#define CSC0_STOP_ACKR0_FCUART3_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART3(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART3_SHIFT))&CSC0_STOP_ACKR0_FCUART3_MASK)
#define CSC0_STOP_ACKR0_FCUART2_MASK   0x8000u
#define CSC0_STOP_ACKR0_FCUART2_SHIFT  15u
#define CSC0_STOP_ACKR0_FCUART2_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART2(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART2_SHIFT))&CSC0_STOP_ACKR0_FCUART2_MASK)
#define CSC0_STOP_ACKR0_FCUART1_MASK   0x4000u
#define CSC0_STOP_ACKR0_FCUART1_SHIFT  14u
#define CSC0_STOP_ACKR0_FCUART1_WIDTH  1u
#define CSC0_STOP_ACKR0_FCUART1(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART1_SHIFT))&CSC0_STOP_ACKR0_FCUART1_MASK)
#define CSC0_STOP_ACKR0_FCSPI3_MASK    0x2000u
#define CSC0_STOP_ACKR0_FCSPI3_SHIFT   13u
#define CSC0_STOP_ACKR0_FCSPI3_WIDTH   1u
#define CSC0_STOP_ACKR0_FCSPI3(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCSPI3_SHIFT))&CSC0_STOP_ACKR0_FCSPI3_MASK)
#define CSC0_STOP_ACKR0_FCSPI2_MASK    0x1000u
#define CSC0_STOP_ACKR0_FCSPI2_SHIFT   12u
#define CSC0_STOP_ACKR0_FCSPI2_WIDTH   1u
#define CSC0_STOP_ACKR0_FCSPI2(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCSPI2_SHIFT))&CSC0_STOP_ACKR0_FCSPI2_MASK)
#define CSC0_STOP_ACKR0_FCSPI1_MASK    0x800u
#define CSC0_STOP_ACKR0_FCSPI1_SHIFT   11u
#define CSC0_STOP_ACKR0_FCSPI1_WIDTH   1u
#define CSC0_STOP_ACKR0_FCSPI1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCSPI1_SHIFT))&CSC0_STOP_ACKR0_FCSPI1_MASK)
#define CSC0_STOP_ACKR0_SENT0_MASK     0x400u
#define CSC0_STOP_ACKR0_SENT0_SHIFT    10u
#define CSC0_STOP_ACKR0_SENT0_WIDTH    1u
#define CSC0_STOP_ACKR0_SENT0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_SENT0_SHIFT))&CSC0_STOP_ACKR0_SENT0_MASK)
#define CSC0_STOP_ACKR0_TMU0_MASK      0x200u
#define CSC0_STOP_ACKR0_TMU0_SHIFT     9u
#define CSC0_STOP_ACKR0_TMU0_WIDTH     1u
#define CSC0_STOP_ACKR0_TMU0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_TMU0_SHIFT))&CSC0_STOP_ACKR0_TMU0_MASK)
#define CSC0_STOP_ACKR0_ADC1_MASK      0x80u
#define CSC0_STOP_ACKR0_ADC1_SHIFT     7u
#define CSC0_STOP_ACKR0_ADC1_WIDTH     1u
#define CSC0_STOP_ACKR0_ADC1(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC1_SHIFT))&CSC0_STOP_ACKR0_ADC1_MASK)
#define CSC0_STOP_ACKR0_ADC0_MASK      0x40u
#define CSC0_STOP_ACKR0_ADC0_SHIFT     6u
#define CSC0_STOP_ACKR0_ADC0_WIDTH     1u
#define CSC0_STOP_ACKR0_ADC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC0_SHIFT))&CSC0_STOP_ACKR0_ADC0_MASK)
#define CSC0_STOP_ACKR0_CMU4_MASK      0x20u
#define CSC0_STOP_ACKR0_CMU4_SHIFT     5u
#define CSC0_STOP_ACKR0_CMU4_WIDTH     1u
#define CSC0_STOP_ACKR0_CMU4(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_CMU4_SHIFT))&CSC0_STOP_ACKR0_CMU4_MASK)
#define CSC0_STOP_ACKR0_WDOG0_MASK     0x10u
#define CSC0_STOP_ACKR0_WDOG0_SHIFT    4u
#define CSC0_STOP_ACKR0_WDOG0_WIDTH    1u
#define CSC0_STOP_ACKR0_WDOG0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_WDOG0_SHIFT))&CSC0_STOP_ACKR0_WDOG0_MASK)
#define CSC0_STOP_ACKR0_FLASH_MASK     0x4u
#define CSC0_STOP_ACKR0_FLASH_SHIFT    2u
#define CSC0_STOP_ACKR0_FLASH_WIDTH    1u
#define CSC0_STOP_ACKR0_FLASH(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLASH_SHIFT))&CSC0_STOP_ACKR0_FLASH_MASK)
#define CSC0_STOP_ACKR0_ISM0_MASK      0x2u
#define CSC0_STOP_ACKR0_ISM0_SHIFT     1u
#define CSC0_STOP_ACKR0_ISM0_WIDTH     1u
#define CSC0_STOP_ACKR0_ISM0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ISM0_SHIFT))&CSC0_STOP_ACKR0_ISM0_MASK)
#define CSC0_STOP_ACKR0_DMA0_MASK      0x1u
#define CSC0_STOP_ACKR0_DMA0_SHIFT     0u
#define CSC0_STOP_ACKR0_DMA0_WIDTH     1u
#define CSC0_STOP_ACKR0_DMA0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_DMA0_SHIFT))&CSC0_STOP_ACKR0_DMA0_MASK)
/* STOP_ACKR0 Reg Mask */
#define CSC0_STOP_ACKR0_MASK           0x0FFFFEF7u

/* STOP_MODER1 Bit Fields */
#define CSC0_STOP_MODER1_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER1_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER1_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER1_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WPB_LOCK_SHIFT))&CSC0_STOP_MODER1_WPB_LOCK_MASK)
#define CSC0_STOP_MODER1_WPB_MASK      0x70000000u
#define CSC0_STOP_MODER1_WPB_SHIFT     28u
#define CSC0_STOP_MODER1_WPB_WIDTH     3u
#define CSC0_STOP_MODER1_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WPB_SHIFT))&CSC0_STOP_MODER1_WPB_MASK)
#define CSC0_STOP_MODER1_FLEXCAN7_MASK 0x2000000u
#define CSC0_STOP_MODER1_FLEXCAN7_SHIFT 25u
#define CSC0_STOP_MODER1_FLEXCAN7_WIDTH 1u
#define CSC0_STOP_MODER1_FLEXCAN7(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FLEXCAN7_SHIFT))&CSC0_STOP_MODER1_FLEXCAN7_MASK)
#define CSC0_STOP_MODER1_FLEXCAN6_MASK 0x1000000u
#define CSC0_STOP_MODER1_FLEXCAN6_SHIFT 24u
#define CSC0_STOP_MODER1_FLEXCAN6_WIDTH 1u
#define CSC0_STOP_MODER1_FLEXCAN6(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FLEXCAN6_SHIFT))&CSC0_STOP_MODER1_FLEXCAN6_MASK)
#define CSC0_STOP_MODER1_FLEXCAN5_MASK 0x800000u
#define CSC0_STOP_MODER1_FLEXCAN5_SHIFT 23u
#define CSC0_STOP_MODER1_FLEXCAN5_WIDTH 1u
#define CSC0_STOP_MODER1_FLEXCAN5(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FLEXCAN5_SHIFT))&CSC0_STOP_MODER1_FLEXCAN5_MASK)
#define CSC0_STOP_MODER1_MSC0_MASK     0x200000u
#define CSC0_STOP_MODER1_MSC0_SHIFT    21u
#define CSC0_STOP_MODER1_MSC0_WIDTH    1u
#define CSC0_STOP_MODER1_MSC0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_MSC0_SHIFT))&CSC0_STOP_MODER1_MSC0_MASK)
#define CSC0_STOP_MODER1_FCSPI5_MASK   0x100000u
#define CSC0_STOP_MODER1_FCSPI5_SHIFT  20u
#define CSC0_STOP_MODER1_FCSPI5_WIDTH  1u
#define CSC0_STOP_MODER1_FCSPI5(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCSPI5_SHIFT))&CSC0_STOP_MODER1_FCSPI5_MASK)
#define CSC0_STOP_MODER1_FCSPI4_MASK   0x80000u
#define CSC0_STOP_MODER1_FCSPI4_SHIFT  19u
#define CSC0_STOP_MODER1_FCSPI4_WIDTH  1u
#define CSC0_STOP_MODER1_FCSPI4(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCSPI4_SHIFT))&CSC0_STOP_MODER1_FCSPI4_MASK)
#define CSC0_STOP_MODER1_FCIIC1_MASK   0x400u
#define CSC0_STOP_MODER1_FCIIC1_SHIFT  10u
#define CSC0_STOP_MODER1_FCIIC1_WIDTH  1u
#define CSC0_STOP_MODER1_FCIIC1(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCIIC1_SHIFT))&CSC0_STOP_MODER1_FCIIC1_MASK)
#define CSC0_STOP_MODER1_SENT1_MASK    0x200u
#define CSC0_STOP_MODER1_SENT1_SHIFT   9u
#define CSC0_STOP_MODER1_SENT1_WIDTH   1u
#define CSC0_STOP_MODER1_SENT1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_SENT1_SHIFT))&CSC0_STOP_MODER1_SENT1_MASK)
#define CSC0_STOP_MODER1_WDOG1_MASK    0x2u
#define CSC0_STOP_MODER1_WDOG1_SHIFT   1u
#define CSC0_STOP_MODER1_WDOG1_WIDTH   1u
#define CSC0_STOP_MODER1_WDOG1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WDOG1_SHIFT))&CSC0_STOP_MODER1_WDOG1_MASK)
/* STOP_MODER1 Reg Mask */
#define CSC0_STOP_MODER1_MASK          0xF3B80602u

/* STOP_REQR1 Bit Fields */
#define CSC0_STOP_REQR1_WPB_LOCK_MASK  0x80000000u
#define CSC0_STOP_REQR1_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR1_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR1_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WPB_LOCK_SHIFT))&CSC0_STOP_REQR1_WPB_LOCK_MASK)
#define CSC0_STOP_REQR1_WPB_MASK       0x70000000u
#define CSC0_STOP_REQR1_WPB_SHIFT      28u
#define CSC0_STOP_REQR1_WPB_WIDTH      3u
#define CSC0_STOP_REQR1_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WPB_SHIFT))&CSC0_STOP_REQR1_WPB_MASK)
#define CSC0_STOP_REQR1_FLEXCAN7_MASK  0x2000000u
#define CSC0_STOP_REQR1_FLEXCAN7_SHIFT 25u
#define CSC0_STOP_REQR1_FLEXCAN7_WIDTH 1u
#define CSC0_STOP_REQR1_FLEXCAN7(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FLEXCAN7_SHIFT))&CSC0_STOP_REQR1_FLEXCAN7_MASK)
#define CSC0_STOP_REQR1_FLEXCAN6_MASK  0x1000000u
#define CSC0_STOP_REQR1_FLEXCAN6_SHIFT 24u
#define CSC0_STOP_REQR1_FLEXCAN6_WIDTH 1u
#define CSC0_STOP_REQR1_FLEXCAN6(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FLEXCAN6_SHIFT))&CSC0_STOP_REQR1_FLEXCAN6_MASK)
#define CSC0_STOP_REQR1_FLEXCAN5_MASK  0x800000u
#define CSC0_STOP_REQR1_FLEXCAN5_SHIFT 23u
#define CSC0_STOP_REQR1_FLEXCAN5_WIDTH 1u
#define CSC0_STOP_REQR1_FLEXCAN5(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FLEXCAN5_SHIFT))&CSC0_STOP_REQR1_FLEXCAN5_MASK)
#define CSC0_STOP_REQR1_MSC0_MASK      0x200000u
#define CSC0_STOP_REQR1_MSC0_SHIFT     21u
#define CSC0_STOP_REQR1_MSC0_WIDTH     1u
#define CSC0_STOP_REQR1_MSC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_MSC0_SHIFT))&CSC0_STOP_REQR1_MSC0_MASK)
#define CSC0_STOP_REQR1_FCSPI5_MASK    0x100000u
#define CSC0_STOP_REQR1_FCSPI5_SHIFT   20u
#define CSC0_STOP_REQR1_FCSPI5_WIDTH   1u
#define CSC0_STOP_REQR1_FCSPI5(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCSPI5_SHIFT))&CSC0_STOP_REQR1_FCSPI5_MASK)
#define CSC0_STOP_REQR1_FCSPI4_MASK    0x80000u
#define CSC0_STOP_REQR1_FCSPI4_SHIFT   19u
#define CSC0_STOP_REQR1_FCSPI4_WIDTH   1u
#define CSC0_STOP_REQR1_FCSPI4(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCSPI4_SHIFT))&CSC0_STOP_REQR1_FCSPI4_MASK)
#define CSC0_STOP_REQR1_FCIIC1_MASK    0x400u
#define CSC0_STOP_REQR1_FCIIC1_SHIFT   10u
#define CSC0_STOP_REQR1_FCIIC1_WIDTH   1u
#define CSC0_STOP_REQR1_FCIIC1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCIIC1_SHIFT))&CSC0_STOP_REQR1_FCIIC1_MASK)
#define CSC0_STOP_REQR1_SENT1_MASK     0x200u
#define CSC0_STOP_REQR1_SENT1_SHIFT    9u
#define CSC0_STOP_REQR1_SENT1_WIDTH    1u
#define CSC0_STOP_REQR1_SENT1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_SENT1_SHIFT))&CSC0_STOP_REQR1_SENT1_MASK)
#define CSC0_STOP_REQR1_WDOG1_MASK     0x2u
#define CSC0_STOP_REQR1_WDOG1_SHIFT    1u
#define CSC0_STOP_REQR1_WDOG1_WIDTH    1u
#define CSC0_STOP_REQR1_WDOG1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WDOG1_SHIFT))&CSC0_STOP_REQR1_WDOG1_MASK)
/* STOP_REQR1 Reg Mask */
#define CSC0_STOP_REQR1_MASK           0xF3B80602u

/* STOP_ACKR1 Bit Fields */
#define CSC0_STOP_ACKR1_FLEXCAN7_MASK  0x2000000u
#define CSC0_STOP_ACKR1_FLEXCAN7_SHIFT 25u
#define CSC0_STOP_ACKR1_FLEXCAN7_WIDTH 1u
#define CSC0_STOP_ACKR1_FLEXCAN7(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FLEXCAN7_SHIFT))&CSC0_STOP_ACKR1_FLEXCAN7_MASK)
#define CSC0_STOP_ACKR1_FLEXCAN6_MASK  0x1000000u
#define CSC0_STOP_ACKR1_FLEXCAN6_SHIFT 24u
#define CSC0_STOP_ACKR1_FLEXCAN6_WIDTH 1u
#define CSC0_STOP_ACKR1_FLEXCAN6(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FLEXCAN6_SHIFT))&CSC0_STOP_ACKR1_FLEXCAN6_MASK)
#define CSC0_STOP_ACKR1_FLEXCAN5_MASK  0x800000u
#define CSC0_STOP_ACKR1_FLEXCAN5_SHIFT 23u
#define CSC0_STOP_ACKR1_FLEXCAN5_WIDTH 1u
#define CSC0_STOP_ACKR1_FLEXCAN5(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FLEXCAN5_SHIFT))&CSC0_STOP_ACKR1_FLEXCAN5_MASK)
#define CSC0_STOP_ACKR1_MSC0_MASK      0x200000u
#define CSC0_STOP_ACKR1_MSC0_SHIFT     21u
#define CSC0_STOP_ACKR1_MSC0_WIDTH     1u
#define CSC0_STOP_ACKR1_MSC0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_MSC0_SHIFT))&CSC0_STOP_ACKR1_MSC0_MASK)
#define CSC0_STOP_ACKR1_FCSPI5_MASK    0x100000u
#define CSC0_STOP_ACKR1_FCSPI5_SHIFT   20u
#define CSC0_STOP_ACKR1_FCSPI5_WIDTH   1u
#define CSC0_STOP_ACKR1_FCSPI5(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCSPI5_SHIFT))&CSC0_STOP_ACKR1_FCSPI5_MASK)
#define CSC0_STOP_ACKR1_FCSPI4_MASK    0x80000u
#define CSC0_STOP_ACKR1_FCSPI4_SHIFT   19u
#define CSC0_STOP_ACKR1_FCSPI4_WIDTH   1u
#define CSC0_STOP_ACKR1_FCSPI4(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCSPI4_SHIFT))&CSC0_STOP_ACKR1_FCSPI4_MASK)
#define CSC0_STOP_ACKR1_FCIIC1_MASK    0x400u
#define CSC0_STOP_ACKR1_FCIIC1_SHIFT   10u
#define CSC0_STOP_ACKR1_FCIIC1_WIDTH   1u
#define CSC0_STOP_ACKR1_FCIIC1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCIIC1_SHIFT))&CSC0_STOP_ACKR1_FCIIC1_MASK)
#define CSC0_STOP_ACKR1_SENT1_MASK     0x200u
#define CSC0_STOP_ACKR1_SENT1_SHIFT    9u
#define CSC0_STOP_ACKR1_SENT1_WIDTH    1u
#define CSC0_STOP_ACKR1_SENT1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_SENT1_SHIFT))&CSC0_STOP_ACKR1_SENT1_MASK)
#define CSC0_STOP_ACKR1_WDOG1_MASK     0x2u
#define CSC0_STOP_ACKR1_WDOG1_SHIFT    1u
#define CSC0_STOP_ACKR1_WDOG1_WIDTH    1u
#define CSC0_STOP_ACKR1_WDOG1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_WDOG1_SHIFT))&CSC0_STOP_ACKR1_WDOG1_MASK)
/* STOP_ACKR1 Reg Mask */
#define CSC0_STOP_ACKR1_MASK           0x03B80602u

/* STOP_MODER2 Bit Fields */
#define CSC0_STOP_MODER2_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER2_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER2_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER2_WPB_LOCK(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_WPB_LOCK_SHIFT))&CSC0_STOP_MODER2_WPB_LOCK_MASK)
#define CSC0_STOP_MODER2_WPB_MASK      0x70000000u
#define CSC0_STOP_MODER2_WPB_SHIFT     28u
#define CSC0_STOP_MODER2_WPB_WIDTH     3u
#define CSC0_STOP_MODER2_WPB(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_WPB_SHIFT))&CSC0_STOP_MODER2_WPB_MASK)
#define CSC0_STOP_MODER2_FREQM_MASK    0x8000000u
#define CSC0_STOP_MODER2_FREQM_SHIFT   27u
#define CSC0_STOP_MODER2_FREQM_WIDTH   1u
#define CSC0_STOP_MODER2_FREQM(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FREQM_SHIFT))&CSC0_STOP_MODER2_FREQM_MASK)
#define CSC0_STOP_MODER2_LDI0_MASK     0x2000000u
#define CSC0_STOP_MODER2_LDI0_SHIFT    25u
#define CSC0_STOP_MODER2_LDI0_WIDTH    1u
#define CSC0_STOP_MODER2_LDI0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_LDI0_SHIFT))&CSC0_STOP_MODER2_LDI0_MASK)
#define CSC0_STOP_MODER2_SSI0_MASK     0x1000000u
#define CSC0_STOP_MODER2_SSI0_SHIFT    24u
#define CSC0_STOP_MODER2_SSI0_WIDTH    1u
#define CSC0_STOP_MODER2_SSI0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_SSI0_SHIFT))&CSC0_STOP_MODER2_SSI0_MASK)
#define CSC0_STOP_MODER2_SDADC0_MASK   0x200000u
#define CSC0_STOP_MODER2_SDADC0_SHIFT  21u
#define CSC0_STOP_MODER2_SDADC0_WIDTH  1u
#define CSC0_STOP_MODER2_SDADC0(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_SDADC0_SHIFT))&CSC0_STOP_MODER2_SDADC0_MASK)
#define CSC0_STOP_MODER2_FCUART0_MASK  0x400u
#define CSC0_STOP_MODER2_FCUART0_SHIFT 10u
#define CSC0_STOP_MODER2_FCUART0_WIDTH 1u
#define CSC0_STOP_MODER2_FCUART0(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCUART0_SHIFT))&CSC0_STOP_MODER2_FCUART0_MASK)
#define CSC0_STOP_MODER2_FCIIC0_MASK   0x200u
#define CSC0_STOP_MODER2_FCIIC0_SHIFT  9u
#define CSC0_STOP_MODER2_FCIIC0_WIDTH  1u
#define CSC0_STOP_MODER2_FCIIC0(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCIIC0_SHIFT))&CSC0_STOP_MODER2_FCIIC0_MASK)
#define CSC0_STOP_MODER2_FCSPI0_MASK   0x100u
#define CSC0_STOP_MODER2_FCSPI0_SHIFT  8u
#define CSC0_STOP_MODER2_FCSPI0_WIDTH  1u
#define CSC0_STOP_MODER2_FCSPI0(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCSPI0_SHIFT))&CSC0_STOP_MODER2_FCSPI0_MASK)
#define CSC0_STOP_MODER2_CMU3_MASK     0x20u
#define CSC0_STOP_MODER2_CMU3_SHIFT    5u
#define CSC0_STOP_MODER2_CMU3_WIDTH    1u
#define CSC0_STOP_MODER2_CMU3(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU3_SHIFT))&CSC0_STOP_MODER2_CMU3_MASK)
#define CSC0_STOP_MODER2_CMU2_MASK     0x10u
#define CSC0_STOP_MODER2_CMU2_SHIFT    4u
#define CSC0_STOP_MODER2_CMU2_WIDTH    1u
#define CSC0_STOP_MODER2_CMU2(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU2_SHIFT))&CSC0_STOP_MODER2_CMU2_MASK)
#define CSC0_STOP_MODER2_CMU1_MASK     0x8u
#define CSC0_STOP_MODER2_CMU1_SHIFT    3u
#define CSC0_STOP_MODER2_CMU1_WIDTH    1u
#define CSC0_STOP_MODER2_CMU1(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU1_SHIFT))&CSC0_STOP_MODER2_CMU1_MASK)
#define CSC0_STOP_MODER2_CMU0_MASK     0x4u
#define CSC0_STOP_MODER2_CMU0_SHIFT    2u
#define CSC0_STOP_MODER2_CMU0_WIDTH    1u
#define CSC0_STOP_MODER2_CMU0(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU0_SHIFT))&CSC0_STOP_MODER2_CMU0_MASK)
/* STOP_MODER2 Reg Mask */
#define CSC0_STOP_MODER2_MASK          0xFB20073Cu

/* STOP_REQR2 Bit Fields */
#define CSC0_STOP_REQR2_WPB_LOCK_MASK  0x80000000u
#define CSC0_STOP_REQR2_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR2_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR2_WPB_LOCK(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_WPB_LOCK_SHIFT))&CSC0_STOP_REQR2_WPB_LOCK_MASK)
#define CSC0_STOP_REQR2_WPB_MASK       0x70000000u
#define CSC0_STOP_REQR2_WPB_SHIFT      28u
#define CSC0_STOP_REQR2_WPB_WIDTH      3u
#define CSC0_STOP_REQR2_WPB(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_WPB_SHIFT))&CSC0_STOP_REQR2_WPB_MASK)
#define CSC0_STOP_REQR2_FREQM_MASK     0x8000000u
#define CSC0_STOP_REQR2_FREQM_SHIFT    27u
#define CSC0_STOP_REQR2_FREQM_WIDTH    1u
#define CSC0_STOP_REQR2_FREQM(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FREQM_SHIFT))&CSC0_STOP_REQR2_FREQM_MASK)
#define CSC0_STOP_REQR2_LDI0_MASK      0x2000000u
#define CSC0_STOP_REQR2_LDI0_SHIFT     25u
#define CSC0_STOP_REQR2_LDI0_WIDTH     1u
#define CSC0_STOP_REQR2_LDI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_LDI0_SHIFT))&CSC0_STOP_REQR2_LDI0_MASK)
#define CSC0_STOP_REQR2_SSI0_MASK      0x1000000u
#define CSC0_STOP_REQR2_SSI0_SHIFT     24u
#define CSC0_STOP_REQR2_SSI0_WIDTH     1u
#define CSC0_STOP_REQR2_SSI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_SSI0_SHIFT))&CSC0_STOP_REQR2_SSI0_MASK)
#define CSC0_STOP_REQR2_SDADC0_MASK    0x200000u
#define CSC0_STOP_REQR2_SDADC0_SHIFT   21u
#define CSC0_STOP_REQR2_SDADC0_WIDTH   1u
#define CSC0_STOP_REQR2_SDADC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_SDADC0_SHIFT))&CSC0_STOP_REQR2_SDADC0_MASK)
#define CSC0_STOP_REQR2_FCUART0_MASK   0x400u
#define CSC0_STOP_REQR2_FCUART0_SHIFT  10u
#define CSC0_STOP_REQR2_FCUART0_WIDTH  1u
#define CSC0_STOP_REQR2_FCUART0(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCUART0_SHIFT))&CSC0_STOP_REQR2_FCUART0_MASK)
#define CSC0_STOP_REQR2_FCIIC0_MASK    0x200u
#define CSC0_STOP_REQR2_FCIIC0_SHIFT   9u
#define CSC0_STOP_REQR2_FCIIC0_WIDTH   1u
#define CSC0_STOP_REQR2_FCIIC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCIIC0_SHIFT))&CSC0_STOP_REQR2_FCIIC0_MASK)
#define CSC0_STOP_REQR2_FCSPI0_MASK    0x100u
#define CSC0_STOP_REQR2_FCSPI0_SHIFT   8u
#define CSC0_STOP_REQR2_FCSPI0_WIDTH   1u
#define CSC0_STOP_REQR2_FCSPI0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCSPI0_SHIFT))&CSC0_STOP_REQR2_FCSPI0_MASK)
#define CSC0_STOP_REQR2_CMP0_MASK      0x40u
#define CSC0_STOP_REQR2_CMP0_SHIFT     6u
#define CSC0_STOP_REQR2_CMP0_WIDTH     1u
#define CSC0_STOP_REQR2_CMP0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMP0_SHIFT))&CSC0_STOP_REQR2_CMP0_MASK)
#define CSC0_STOP_REQR2_CMU3_MASK      0x20u
#define CSC0_STOP_REQR2_CMU3_SHIFT     5u
#define CSC0_STOP_REQR2_CMU3_WIDTH     1u
#define CSC0_STOP_REQR2_CMU3(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU3_SHIFT))&CSC0_STOP_REQR2_CMU3_MASK)
#define CSC0_STOP_REQR2_CMU2_MASK      0x10u
#define CSC0_STOP_REQR2_CMU2_SHIFT     4u
#define CSC0_STOP_REQR2_CMU2_WIDTH     1u
#define CSC0_STOP_REQR2_CMU2(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU2_SHIFT))&CSC0_STOP_REQR2_CMU2_MASK)
#define CSC0_STOP_REQR2_CMU1_MASK      0x8u
#define CSC0_STOP_REQR2_CMU1_SHIFT     3u
#define CSC0_STOP_REQR2_CMU1_WIDTH     1u
#define CSC0_STOP_REQR2_CMU1(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU1_SHIFT))&CSC0_STOP_REQR2_CMU1_MASK)
#define CSC0_STOP_REQR2_CMU0_MASK      0x4u
#define CSC0_STOP_REQR2_CMU0_SHIFT     2u
#define CSC0_STOP_REQR2_CMU0_WIDTH     1u
#define CSC0_STOP_REQR2_CMU0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU0_SHIFT))&CSC0_STOP_REQR2_CMU0_MASK)
/* STOP_REQR2 Reg Mask */
#define CSC0_STOP_REQR2_MASK           0xFB20077Cu

/* STOP_ACKR2 Bit Fields */
#define CSC0_STOP_ACKR2_FREQM_MASK     0x8000000u
#define CSC0_STOP_ACKR2_FREQM_SHIFT    27u
#define CSC0_STOP_ACKR2_FREQM_WIDTH    1u
#define CSC0_STOP_ACKR2_FREQM(x)       (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FREQM_SHIFT))&CSC0_STOP_ACKR2_FREQM_MASK)
#define CSC0_STOP_ACKR2_LDI0_MASK      0x2000000u
#define CSC0_STOP_ACKR2_LDI0_SHIFT     25u
#define CSC0_STOP_ACKR2_LDI0_WIDTH     1u
#define CSC0_STOP_ACKR2_LDI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_LDI0_SHIFT))&CSC0_STOP_ACKR2_LDI0_MASK)
#define CSC0_STOP_ACKR2_SSI0_MASK      0x1000000u
#define CSC0_STOP_ACKR2_SSI0_SHIFT     24u
#define CSC0_STOP_ACKR2_SSI0_WIDTH     1u
#define CSC0_STOP_ACKR2_SSI0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_SSI0_SHIFT))&CSC0_STOP_ACKR2_SSI0_MASK)
#define CSC0_STOP_ACKR2_SDADC0_MASK    0x200000u
#define CSC0_STOP_ACKR2_SDADC0_SHIFT   21u
#define CSC0_STOP_ACKR2_SDADC0_WIDTH   1u
#define CSC0_STOP_ACKR2_SDADC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_SDADC0_SHIFT))&CSC0_STOP_ACKR2_SDADC0_MASK)
#define CSC0_STOP_ACKR2_FCUART0_MASK   0x400u
#define CSC0_STOP_ACKR2_FCUART0_SHIFT  10u
#define CSC0_STOP_ACKR2_FCUART0_WIDTH  1u
#define CSC0_STOP_ACKR2_FCUART0(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCUART0_SHIFT))&CSC0_STOP_ACKR2_FCUART0_MASK)
#define CSC0_STOP_ACKR2_FCIIC0_MASK    0x200u
#define CSC0_STOP_ACKR2_FCIIC0_SHIFT   9u
#define CSC0_STOP_ACKR2_FCIIC0_WIDTH   1u
#define CSC0_STOP_ACKR2_FCIIC0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCIIC0_SHIFT))&CSC0_STOP_ACKR2_FCIIC0_MASK)
#define CSC0_STOP_ACKR2_FCSPI0_MASK    0x100u
#define CSC0_STOP_ACKR2_FCSPI0_SHIFT   8u
#define CSC0_STOP_ACKR2_FCSPI0_WIDTH   1u
#define CSC0_STOP_ACKR2_FCSPI0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCSPI0_SHIFT))&CSC0_STOP_ACKR2_FCSPI0_MASK)
#define CSC0_STOP_ACKR2_CMU3_MASK      0x20u
#define CSC0_STOP_ACKR2_CMU3_SHIFT     5u
#define CSC0_STOP_ACKR2_CMU3_WIDTH     1u
#define CSC0_STOP_ACKR2_CMU3(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU3_SHIFT))&CSC0_STOP_ACKR2_CMU3_MASK)
#define CSC0_STOP_ACKR2_CMU2_MASK      0x10u
#define CSC0_STOP_ACKR2_CMU2_SHIFT     4u
#define CSC0_STOP_ACKR2_CMU2_WIDTH     1u
#define CSC0_STOP_ACKR2_CMU2(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU2_SHIFT))&CSC0_STOP_ACKR2_CMU2_MASK)
#define CSC0_STOP_ACKR2_CMU1_MASK      0x8u
#define CSC0_STOP_ACKR2_CMU1_SHIFT     3u
#define CSC0_STOP_ACKR2_CMU1_WIDTH     1u
#define CSC0_STOP_ACKR2_CMU1(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU1_SHIFT))&CSC0_STOP_ACKR2_CMU1_MASK)
#define CSC0_STOP_ACKR2_CMU0_MASK      0x4u
#define CSC0_STOP_ACKR2_CMU0_SHIFT     2u
#define CSC0_STOP_ACKR2_CMU0_WIDTH     1u
#define CSC0_STOP_ACKR2_CMU0(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU0_SHIFT))&CSC0_STOP_ACKR2_CMU0_MASK)
/* STOP_ACKR2 Reg Mask */
#define CSC0_STOP_ACKR2_MASK           0x0B20073Cu

/* CCM0_CFG Bit Fields */
#define CSC0_CCM0_CFG_WPB_LOCK_MASK    0x80000000u
#define CSC0_CCM0_CFG_WPB_LOCK_SHIFT   31u
#define CSC0_CCM0_CFG_WPB_LOCK_WIDTH   1u
#define CSC0_CCM0_CFG_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_WPB_LOCK_SHIFT))&CSC0_CCM0_CFG_WPB_LOCK_MASK)
#define CSC0_CCM0_CFG_WPB_MASK         0x70000000u
#define CSC0_CCM0_CFG_WPB_SHIFT        28u
#define CSC0_CCM0_CFG_WPB_WIDTH        3u
#define CSC0_CCM0_CFG_WPB(x)           (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_WPB_SHIFT))&CSC0_CCM0_CFG_WPB_MASK)
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK 0x4u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_SHIFT 2u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_WIDTH 1u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_SHIFT))&CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK)
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK 0x3u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT 0u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_WIDTH 2u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT))&CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK)
/* CCM0_CFG Reg Mask */
#define CSC0_CCM0_CFG_MASK             0xF0000007u

/* SCG_MAM_STALL Bit Fields */
#define CSC0_SCG_MAM_STALL_SCG_STALL_MASK 0x2u
#define CSC0_SCG_MAM_STALL_SCG_STALL_SHIFT 1u
#define CSC0_SCG_MAM_STALL_SCG_STALL_WIDTH 1u
#define CSC0_SCG_MAM_STALL_SCG_STALL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SCG_MAM_STALL_SCG_STALL_SHIFT))&CSC0_SCG_MAM_STALL_SCG_STALL_MASK)
#define CSC0_SCG_MAM_STALL_LOCK_MASK   0x1u
#define CSC0_SCG_MAM_STALL_LOCK_SHIFT  0u
#define CSC0_SCG_MAM_STALL_LOCK_WIDTH  1u
#define CSC0_SCG_MAM_STALL_LOCK(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SCG_MAM_STALL_LOCK_SHIFT))&CSC0_SCG_MAM_STALL_LOCK_MASK)
/* SCG_MAM_STALL Reg Mask */
#define CSC0_SCG_MAM_STALL_MASK        0x00000003u

/* CPU0_INT Bit Fields */
#define CSC0_CPU0_INT_WPB_LOCK_MASK    0x80000000u
#define CSC0_CPU0_INT_WPB_LOCK_SHIFT   31u
#define CSC0_CPU0_INT_WPB_LOCK_WIDTH   1u
#define CSC0_CPU0_INT_WPB_LOCK(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_WPB_LOCK_SHIFT))&CSC0_CPU0_INT_WPB_LOCK_MASK)
#define CSC0_CPU0_INT_WPB_MASK         0x70000000u
#define CSC0_CPU0_INT_WPB_SHIFT        28u
#define CSC0_CPU0_INT_WPB_WIDTH        3u
#define CSC0_CPU0_INT_WPB(x)           (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_WPB_SHIFT))&CSC0_CPU0_INT_WPB_MASK)
#define CSC0_CPU0_INT_SW_INT_MASK      0x1u
#define CSC0_CPU0_INT_SW_INT_SHIFT     0u
#define CSC0_CPU0_INT_SW_INT_WIDTH     1u
#define CSC0_CPU0_INT_SW_INT(x)        (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_SW_INT_SHIFT))&CSC0_CPU0_INT_SW_INT_MASK)
/* CPU0_INT Reg Mask */
#define CSC0_CPU0_INT_MASK             0xF0000001u

/* SMU_CTRL0 Bit Fields */
#define CSC0_SMU_CTRL0_CMU4_MASK       0x80000000u
#define CSC0_SMU_CTRL0_CMU4_SHIFT      31u
#define CSC0_SMU_CTRL0_CMU4_WIDTH      1u
#define CSC0_SMU_CTRL0_CMU4(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU4_SHIFT))&CSC0_SMU_CTRL0_CMU4_MASK)
#define CSC0_SMU_CTRL0_PMC_MON_MASK    0x40000000u
#define CSC0_SMU_CTRL0_PMC_MON_SHIFT   30u
#define CSC0_SMU_CTRL0_PMC_MON_WIDTH   1u
#define CSC0_SMU_CTRL0_PMC_MON(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_PMC_MON_SHIFT))&CSC0_SMU_CTRL0_PMC_MON_MASK)
#define CSC0_SMU_CTRL0_CMU2_MASK       0x20000000u
#define CSC0_SMU_CTRL0_CMU2_SHIFT      29u
#define CSC0_SMU_CTRL0_CMU2_WIDTH      1u
#define CSC0_SMU_CTRL0_CMU2(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU2_SHIFT))&CSC0_SMU_CTRL0_CMU2_MASK)
#define CSC0_SMU_CTRL0_CMU1_MASK       0x10000000u
#define CSC0_SMU_CTRL0_CMU1_SHIFT      28u
#define CSC0_SMU_CTRL0_CMU1_WIDTH      1u
#define CSC0_SMU_CTRL0_CMU1(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU1_SHIFT))&CSC0_SMU_CTRL0_CMU1_MASK)
#define CSC0_SMU_CTRL0_PMC_LVDHVD_MASK 0x8000000u
#define CSC0_SMU_CTRL0_PMC_LVDHVD_SHIFT 27u
#define CSC0_SMU_CTRL0_PMC_LVDHVD_WIDTH 1u
#define CSC0_SMU_CTRL0_PMC_LVDHVD(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_PMC_LVDHVD_SHIFT))&CSC0_SMU_CTRL0_PMC_LVDHVD_MASK)
#define CSC0_SMU_CTRL0_SRAM2_MON_MASK  0x4000000u
#define CSC0_SMU_CTRL0_SRAM2_MON_SHIFT 26u
#define CSC0_SMU_CTRL0_SRAM2_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_SRAM2_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_SRAM2_MON_SHIFT))&CSC0_SMU_CTRL0_SRAM2_MON_MASK)
#define CSC0_SMU_CTRL0_SRAM1_MON_MASK  0x2000000u
#define CSC0_SMU_CTRL0_SRAM1_MON_SHIFT 25u
#define CSC0_SMU_CTRL0_SRAM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_SRAM1_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_SRAM1_MON_SHIFT))&CSC0_SMU_CTRL0_SRAM1_MON_MASK)
#define CSC0_SMU_CTRL0_SRAM0_MON_MASK  0x1000000u
#define CSC0_SMU_CTRL0_SRAM0_MON_SHIFT 24u
#define CSC0_SMU_CTRL0_SRAM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_SRAM0_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_SRAM0_MON_SHIFT))&CSC0_SMU_CTRL0_SRAM0_MON_MASK)
#define CSC0_SMU_CTRL0_MCM_MASK        0x800000u
#define CSC0_SMU_CTRL0_MCM_SHIFT       23u
#define CSC0_SMU_CTRL0_MCM_WIDTH       1u
#define CSC0_SMU_CTRL0_MCM(x)          (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MCM_SHIFT))&CSC0_SMU_CTRL0_MCM_MASK)
#define CSC0_SMU_CTRL0_MAM1_S2_DS_MASK 0x200000u
#define CSC0_SMU_CTRL0_MAM1_S2_DS_SHIFT 21u
#define CSC0_SMU_CTRL0_MAM1_S2_DS_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM1_S2_DS(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM1_S2_DS_SHIFT))&CSC0_SMU_CTRL0_MAM1_S2_DS_MASK)
#define CSC0_SMU_CTRL0_MAM0_S7_DS_MASK 0x100000u
#define CSC0_SMU_CTRL0_MAM0_S7_DS_SHIFT 20u
#define CSC0_SMU_CTRL0_MAM0_S7_DS_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S7_DS(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S7_DS_SHIFT))&CSC0_SMU_CTRL0_MAM0_S7_DS_MASK)
#define CSC0_SMU_CTRL0_DMA0_MASK       0x40000u
#define CSC0_SMU_CTRL0_DMA0_SHIFT      18u
#define CSC0_SMU_CTRL0_DMA0_WIDTH      1u
#define CSC0_SMU_CTRL0_DMA0(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_DMA0_SHIFT))&CSC0_SMU_CTRL0_DMA0_MASK)
#define CSC0_SMU_CTRL0_HSM_MASK        0x20000u
#define CSC0_SMU_CTRL0_HSM_SHIFT       17u
#define CSC0_SMU_CTRL0_HSM_WIDTH       1u
#define CSC0_SMU_CTRL0_HSM(x)          (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_HSM_SHIFT))&CSC0_SMU_CTRL0_HSM_MASK)
#define CSC0_SMU_CTRL0_ENET_MASK       0x10000u
#define CSC0_SMU_CTRL0_ENET_SHIFT      16u
#define CSC0_SMU_CTRL0_ENET_WIDTH      1u
#define CSC0_SMU_CTRL0_ENET(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_ENET_SHIFT))&CSC0_SMU_CTRL0_ENET_MASK)
#define CSC0_SMU_CTRL0_MAM0_S7_S2F_MON_MASK 0x8000u
#define CSC0_SMU_CTRL0_MAM0_S7_S2F_MON_SHIFT 15u
#define CSC0_SMU_CTRL0_MAM0_S7_S2F_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S7_S2F_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S7_S2F_MON_SHIFT))&CSC0_SMU_CTRL0_MAM0_S7_S2F_MON_MASK)
#define CSC0_SMU_CTRL0_MAM1_S2_MASK    0x800u
#define CSC0_SMU_CTRL0_MAM1_S2_SHIFT   11u
#define CSC0_SMU_CTRL0_MAM1_S2_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM1_S2(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM1_S2_SHIFT))&CSC0_SMU_CTRL0_MAM1_S2_MASK)
#define CSC0_SMU_CTRL0_MAM1_S1_MASK    0x400u
#define CSC0_SMU_CTRL0_MAM1_S1_SHIFT   10u
#define CSC0_SMU_CTRL0_MAM1_S1_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM1_S1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM1_S1_SHIFT))&CSC0_SMU_CTRL0_MAM1_S1_MASK)
#define CSC0_SMU_CTRL0_MAM1_S0_MASK    0x200u
#define CSC0_SMU_CTRL0_MAM1_S0_SHIFT   9u
#define CSC0_SMU_CTRL0_MAM1_S0_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM1_S0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM1_S0_SHIFT))&CSC0_SMU_CTRL0_MAM1_S0_MASK)
#define CSC0_SMU_CTRL0_MAM0_S7_MASK    0x100u
#define CSC0_SMU_CTRL0_MAM0_S7_SHIFT   8u
#define CSC0_SMU_CTRL0_MAM0_S7_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S7(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S7_SHIFT))&CSC0_SMU_CTRL0_MAM0_S7_MASK)
#define CSC0_SMU_CTRL0_MAM0_S6_MASK    0x80u
#define CSC0_SMU_CTRL0_MAM0_S6_SHIFT   7u
#define CSC0_SMU_CTRL0_MAM0_S6_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S6(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S6_SHIFT))&CSC0_SMU_CTRL0_MAM0_S6_MASK)
#define CSC0_SMU_CTRL0_MAM0_S5_MASK    0x40u
#define CSC0_SMU_CTRL0_MAM0_S5_SHIFT   6u
#define CSC0_SMU_CTRL0_MAM0_S5_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S5(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S5_SHIFT))&CSC0_SMU_CTRL0_MAM0_S5_MASK)
#define CSC0_SMU_CTRL0_MAM0_S4_MASK    0x20u
#define CSC0_SMU_CTRL0_MAM0_S4_SHIFT   5u
#define CSC0_SMU_CTRL0_MAM0_S4_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S4(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S4_SHIFT))&CSC0_SMU_CTRL0_MAM0_S4_MASK)
#define CSC0_SMU_CTRL0_MAM0_S3_MASK    0x10u
#define CSC0_SMU_CTRL0_MAM0_S3_SHIFT   4u
#define CSC0_SMU_CTRL0_MAM0_S3_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S3(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S3_SHIFT))&CSC0_SMU_CTRL0_MAM0_S3_MASK)
#define CSC0_SMU_CTRL0_MAM0_S1_MASK    0x4u
#define CSC0_SMU_CTRL0_MAM0_S1_SHIFT   2u
#define CSC0_SMU_CTRL0_MAM0_S1_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S1(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S1_SHIFT))&CSC0_SMU_CTRL0_MAM0_S1_MASK)
#define CSC0_SMU_CTRL0_MAM0_S0_MASK    0x2u
#define CSC0_SMU_CTRL0_MAM0_S0_SHIFT   1u
#define CSC0_SMU_CTRL0_MAM0_S0_WIDTH   1u
#define CSC0_SMU_CTRL0_MAM0_S0(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S0_SHIFT))&CSC0_SMU_CTRL0_MAM0_S0_MASK)
#define CSC0_SMU_CTRL0_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL0_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL0_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL0_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_LOCK_SHIFT))&CSC0_SMU_CTRL0_LOCK_MASK)
/* SMU_CTRL0 Reg Mask */
#define CSC0_SMU_CTRL0_MASK            0xFFB78FF7u

/* SMU_CTRL1 Bit Fields */
#define CSC0_SMU_CTRL1_INTM0_MON_MASK  0x80000000u
#define CSC0_SMU_CTRL1_INTM0_MON_SHIFT 31u
#define CSC0_SMU_CTRL1_INTM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_INTM0_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_INTM0_MON_SHIFT))&CSC0_SMU_CTRL1_INTM0_MON_MASK)
#define CSC0_SMU_CTRL1_C0_DTCM1_S_EN_MASK 0x40000u
#define CSC0_SMU_CTRL1_C0_DTCM1_S_EN_SHIFT 18u
#define CSC0_SMU_CTRL1_C0_DTCM1_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_C0_DTCM1_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_C0_DTCM1_S_EN_SHIFT))&CSC0_SMU_CTRL1_C0_DTCM1_S_EN_MASK)
#define CSC0_SMU_CTRL1_C0_DTCM0_S_EN_MASK 0x20000u
#define CSC0_SMU_CTRL1_C0_DTCM0_S_EN_SHIFT 17u
#define CSC0_SMU_CTRL1_C0_DTCM0_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_C0_DTCM0_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_C0_DTCM0_S_EN_SHIFT))&CSC0_SMU_CTRL1_C0_DTCM0_S_EN_MASK)
#define CSC0_SMU_CTRL1_C0_ITCM_S_EN_MASK 0x10000u
#define CSC0_SMU_CTRL1_C0_ITCM_S_EN_SHIFT 16u
#define CSC0_SMU_CTRL1_C0_ITCM_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_C0_ITCM_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_C0_ITCM_S_EN_SHIFT))&CSC0_SMU_CTRL1_C0_ITCM_S_EN_MASK)
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK 0x8000u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_SHIFT 15u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_OVERLAY_SHIFT))&CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK 0x4000u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_SHIFT 14u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM1_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK 0x2000u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_SHIFT 13u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM0_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK 0x1000u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_SHIFT 12u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ITCM_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK 0x100u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_SHIFT 8u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBP_F2S_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MASK 0x80u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_SHIFT 7u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM1(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM1_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM1_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MASK 0x40u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_SHIFT 6u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM0(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM0_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM0_MASK)
#define CSC0_SMU_CTRL1_CPU0_ITCM_MASK  0x20u
#define CSC0_SMU_CTRL1_CPU0_ITCM_SHIFT 5u
#define CSC0_SMU_CTRL1_CPU0_ITCM_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ITCM(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ITCM_SHIFT))&CSC0_SMU_CTRL1_CPU0_ITCM_MASK)
#define CSC0_SMU_CTRL1_CPU0_DCACHE_MASK 0x10u
#define CSC0_SMU_CTRL1_CPU0_DCACHE_SHIFT 4u
#define CSC0_SMU_CTRL1_CPU0_DCACHE_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DCACHE(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DCACHE_SHIFT))&CSC0_SMU_CTRL1_CPU0_DCACHE_MASK)
#define CSC0_SMU_CTRL1_CPU0_ICACHE_MASK 0x8u
#define CSC0_SMU_CTRL1_CPU0_ICACHE_SHIFT 3u
#define CSC0_SMU_CTRL1_CPU0_ICACHE_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ICACHE(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ICACHE_SHIFT))&CSC0_SMU_CTRL1_CPU0_ICACHE_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBP_MASK  0x4u
#define CSC0_SMU_CTRL1_CPU0_AHBP_SHIFT 2u
#define CSC0_SMU_CTRL1_CPU0_AHBP_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBP(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBP_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBP_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBM_MASK  0x2u
#define CSC0_SMU_CTRL1_CPU0_AHBM_SHIFT 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBM_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBM_MASK)
#define CSC0_SMU_CTRL1_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL1_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL1_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL1_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_LOCK_SHIFT))&CSC0_SMU_CTRL1_LOCK_MASK)
/* SMU_CTRL1 Reg Mask */
#define CSC0_SMU_CTRL1_MASK            0x8007F1FFu

/* SMU_CTRL2 Bit Fields */
#define CSC0_SMU_CTRL2_INTM1_MON_MASK  0x80000000u
#define CSC0_SMU_CTRL2_INTM1_MON_SHIFT 31u
#define CSC0_SMU_CTRL2_INTM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL2_INTM1_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_INTM1_MON_SHIFT))&CSC0_SMU_CTRL2_INTM1_MON_MASK)
#define CSC0_SMU_CTRL2_C1_DTCM1_S_EN_MASK 0x40000u
#define CSC0_SMU_CTRL2_C1_DTCM1_S_EN_SHIFT 18u
#define CSC0_SMU_CTRL2_C1_DTCM1_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL2_C1_DTCM1_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_C1_DTCM1_S_EN_SHIFT))&CSC0_SMU_CTRL2_C1_DTCM1_S_EN_MASK)
#define CSC0_SMU_CTRL2_C1_DTCM0_S_EN_MASK 0x20000u
#define CSC0_SMU_CTRL2_C1_DTCM0_S_EN_SHIFT 17u
#define CSC0_SMU_CTRL2_C1_DTCM0_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL2_C1_DTCM0_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_C1_DTCM0_S_EN_SHIFT))&CSC0_SMU_CTRL2_C1_DTCM0_S_EN_MASK)
#define CSC0_SMU_CTRL2_C1_ITCM_S_EN_MASK 0x10000u
#define CSC0_SMU_CTRL2_C1_ITCM_S_EN_SHIFT 16u
#define CSC0_SMU_CTRL2_C1_ITCM_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL2_C1_ITCM_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_C1_ITCM_S_EN_SHIFT))&CSC0_SMU_CTRL2_C1_ITCM_S_EN_MASK)
#define CSC0_SMU_CTRL2_CPU1_OVERLAY_MASK 0x8000u
#define CSC0_SMU_CTRL2_CPU1_OVERLAY_SHIFT 15u
#define CSC0_SMU_CTRL2_CPU1_OVERLAY_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_OVERLAY(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_OVERLAY_SHIFT))&CSC0_SMU_CTRL2_CPU1_OVERLAY_MASK)
#define CSC0_SMU_CTRL2_CPU1_DTCM1_MON_MASK 0x4000u
#define CSC0_SMU_CTRL2_CPU1_DTCM1_MON_SHIFT 14u
#define CSC0_SMU_CTRL2_CPU1_DTCM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_DTCM1_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_DTCM1_MON_SHIFT))&CSC0_SMU_CTRL2_CPU1_DTCM1_MON_MASK)
#define CSC0_SMU_CTRL2_CPU1_DTCM0_MON_MASK 0x2000u
#define CSC0_SMU_CTRL2_CPU1_DTCM0_MON_SHIFT 13u
#define CSC0_SMU_CTRL2_CPU1_DTCM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_DTCM0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_DTCM0_MON_SHIFT))&CSC0_SMU_CTRL2_CPU1_DTCM0_MON_MASK)
#define CSC0_SMU_CTRL2_CPU1_ITCM_MON_MASK 0x1000u
#define CSC0_SMU_CTRL2_CPU1_ITCM_MON_SHIFT 12u
#define CSC0_SMU_CTRL2_CPU1_ITCM_MON_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_ITCM_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_ITCM_MON_SHIFT))&CSC0_SMU_CTRL2_CPU1_ITCM_MON_MASK)
#define CSC0_SMU_CTRL2_CPU1_AHBP_F2S_MASK 0x100u
#define CSC0_SMU_CTRL2_CPU1_AHBP_F2S_SHIFT 8u
#define CSC0_SMU_CTRL2_CPU1_AHBP_F2S_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_AHBP_F2S_SHIFT))&CSC0_SMU_CTRL2_CPU1_AHBP_F2S_MASK)
#define CSC0_SMU_CTRL2_CPU1_DTCM1_MASK 0x80u
#define CSC0_SMU_CTRL2_CPU1_DTCM1_SHIFT 7u
#define CSC0_SMU_CTRL2_CPU1_DTCM1_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_DTCM1(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_DTCM1_SHIFT))&CSC0_SMU_CTRL2_CPU1_DTCM1_MASK)
#define CSC0_SMU_CTRL2_CPU1_DTCM0_MASK 0x40u
#define CSC0_SMU_CTRL2_CPU1_DTCM0_SHIFT 6u
#define CSC0_SMU_CTRL2_CPU1_DTCM0_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_DTCM0(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_DTCM0_SHIFT))&CSC0_SMU_CTRL2_CPU1_DTCM0_MASK)
#define CSC0_SMU_CTRL2_CPU1_ITCM_MASK  0x20u
#define CSC0_SMU_CTRL2_CPU1_ITCM_SHIFT 5u
#define CSC0_SMU_CTRL2_CPU1_ITCM_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_ITCM(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_ITCM_SHIFT))&CSC0_SMU_CTRL2_CPU1_ITCM_MASK)
#define CSC0_SMU_CTRL2_CPU1_DCACHE_MASK 0x10u
#define CSC0_SMU_CTRL2_CPU1_DCACHE_SHIFT 4u
#define CSC0_SMU_CTRL2_CPU1_DCACHE_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_DCACHE(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_DCACHE_SHIFT))&CSC0_SMU_CTRL2_CPU1_DCACHE_MASK)
#define CSC0_SMU_CTRL2_CPU1_ICACHE_MASK 0x8u
#define CSC0_SMU_CTRL2_CPU1_ICACHE_SHIFT 3u
#define CSC0_SMU_CTRL2_CPU1_ICACHE_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_ICACHE(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_ICACHE_SHIFT))&CSC0_SMU_CTRL2_CPU1_ICACHE_MASK)
#define CSC0_SMU_CTRL2_CPU1_AHBP_MASK  0x4u
#define CSC0_SMU_CTRL2_CPU1_AHBP_SHIFT 2u
#define CSC0_SMU_CTRL2_CPU1_AHBP_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_AHBP(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_AHBP_SHIFT))&CSC0_SMU_CTRL2_CPU1_AHBP_MASK)
#define CSC0_SMU_CTRL2_CPU1_AHBM_MASK  0x2u
#define CSC0_SMU_CTRL2_CPU1_AHBM_SHIFT 1u
#define CSC0_SMU_CTRL2_CPU1_AHBM_WIDTH 1u
#define CSC0_SMU_CTRL2_CPU1_AHBM(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_CPU1_AHBM_SHIFT))&CSC0_SMU_CTRL2_CPU1_AHBM_MASK)
#define CSC0_SMU_CTRL2_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL2_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL2_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL2_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL2_LOCK_SHIFT))&CSC0_SMU_CTRL2_LOCK_MASK)
/* SMU_CTRL2 Reg Mask */
#define CSC0_SMU_CTRL2_MASK            0x8007F1FFu

/* SMU_CTRL4 Bit Fields */
#define CSC0_SMU_CTRL4_HSM_WDG_MASK    0x80000000u
#define CSC0_SMU_CTRL4_HSM_WDG_SHIFT   31u
#define CSC0_SMU_CTRL4_HSM_WDG_WIDTH   1u
#define CSC0_SMU_CTRL4_HSM_WDG(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_HSM_WDG_SHIFT))&CSC0_SMU_CTRL4_HSM_WDG_MASK)
#define CSC0_SMU_CTRL4_FMC_ERR_MASK    0x40000000u
#define CSC0_SMU_CTRL4_FMC_ERR_SHIFT   30u
#define CSC0_SMU_CTRL4_FMC_ERR_WIDTH   1u
#define CSC0_SMU_CTRL4_FMC_ERR(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FMC_ERR_SHIFT))&CSC0_SMU_CTRL4_FMC_ERR_MASK)
#define CSC0_SMU_CTRL4_ROM_S_EN_MASK   0x10000000u
#define CSC0_SMU_CTRL4_ROM_S_EN_SHIFT  28u
#define CSC0_SMU_CTRL4_ROM_S_EN_WIDTH  1u
#define CSC0_SMU_CTRL4_ROM_S_EN(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_ROM_S_EN_SHIFT))&CSC0_SMU_CTRL4_ROM_S_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN_MASK 0x4000000u
#define CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN_SHIFT 26u
#define CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM2_EDC_MON_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK 0x2000000u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_SHIFT 25u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK 0x1000000u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_SHIFT 24u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM2_S_EN_MASK 0x400000u
#define CSC0_SMU_CTRL4_SRAM2_S_EN_SHIFT 22u
#define CSC0_SMU_CTRL4_SRAM2_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM2_S_EN(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM2_S_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM2_S_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM1_S_EN_MASK 0x200000u
#define CSC0_SMU_CTRL4_SRAM1_S_EN_SHIFT 21u
#define CSC0_SMU_CTRL4_SRAM1_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_S_EN(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_S_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM1_S_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM0_S_EN_MASK 0x100000u
#define CSC0_SMU_CTRL4_SRAM0_S_EN_SHIFT 20u
#define CSC0_SMU_CTRL4_SRAM0_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_S_EN(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_S_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM0_S_EN_MASK)
#define CSC0_SMU_CTRL4_FLASH_RST_EN_MASK 0x40000u
#define CSC0_SMU_CTRL4_FLASH_RST_EN_SHIFT 18u
#define CSC0_SMU_CTRL4_FLASH_RST_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_FLASH_RST_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FLASH_RST_EN_SHIFT))&CSC0_SMU_CTRL4_FLASH_RST_EN_MASK)
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK 0x20000u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_SHIFT 17u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_WIDTH 1u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FLASH_ECC_EN_S_SHIFT))&CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK)
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK 0x10000u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_SHIFT 16u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FLASH_ECC_EN_SHIFT))&CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK)
#define CSC0_SMU_CTRL4_AFCB1_MON_MASK  0x8000u
#define CSC0_SMU_CTRL4_AFCB1_MON_SHIFT 15u
#define CSC0_SMU_CTRL4_AFCB1_MON_WIDTH 1u
#define CSC0_SMU_CTRL4_AFCB1_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_AFCB1_MON_SHIFT))&CSC0_SMU_CTRL4_AFCB1_MON_MASK)
#define CSC0_SMU_CTRL4_AFCB0_MON_MASK  0x4000u
#define CSC0_SMU_CTRL4_AFCB0_MON_SHIFT 14u
#define CSC0_SMU_CTRL4_AFCB0_MON_WIDTH 1u
#define CSC0_SMU_CTRL4_AFCB0_MON(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_AFCB0_MON_SHIFT))&CSC0_SMU_CTRL4_AFCB0_MON_MASK)
#define CSC0_SMU_CTRL4_SCF_RST_EN_MASK 0x2000u
#define CSC0_SMU_CTRL4_SCF_RST_EN_SHIFT 13u
#define CSC0_SMU_CTRL4_SCF_RST_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SCF_RST_EN(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCF_RST_EN_SHIFT))&CSC0_SMU_CTRL4_SCF_RST_EN_MASK)
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK 0x1000u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_SHIFT 12u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCF_IRQ_EN_SHIFT))&CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK)
#define CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN_MASK 0x400u
#define CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN_SHIFT 10u
#define CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN_SHIFT))&CSC0_SMU_CTRL4_TMU_IRQ_ERR_EN_MASK)
#define CSC0_SMU_CTRL4_SCM_CRC_MASK    0x200u
#define CSC0_SMU_CTRL4_SCM_CRC_SHIFT   9u
#define CSC0_SMU_CTRL4_SCM_CRC_WIDTH   1u
#define CSC0_SMU_CTRL4_SCM_CRC(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCM_CRC_SHIFT))&CSC0_SMU_CTRL4_SCM_CRC_MASK)
#define CSC0_SMU_CTRL4_SCG_CRC_MASK    0x100u
#define CSC0_SMU_CTRL4_SCG_CRC_SHIFT   8u
#define CSC0_SMU_CTRL4_SCG_CRC_WIDTH   1u
#define CSC0_SMU_CTRL4_SCG_CRC(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCG_CRC_SHIFT))&CSC0_SMU_CTRL4_SCG_CRC_MASK)
#define CSC0_SMU_CTRL4_SRAM2_ECC_MASK  0x40u
#define CSC0_SMU_CTRL4_SRAM2_ECC_SHIFT 6u
#define CSC0_SMU_CTRL4_SRAM2_ECC_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM2_ECC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM2_ECC_SHIFT))&CSC0_SMU_CTRL4_SRAM2_ECC_MASK)
#define CSC0_SMU_CTRL4_SRAM1_ECC_MASK  0x20u
#define CSC0_SMU_CTRL4_SRAM1_ECC_SHIFT 5u
#define CSC0_SMU_CTRL4_SRAM1_ECC_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_ECC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_ECC_SHIFT))&CSC0_SMU_CTRL4_SRAM1_ECC_MASK)
#define CSC0_SMU_CTRL4_SRAM0_ECC_MASK  0x10u
#define CSC0_SMU_CTRL4_SRAM0_ECC_SHIFT 4u
#define CSC0_SMU_CTRL4_SRAM0_ECC_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_ECC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_ECC_SHIFT))&CSC0_SMU_CTRL4_SRAM0_ECC_MASK)
#define CSC0_SMU_CTRL4_MAM1_ERR_MASK   0x4u
#define CSC0_SMU_CTRL4_MAM1_ERR_SHIFT  2u
#define CSC0_SMU_CTRL4_MAM1_ERR_WIDTH  1u
#define CSC0_SMU_CTRL4_MAM1_ERR(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_MAM1_ERR_SHIFT))&CSC0_SMU_CTRL4_MAM1_ERR_MASK)
#define CSC0_SMU_CTRL4_MAM0_ERR_MASK   0x2u
#define CSC0_SMU_CTRL4_MAM0_ERR_SHIFT  1u
#define CSC0_SMU_CTRL4_MAM0_ERR_WIDTH  1u
#define CSC0_SMU_CTRL4_MAM0_ERR(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_MAM0_ERR_SHIFT))&CSC0_SMU_CTRL4_MAM0_ERR_MASK)
#define CSC0_SMU_CTRL4_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL4_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL4_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL4_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_LOCK_SHIFT))&CSC0_SMU_CTRL4_LOCK_MASK)
/* SMU_CTRL4 Reg Mask */
#define CSC0_SMU_CTRL4_MASK            0xD777F777u

/* PERP_CTRL Bit Fields */
#define CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS_MASK 0x40000000u
#define CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS_SHIFT 30u
#define CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS_WIDTH 1u
#define CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS_SHIFT))&CSC0_PERP_CTRL_AFCB0_PD0_RMON_DIS_MASK)
#define CSC0_PERP_CTRL_AFCB1_RMON_DIS_MASK 0x20000000u
#define CSC0_PERP_CTRL_AFCB1_RMON_DIS_SHIFT 29u
#define CSC0_PERP_CTRL_AFCB1_RMON_DIS_WIDTH 1u
#define CSC0_PERP_CTRL_AFCB1_RMON_DIS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_AFCB1_RMON_DIS_SHIFT))&CSC0_PERP_CTRL_AFCB1_RMON_DIS_MASK)
#define CSC0_PERP_CTRL_AFCB0_RMON_DIS_MASK 0x10000000u
#define CSC0_PERP_CTRL_AFCB0_RMON_DIS_SHIFT 28u
#define CSC0_PERP_CTRL_AFCB0_RMON_DIS_WIDTH 1u
#define CSC0_PERP_CTRL_AFCB0_RMON_DIS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_AFCB0_RMON_DIS_SHIFT))&CSC0_PERP_CTRL_AFCB0_RMON_DIS_MASK)
#define CSC0_PERP_CTRL_DMA0_CHK_EN_MASK 0x10000u
#define CSC0_PERP_CTRL_DMA0_CHK_EN_SHIFT 16u
#define CSC0_PERP_CTRL_DMA0_CHK_EN_WIDTH 1u
#define CSC0_PERP_CTRL_DMA0_CHK_EN(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_DMA0_CHK_EN_SHIFT))&CSC0_PERP_CTRL_DMA0_CHK_EN_MASK)
#define CSC0_PERP_CTRL_CMU3_FCSMU_RST_MASK 0x200u
#define CSC0_PERP_CTRL_CMU3_FCSMU_RST_SHIFT 9u
#define CSC0_PERP_CTRL_CMU3_FCSMU_RST_WIDTH 1u
#define CSC0_PERP_CTRL_CMU3_FCSMU_RST(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_CMU3_FCSMU_RST_SHIFT))&CSC0_PERP_CTRL_CMU3_FCSMU_RST_MASK)
#define CSC0_PERP_CTRL_CMU3_RST_EN_MASK 0x100u
#define CSC0_PERP_CTRL_CMU3_RST_EN_SHIFT 8u
#define CSC0_PERP_CTRL_CMU3_RST_EN_WIDTH 1u
#define CSC0_PERP_CTRL_CMU3_RST_EN(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_CMU3_RST_EN_SHIFT))&CSC0_PERP_CTRL_CMU3_RST_EN_MASK)
#define CSC0_PERP_CTRL_CMU4_LOC_EN_MASK 0x20u
#define CSC0_PERP_CTRL_CMU4_LOC_EN_SHIFT 5u
#define CSC0_PERP_CTRL_CMU4_LOC_EN_WIDTH 1u
#define CSC0_PERP_CTRL_CMU4_LOC_EN(x)  (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_CMU4_LOC_EN_SHIFT))&CSC0_PERP_CTRL_CMU4_LOC_EN_MASK)
#define CSC0_PERP_CTRL_LOCK_MASK       0x1u
#define CSC0_PERP_CTRL_LOCK_SHIFT      0u
#define CSC0_PERP_CTRL_LOCK_WIDTH      1u
#define CSC0_PERP_CTRL_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_PERP_CTRL_LOCK_SHIFT))&CSC0_PERP_CTRL_LOCK_MASK)
/* PERP_CTRL Reg Mask */
#define CSC0_PERP_CTRL_MASK            0x70010321u

/* SMU_CTRL5 Bit Fields */
#define CSC0_SMU_CTRL5_SRAM2_EDC_MASK  0x40000000u
#define CSC0_SMU_CTRL5_SRAM2_EDC_SHIFT 30u
#define CSC0_SMU_CTRL5_SRAM2_EDC_WIDTH 1u
#define CSC0_SMU_CTRL5_SRAM2_EDC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_SRAM2_EDC_SHIFT))&CSC0_SMU_CTRL5_SRAM2_EDC_MASK)
#define CSC0_SMU_CTRL5_SRAM1_EDC_MASK  0x20000000u
#define CSC0_SMU_CTRL5_SRAM1_EDC_SHIFT 29u
#define CSC0_SMU_CTRL5_SRAM1_EDC_WIDTH 1u
#define CSC0_SMU_CTRL5_SRAM1_EDC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_SRAM1_EDC_SHIFT))&CSC0_SMU_CTRL5_SRAM1_EDC_MASK)
#define CSC0_SMU_CTRL5_SRAM0_EDC_MASK  0x10000000u
#define CSC0_SMU_CTRL5_SRAM0_EDC_SHIFT 28u
#define CSC0_SMU_CTRL5_SRAM0_EDC_WIDTH 1u
#define CSC0_SMU_CTRL5_SRAM0_EDC(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_SRAM0_EDC_SHIFT))&CSC0_SMU_CTRL5_SRAM0_EDC_MASK)
#define CSC0_SMU_CTRL5_FLASH_EDC_HI_EN_MASK 0x2000000u
#define CSC0_SMU_CTRL5_FLASH_EDC_HI_EN_SHIFT 25u
#define CSC0_SMU_CTRL5_FLASH_EDC_HI_EN_WIDTH 1u
#define CSC0_SMU_CTRL5_FLASH_EDC_HI_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FLASH_EDC_HI_EN_SHIFT))&CSC0_SMU_CTRL5_FLASH_EDC_HI_EN_MASK)
#define CSC0_SMU_CTRL5_FLASH_EDC_EN_MASK 0x1000000u
#define CSC0_SMU_CTRL5_FLASH_EDC_EN_SHIFT 24u
#define CSC0_SMU_CTRL5_FLASH_EDC_EN_WIDTH 1u
#define CSC0_SMU_CTRL5_FLASH_EDC_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FLASH_EDC_EN_SHIFT))&CSC0_SMU_CTRL5_FLASH_EDC_EN_MASK)
#define CSC0_SMU_CTRL5_HSM_IRAM_S_MASK 0x800000u
#define CSC0_SMU_CTRL5_HSM_IRAM_S_SHIFT 23u
#define CSC0_SMU_CTRL5_HSM_IRAM_S_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_IRAM_S(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_IRAM_S_SHIFT))&CSC0_SMU_CTRL5_HSM_IRAM_S_MASK)
#define CSC0_SMU_CTRL5_HSM_DRAM_S_MASK 0x400000u
#define CSC0_SMU_CTRL5_HSM_DRAM_S_SHIFT 22u
#define CSC0_SMU_CTRL5_HSM_DRAM_S_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_DRAM_S(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_DRAM_S_SHIFT))&CSC0_SMU_CTRL5_HSM_DRAM_S_MASK)
#define CSC0_SMU_CTRL5_HSM_IRAM_MASK   0x200000u
#define CSC0_SMU_CTRL5_HSM_IRAM_SHIFT  21u
#define CSC0_SMU_CTRL5_HSM_IRAM_WIDTH  1u
#define CSC0_SMU_CTRL5_HSM_IRAM(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_IRAM_SHIFT))&CSC0_SMU_CTRL5_HSM_IRAM_MASK)
#define CSC0_SMU_CTRL5_HSM_DRAM_MASK   0x100000u
#define CSC0_SMU_CTRL5_HSM_DRAM_SHIFT  20u
#define CSC0_SMU_CTRL5_HSM_DRAM_WIDTH  1u
#define CSC0_SMU_CTRL5_HSM_DRAM(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_DRAM_SHIFT))&CSC0_SMU_CTRL5_HSM_DRAM_MASK)
#define CSC0_SMU_CTRL5_DMA0_ECC_S_MASK 0x10000u
#define CSC0_SMU_CTRL5_DMA0_ECC_S_SHIFT 16u
#define CSC0_SMU_CTRL5_DMA0_ECC_S_WIDTH 1u
#define CSC0_SMU_CTRL5_DMA0_ECC_S(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_ECC_S_SHIFT))&CSC0_SMU_CTRL5_DMA0_ECC_S_MASK)
#define CSC0_SMU_CTRL5_DMA0_ECC_MASK   0x4000u
#define CSC0_SMU_CTRL5_DMA0_ECC_SHIFT  14u
#define CSC0_SMU_CTRL5_DMA0_ECC_WIDTH  1u
#define CSC0_SMU_CTRL5_DMA0_ECC(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_ECC_SHIFT))&CSC0_SMU_CTRL5_DMA0_ECC_MASK)
#define CSC0_SMU_CTRL5_DMA0_LS_MASK    0x1000u
#define CSC0_SMU_CTRL5_DMA0_LS_SHIFT   12u
#define CSC0_SMU_CTRL5_DMA0_LS_WIDTH   1u
#define CSC0_SMU_CTRL5_DMA0_LS(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_LS_SHIFT))&CSC0_SMU_CTRL5_DMA0_LS_MASK)
#define CSC0_SMU_CTRL5_FOSC_LOC_ERR_MASK 0x400u
#define CSC0_SMU_CTRL5_FOSC_LOC_ERR_SHIFT 10u
#define CSC0_SMU_CTRL5_FOSC_LOC_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_FOSC_LOC_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FOSC_LOC_ERR_SHIFT))&CSC0_SMU_CTRL5_FOSC_LOC_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL1_LOC_ERR_MASK 0x200u
#define CSC0_SMU_CTRL5_PLL1_LOC_ERR_SHIFT 9u
#define CSC0_SMU_CTRL5_PLL1_LOC_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL1_LOC_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL1_LOC_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL1_LOC_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL0_LOC_ERR_MASK 0x100u
#define CSC0_SMU_CTRL5_PLL0_LOC_ERR_SHIFT 8u
#define CSC0_SMU_CTRL5_PLL0_LOC_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL0_LOC_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL0_LOC_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL0_LOC_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL1_LOL_ERR_MASK 0x80u
#define CSC0_SMU_CTRL5_PLL1_LOL_ERR_SHIFT 7u
#define CSC0_SMU_CTRL5_PLL1_LOL_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL1_LOL_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL1_LOL_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL1_LOL_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL0_LOL_ERR_MASK 0x40u
#define CSC0_SMU_CTRL5_PLL0_LOL_ERR_SHIFT 6u
#define CSC0_SMU_CTRL5_PLL0_LOL_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL0_LOL_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL0_LOL_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL0_LOL_ERR_MASK)
#define CSC0_SMU_CTRL5_STCU_ERR_MASK   0x10u
#define CSC0_SMU_CTRL5_STCU_ERR_SHIFT  4u
#define CSC0_SMU_CTRL5_STCU_ERR_WIDTH  1u
#define CSC0_SMU_CTRL5_STCU_ERR(x)     (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_STCU_ERR_SHIFT))&CSC0_SMU_CTRL5_STCU_ERR_MASK)
#define CSC0_SMU_CTRL5_NONUSER_MASK    0x4u
#define CSC0_SMU_CTRL5_NONUSER_SHIFT   2u
#define CSC0_SMU_CTRL5_NONUSER_WIDTH   1u
#define CSC0_SMU_CTRL5_NONUSER(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_NONUSER_SHIFT))&CSC0_SMU_CTRL5_NONUSER_MASK)
#define CSC0_SMU_CTRL5_NVR_ERR_MASK    0x2u
#define CSC0_SMU_CTRL5_NVR_ERR_SHIFT   1u
#define CSC0_SMU_CTRL5_NVR_ERR_WIDTH   1u
#define CSC0_SMU_CTRL5_NVR_ERR(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_NVR_ERR_SHIFT))&CSC0_SMU_CTRL5_NVR_ERR_MASK)
#define CSC0_SMU_CTRL5_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL5_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL5_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL5_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_LOCK_SHIFT))&CSC0_SMU_CTRL5_LOCK_MASK)
/* SMU_CTRL5 Reg Mask */
#define CSC0_SMU_CTRL5_MASK            0x73F157D7u

/* SMU_CTRL6 Bit Fields */
#define CSC0_SMU_CTRL6_MAM1_CHK_ERR_MASK 0x2000000u
#define CSC0_SMU_CTRL6_MAM1_CHK_ERR_SHIFT 25u
#define CSC0_SMU_CTRL6_MAM1_CHK_ERR_WIDTH 1u
#define CSC0_SMU_CTRL6_MAM1_CHK_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM1_CHK_ERR_SHIFT))&CSC0_SMU_CTRL6_MAM1_CHK_ERR_MASK)
#define CSC0_SMU_CTRL6_MAM0_CHK_ERR_MASK 0x1000000u
#define CSC0_SMU_CTRL6_MAM0_CHK_ERR_SHIFT 24u
#define CSC0_SMU_CTRL6_MAM0_CHK_ERR_WIDTH 1u
#define CSC0_SMU_CTRL6_MAM0_CHK_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM0_CHK_ERR_SHIFT))&CSC0_SMU_CTRL6_MAM0_CHK_ERR_MASK)
#define CSC0_SMU_CTRL6_MAM0_S8_DS_MASK 0x100000u
#define CSC0_SMU_CTRL6_MAM0_S8_DS_SHIFT 20u
#define CSC0_SMU_CTRL6_MAM0_S8_DS_WIDTH 1u
#define CSC0_SMU_CTRL6_MAM0_S8_DS(x)   (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM0_S8_DS_SHIFT))&CSC0_SMU_CTRL6_MAM0_S8_DS_MASK)
#define CSC0_SMU_CTRL6_AFCB0_PD0_MON_MASK 0x10000u
#define CSC0_SMU_CTRL6_AFCB0_PD0_MON_SHIFT 16u
#define CSC0_SMU_CTRL6_AFCB0_PD0_MON_WIDTH 1u
#define CSC0_SMU_CTRL6_AFCB0_PD0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_AFCB0_PD0_MON_SHIFT))&CSC0_SMU_CTRL6_AFCB0_PD0_MON_MASK)
#define CSC0_SMU_CTRL6_MAM0_S8_S2F_MON_MASK 0x1000u
#define CSC0_SMU_CTRL6_MAM0_S8_S2F_MON_SHIFT 12u
#define CSC0_SMU_CTRL6_MAM0_S8_S2F_MON_WIDTH 1u
#define CSC0_SMU_CTRL6_MAM0_S8_S2F_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM0_S8_S2F_MON_SHIFT))&CSC0_SMU_CTRL6_MAM0_S8_S2F_MON_MASK)
#define CSC0_SMU_CTRL6_MAM1_S3_MASK    0x10u
#define CSC0_SMU_CTRL6_MAM1_S3_SHIFT   4u
#define CSC0_SMU_CTRL6_MAM1_S3_WIDTH   1u
#define CSC0_SMU_CTRL6_MAM1_S3(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM1_S3_SHIFT))&CSC0_SMU_CTRL6_MAM1_S3_MASK)
#define CSC0_SMU_CTRL6_MAM0_S8_MASK    0x2u
#define CSC0_SMU_CTRL6_MAM0_S8_SHIFT   1u
#define CSC0_SMU_CTRL6_MAM0_S8_WIDTH   1u
#define CSC0_SMU_CTRL6_MAM0_S8(x)      (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_MAM0_S8_SHIFT))&CSC0_SMU_CTRL6_MAM0_S8_MASK)
#define CSC0_SMU_CTRL6_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL6_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL6_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL6_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL6_LOCK_SHIFT))&CSC0_SMU_CTRL6_LOCK_MASK)
/* SMU_CTRL6 Reg Mask */
#define CSC0_SMU_CTRL6_MASK            0x03111013u

/* SMU_CTRL8 Bit Fields */
#define CSC0_SMU_CTRL8_ADC1_CMP2_MASK  0x10u
#define CSC0_SMU_CTRL8_ADC1_CMP2_SHIFT 4u
#define CSC0_SMU_CTRL8_ADC1_CMP2_WIDTH 1u
#define CSC0_SMU_CTRL8_ADC1_CMP2(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL8_ADC1_CMP2_SHIFT))&CSC0_SMU_CTRL8_ADC1_CMP2_MASK)
#define CSC0_SMU_CTRL8_ADC1_CMP1_MASK  0x8u
#define CSC0_SMU_CTRL8_ADC1_CMP1_SHIFT 3u
#define CSC0_SMU_CTRL8_ADC1_CMP1_WIDTH 1u
#define CSC0_SMU_CTRL8_ADC1_CMP1(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL8_ADC1_CMP1_SHIFT))&CSC0_SMU_CTRL8_ADC1_CMP1_MASK)
#define CSC0_SMU_CTRL8_ADC0_CMP2_MASK  0x4u
#define CSC0_SMU_CTRL8_ADC0_CMP2_SHIFT 2u
#define CSC0_SMU_CTRL8_ADC0_CMP2_WIDTH 1u
#define CSC0_SMU_CTRL8_ADC0_CMP2(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL8_ADC0_CMP2_SHIFT))&CSC0_SMU_CTRL8_ADC0_CMP2_MASK)
#define CSC0_SMU_CTRL8_ADC0_CMP1_MASK  0x2u
#define CSC0_SMU_CTRL8_ADC0_CMP1_SHIFT 1u
#define CSC0_SMU_CTRL8_ADC0_CMP1_WIDTH 1u
#define CSC0_SMU_CTRL8_ADC0_CMP1(x)    (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL8_ADC0_CMP1_SHIFT))&CSC0_SMU_CTRL8_ADC0_CMP1_MASK)
#define CSC0_SMU_CTRL8_LOCK_MASK       0x1u
#define CSC0_SMU_CTRL8_LOCK_SHIFT      0u
#define CSC0_SMU_CTRL8_LOCK_WIDTH      1u
#define CSC0_SMU_CTRL8_LOCK(x)         (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL8_LOCK_SHIFT))&CSC0_SMU_CTRL8_LOCK_MASK)
/* SMU_CTRL8 Reg Mask */
#define CSC0_SMU_CTRL8_MASK            0x0000001Fu

/* PCC_CFG Bit Fields */
#define CSC0_PCC_CFG_DWP_FORCE_CPU0_MASK 0x1u
#define CSC0_PCC_CFG_DWP_FORCE_CPU0_SHIFT 0u
#define CSC0_PCC_CFG_DWP_FORCE_CPU0_WIDTH 1u
#define CSC0_PCC_CFG_DWP_FORCE_CPU0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PCC_CFG_DWP_FORCE_CPU0_SHIFT))&CSC0_PCC_CFG_DWP_FORCE_CPU0_MASK)
/* PCC_CFG Reg Mask */
#define CSC0_PCC_CFG_MASK              0x00000001u


/*!
 * @}
 */ /* end of group CSC0_Register_Masks */

/*!
 * @}
 */ /* end of group CSC0_Peripheral_Access_Layer */

#endif
