382 lines
8.5 KiB
C
382 lines
8.5 KiB
C
#ifndef _FC7240_RTC_NU_Tztufn39_REGS_H_
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#define _FC7240_RTC_NU_Tztufn39_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- RTC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
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* @{
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*/
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/** RTC - Size of Registers Arrays */
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/** RTC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t SR ; /* Seconds Register, offset: 0x0 */
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__IO uint32_t PR ; /* Prescaler Register, offset: 0x4 */
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__IO uint32_t AR ; /* Alarm Register, offset: 0x8 */
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__IO uint32_t COMPR ; /* Compensation Register, offset: 0xC */
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__IO uint32_t CR ; /* Control Register, offset: 0x10 */
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__IO uint32_t STR ; /* Status Register, offset: 0x14 */
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__IO uint32_t LR ; /* Lock Register, offset: 0x18 */
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__IO uint32_t IER ; /* Interrupt Enable Register, offset: 0x1C */
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} RTC_Type, *RTC_MemMapPtr;
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/** Number of instances of the RTC module. */
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#define RTC_INSTANCE_COUNT (1u)
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/* RTC - Peripheral instance base addresses */
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/** Peripheral RTC base address */
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#define RTC_BASE (0x40030000u)
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/** Peripheral RTC base pointer */
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#define RTC ((RTC_Type *)RTC_BASE)
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/** Array initializer of RTC peripheral base addresses */
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#define RTC_BASE_ADDRS {RTC_BASE}
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/** Array initializer of RTC peripheral base pointers */
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#define RTC_BASE_PTRS {RTC}
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// need fill by yourself
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///** Number of interrupt vector arrays for the RTC module. */
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//#define RTC_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the RTC module. */
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//#define RTC_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the RTC peripheral type */
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//#define RTC_IRQS {RTC_IRQn}
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/* ----------------------------------------------------------------------------
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-- RTC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup RTC_Register_Masks RTC Register Masks
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* @{
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*/
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/* SR Bit Fields */
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#define RTC_SR_TSR_MASK 0xFFFFFFFFu
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#define RTC_SR_TSR_SHIFT 0u
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#define RTC_SR_TSR_WIDTH 32u
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#define RTC_SR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TSR_SHIFT))&RTC_SR_TSR_MASK)
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/* SR Reg Mask */
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#define RTC_SR_MASK 0xFFFFFFFFu
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/* PR Bit Fields */
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#define RTC_PR_TPR_MASK 0xFFFFu
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#define RTC_PR_TPR_SHIFT 0u
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#define RTC_PR_TPR_WIDTH 16u
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#define RTC_PR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_PR_TPR_SHIFT))&RTC_PR_TPR_MASK)
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/* PR Reg Mask */
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#define RTC_PR_MASK 0x0000FFFFu
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/* AR Bit Fields */
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#define RTC_AR_TAR_MASK 0xFFFFFFFFu
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#define RTC_AR_TAR_SHIFT 0u
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#define RTC_AR_TAR_WIDTH 32u
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#define RTC_AR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_AR_TAR_SHIFT))&RTC_AR_TAR_MASK)
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/* AR Reg Mask */
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#define RTC_AR_MASK 0xFFFFFFFFu
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/* COMPR Bit Fields */
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#define RTC_COMPR_CIC_MASK 0xFF000000u
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#define RTC_COMPR_CIC_SHIFT 24u
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#define RTC_COMPR_CIC_WIDTH 8u
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#define RTC_COMPR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_CIC_SHIFT))&RTC_COMPR_CIC_MASK)
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#define RTC_COMPR_TCV_MASK 0xFF0000u
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#define RTC_COMPR_TCV_SHIFT 16u
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#define RTC_COMPR_TCV_WIDTH 8u
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#define RTC_COMPR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_TCV_SHIFT))&RTC_COMPR_TCV_MASK)
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#define RTC_COMPR_CIR_MASK 0xFF00u
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#define RTC_COMPR_CIR_SHIFT 8u
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#define RTC_COMPR_CIR_WIDTH 8u
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#define RTC_COMPR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_CIR_SHIFT))&RTC_COMPR_CIR_MASK)
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#define RTC_COMPR_TCR_MASK 0xFFu
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#define RTC_COMPR_TCR_SHIFT 0u
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#define RTC_COMPR_TCR_WIDTH 8u
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#define RTC_COMPR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_TCR_SHIFT))&RTC_COMPR_TCR_MASK)
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/* COMPR Reg Mask */
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#define RTC_COMPR_MASK 0xFFFFFFFFu
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/* CR Bit Fields */
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#define RTC_CR_CKO_MASK 0x200u
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#define RTC_CR_CKO_SHIFT 9u
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#define RTC_CR_CKO_WIDTH 1u
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#define RTC_CR_CKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CKO_SHIFT))&RTC_CR_CKO_MASK)
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#define RTC_CR_CKPS_MASK 0x20u
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#define RTC_CR_CKPS_SHIFT 5u
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#define RTC_CR_CKPS_WIDTH 1u
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#define RTC_CR_CKPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CKPS_SHIFT))&RTC_CR_CKPS_MASK)
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#define RTC_CR_UM_MASK 0x8u
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#define RTC_CR_UM_SHIFT 3u
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#define RTC_CR_UM_WIDTH 1u
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#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
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#define RTC_CR_SWRST_MASK 0x1u
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#define RTC_CR_SWRST_SHIFT 0u
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#define RTC_CR_SWRST_WIDTH 1u
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#define RTC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWRST_SHIFT))&RTC_CR_SWRST_MASK)
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/* CR Reg Mask */
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#define RTC_CR_MASK 0x00000229u
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/* STR Bit Fields */
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#define RTC_STR_TCE_MASK 0x10u
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#define RTC_STR_TCE_SHIFT 4u
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#define RTC_STR_TCE_WIDTH 1u
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#define RTC_STR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TCE_SHIFT))&RTC_STR_TCE_MASK)
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#define RTC_STR_TAF_MASK 0x4u
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#define RTC_STR_TAF_SHIFT 2u
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#define RTC_STR_TAF_WIDTH 1u
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#define RTC_STR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TAF_SHIFT))&RTC_STR_TAF_MASK)
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#define RTC_STR_TOF_MASK 0x2u
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#define RTC_STR_TOF_SHIFT 1u
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#define RTC_STR_TOF_WIDTH 1u
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#define RTC_STR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TOF_SHIFT))&RTC_STR_TOF_MASK)
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/* STR Reg Mask */
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#define RTC_STR_MASK 0x00000016u
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/* LR Bit Fields */
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#define RTC_LR_LRL_MASK 0x40u
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#define RTC_LR_LRL_SHIFT 6u
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#define RTC_LR_LRL_WIDTH 1u
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#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
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#define RTC_LR_STRL_MASK 0x20u
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#define RTC_LR_STRL_SHIFT 5u
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#define RTC_LR_STRL_WIDTH 1u
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#define RTC_LR_STRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_STRL_SHIFT))&RTC_LR_STRL_MASK)
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#define RTC_LR_CRL_MASK 0x10u
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#define RTC_LR_CRL_SHIFT 4u
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#define RTC_LR_CRL_WIDTH 1u
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#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
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#define RTC_LR_CPL_MASK 0x8u
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#define RTC_LR_CPL_SHIFT 3u
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#define RTC_LR_CPL_WIDTH 1u
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#define RTC_LR_CPL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CPL_SHIFT))&RTC_LR_CPL_MASK)
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/* LR Reg Mask */
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#define RTC_LR_MASK 0x00000078u
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/* IER Bit Fields */
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#define RTC_IER_TSIC_MASK 0x70000u
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#define RTC_IER_TSIC_SHIFT 16u
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#define RTC_IER_TSIC_WIDTH 3u
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#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
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#define RTC_IER_TSIE_MASK 0x10u
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#define RTC_IER_TSIE_SHIFT 4u
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#define RTC_IER_TSIE_WIDTH 1u
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#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
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#define RTC_IER_TAIE_MASK 0x4u
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#define RTC_IER_TAIE_SHIFT 2u
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#define RTC_IER_TAIE_WIDTH 1u
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#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
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#define RTC_IER_TOIE_MASK 0x2u
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#define RTC_IER_TOIE_SHIFT 1u
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#define RTC_IER_TOIE_WIDTH 1u
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#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
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/* IER Reg Mask */
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#define RTC_IER_MASK 0x00070016u
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/*!
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* @}
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*/ /* end of group RTC_Register_Masks */
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/*!
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* @}
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*/ /* end of group RTC_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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