414 lines
11 KiB
C
414 lines
11 KiB
C
#ifndef _FC7240_PTIMER_NU_Tztufn31_REGS_H_
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#define _FC7240_PTIMER_NU_Tztufn31_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- PTIMER Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PTIMER_Peripheral_Access_Layer PTIMER Peripheral Access Layer
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* @{
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*/
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/** PTIMER - Size of Registers Arrays */
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#define PTIMER_CH_CNT 4u
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#define PTIMER_CH_DLY_CNT 8u
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#define PTIMER_DLY_CNT (PTIMER_CH_CNT * PTIMER_CH_DLY_CNT)
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/** PTIMER - Register Layout Typedef */
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typedef struct {
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__IO uint32_t STATUS_CTRL ; /* Status and Control Register, offset: 0x0 */
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__IO uint32_t MAX_CNT ; /* Max Count Number Register, offset: 0x4 */
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__IO uint32_t CNT ; /* Counter Register, offset: 0x8 */
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__IO uint32_t INT_DLY ; /* Interrupt Delay Register, offset: 0xC */
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struct{
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__IO uint32_t CTRL ; /* Channel n Control register 1, array offset: 0x10, array step: 0x28 */
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__IO uint32_t STATUS ; /* Channel n Status register, array offset: 0x14, array step: 0x28 */
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__IO uint32_t DLY[PTIMER_CH_DLY_CNT] ; /* Channel n Delay 0 register..Channel n Delay 7 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
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} CH[PTIMER_CH_CNT] ; /* Channel n registers, array offset: 0x10, array step: 0x28 */
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uint8_t RESERVED_0[224];
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__IO uint32_t POEN ; /* Pulse-Out Enable Register, offset: 0x190 */
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__IO uint32_t PODLY ; /* Pulse-Out Delay Register, offset: 0x194 */
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} PTIMER_Type, *PTIMER_MemMapPtr;
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/** Number of instances of the PTIMER module. */
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#define PTIMER_INSTANCE_COUNT (2u)
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/* PTIMER - Peripheral instance base addresses */
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/** Peripheral PTIMER0 base address */
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#define PTIMER0_BASE (0x40037000u)
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/** Peripheral PTIMER0 base pointer */
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#define PTIMER0 ((PTIMER_Type *)PTIMER0_BASE)
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/** Peripheral PTIMER1 base address */
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#define PTIMER1_BASE (0x40038000u)
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/** Peripheral PTIMER1 base pointer */
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#define PTIMER1 ((PTIMER_Type *)PTIMER1_BASE)
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/** Array initializer of PTIMER peripheral base addresses */
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#define PTIMER_BASE_ADDRS {PTIMER0_BASE, PTIMER1_BASE}
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/** Array initializer of PTIMER peripheral base pointers */
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#define PTIMER_BASE_PTRS {PTIMER0, PTIMER1}
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// need fill by yourself
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///** Number of interrupt vector arrays for the PTIMER module. */
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//#define PTIMER_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the PTIMER module. */
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//#define PTIMER_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the PTIMER peripheral type */
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//#define PTIMER_IRQS {PTIMER0_IRQn, PTIMER1_IRQn}
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/* ----------------------------------------------------------------------------
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-- PTIMER Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PTIMER_Register_Masks PTIMER Register Masks
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* @{
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*/
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/* STATUS_CTRL Bit Fields */
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#define PTIMER_STATUS_CTRL_LDMODE_MASK 0xC0000u
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#define PTIMER_STATUS_CTRL_LDMODE_SHIFT 18u
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#define PTIMER_STATUS_CTRL_LDMODE_WIDTH 2u
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#define PTIMER_STATUS_CTRL_LDMODE(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_LDMODE_SHIFT))&PTIMER_STATUS_CTRL_LDMODE_MASK)
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#define PTIMER_STATUS_CTRL_SERR_INTEN_MASK 0x20000u
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#define PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT 17u
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#define PTIMER_STATUS_CTRL_SERR_INTEN_WIDTH 1u
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#define PTIMER_STATUS_CTRL_SERR_INTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT))&PTIMER_STATUS_CTRL_SERR_INTEN_MASK)
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#define PTIMER_STATUS_CTRL_SWTRG_MASK 0x10000u
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#define PTIMER_STATUS_CTRL_SWTRG_SHIFT 16u
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#define PTIMER_STATUS_CTRL_SWTRG_WIDTH 1u
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#define PTIMER_STATUS_CTRL_SWTRG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_SWTRG_SHIFT))&PTIMER_STATUS_CTRL_SWTRG_MASK)
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#define PTIMER_STATUS_CTRL_DMAEN_MASK 0x8000u
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#define PTIMER_STATUS_CTRL_DMAEN_SHIFT 15u
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#define PTIMER_STATUS_CTRL_DMAEN_WIDTH 1u
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#define PTIMER_STATUS_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_DMAEN_SHIFT))&PTIMER_STATUS_CTRL_DMAEN_MASK)
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#define PTIMER_STATUS_CTRL_PRESCALER_MASK 0x7000u
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#define PTIMER_STATUS_CTRL_PRESCALER_SHIFT 12u
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#define PTIMER_STATUS_CTRL_PRESCALER_WIDTH 3u
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#define PTIMER_STATUS_CTRL_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_PRESCALER_SHIFT))&PTIMER_STATUS_CTRL_PRESCALER_MASK)
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#define PTIMER_STATUS_CTRL_TRGSEL_MASK 0xF00u
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#define PTIMER_STATUS_CTRL_TRGSEL_SHIFT 8u
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#define PTIMER_STATUS_CTRL_TRGSEL_WIDTH 4u
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#define PTIMER_STATUS_CTRL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_TRGSEL_SHIFT))&PTIMER_STATUS_CTRL_TRGSEL_MASK)
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#define PTIMER_STATUS_CTRL_ENABLE_MASK 0x80u
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#define PTIMER_STATUS_CTRL_ENABLE_SHIFT 7u
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#define PTIMER_STATUS_CTRL_ENABLE_WIDTH 1u
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#define PTIMER_STATUS_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_ENABLE_SHIFT))&PTIMER_STATUS_CTRL_ENABLE_MASK)
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#define PTIMER_STATUS_CTRL_INTFLAG_MASK 0x40u
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#define PTIMER_STATUS_CTRL_INTFLAG_SHIFT 6u
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#define PTIMER_STATUS_CTRL_INTFLAG_WIDTH 1u
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#define PTIMER_STATUS_CTRL_INTFLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_INTFLAG_SHIFT))&PTIMER_STATUS_CTRL_INTFLAG_MASK)
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#define PTIMER_STATUS_CTRL_INTEN_MASK 0x20u
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#define PTIMER_STATUS_CTRL_INTEN_SHIFT 5u
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#define PTIMER_STATUS_CTRL_INTEN_WIDTH 1u
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#define PTIMER_STATUS_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_INTEN_SHIFT))&PTIMER_STATUS_CTRL_INTEN_MASK)
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#define PTIMER_STATUS_CTRL_MULT_MASK 0xCu
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#define PTIMER_STATUS_CTRL_MULT_SHIFT 2u
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#define PTIMER_STATUS_CTRL_MULT_WIDTH 2u
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#define PTIMER_STATUS_CTRL_MULT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_MULT_SHIFT))&PTIMER_STATUS_CTRL_MULT_MASK)
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#define PTIMER_STATUS_CTRL_CONT_MASK 0x2u
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#define PTIMER_STATUS_CTRL_CONT_SHIFT 1u
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#define PTIMER_STATUS_CTRL_CONT_WIDTH 1u
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#define PTIMER_STATUS_CTRL_CONT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_CONT_SHIFT))&PTIMER_STATUS_CTRL_CONT_MASK)
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#define PTIMER_STATUS_CTRL_LDOK_MASK 0x1u
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#define PTIMER_STATUS_CTRL_LDOK_SHIFT 0u
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#define PTIMER_STATUS_CTRL_LDOK_WIDTH 1u
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#define PTIMER_STATUS_CTRL_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_LDOK_SHIFT))&PTIMER_STATUS_CTRL_LDOK_MASK)
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/* STATUS_CTRL Reg Mask */
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#define PTIMER_STATUS_CTRL_MASK 0x000FFFEFu
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/* MAX_CNT Bit Fields */
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#define PTIMER_MAX_CNT_MAX_CNT_MASK 0xFFFFu
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#define PTIMER_MAX_CNT_MAX_CNT_SHIFT 0u
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#define PTIMER_MAX_CNT_MAX_CNT_WIDTH 16u
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#define PTIMER_MAX_CNT_MAX_CNT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_MAX_CNT_MAX_CNT_SHIFT))&PTIMER_MAX_CNT_MAX_CNT_MASK)
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/* MAX_CNT Reg Mask */
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#define PTIMER_MAX_CNT_MASK 0x0000FFFFu
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/* CNT Bit Fields */
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#define PTIMER_CNT_CNT_MASK 0xFFFFu
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#define PTIMER_CNT_CNT_SHIFT 0u
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#define PTIMER_CNT_CNT_WIDTH 16u
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#define PTIMER_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CNT_CNT_SHIFT))&PTIMER_CNT_CNT_MASK)
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/* CNT Reg Mask */
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#define PTIMER_CNT_MASK 0x0000FFFFu
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/* INT_DLY Bit Fields */
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#define PTIMER_INT_DLY_INT_DLY_MASK 0xFFFFu
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#define PTIMER_INT_DLY_INT_DLY_SHIFT 0u
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#define PTIMER_INT_DLY_INT_DLY_WIDTH 16u
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#define PTIMER_INT_DLY_INT_DLY(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_INT_DLY_INT_DLY_SHIFT))&PTIMER_INT_DLY_INT_DLY_MASK)
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/* INT_DLY Reg Mask */
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#define PTIMER_INT_DLY_MASK 0x0000FFFFu
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/* CTRL_CH Bit Fields */
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#define PTIMER_CTRL_CH_BTB_MASK 0xFF0000u
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#define PTIMER_CTRL_CH_BTB_SHIFT 16u
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#define PTIMER_CTRL_CH_BTB_WIDTH 8u
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#define PTIMER_CTRL_CH_BTB(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_BTB_SHIFT))&PTIMER_CTRL_CH_BTB_MASK)
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#define PTIMER_CTRL_CH_PTOS_MASK 0xFF00u
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#define PTIMER_CTRL_CH_PTOS_SHIFT 8u
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#define PTIMER_CTRL_CH_PTOS_WIDTH 8u
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#define PTIMER_CTRL_CH_PTOS(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_PTOS_SHIFT))&PTIMER_CTRL_CH_PTOS_MASK)
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#define PTIMER_CTRL_CH_PTEN_MASK 0xFFu
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#define PTIMER_CTRL_CH_PTEN_SHIFT 0u
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#define PTIMER_CTRL_CH_PTEN_WIDTH 8u
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#define PTIMER_CTRL_CH_PTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_PTEN_SHIFT))&PTIMER_CTRL_CH_PTEN_MASK)
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/* CTRL_CH Reg Mask */
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#define PTIMER_CTRL_CH_MASK 0x00FFFFFFu
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/* STATUS_CH Bit Fields */
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#define PTIMER_STATUS_CH_CHN_FLAG_MASK 0xFF0000u
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#define PTIMER_STATUS_CH_CHN_FLAG_SHIFT 16u
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#define PTIMER_STATUS_CH_CHN_FLAG_WIDTH 8u
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#define PTIMER_STATUS_CH_CHN_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CH_CHN_FLAG_SHIFT))&PTIMER_STATUS_CH_CHN_FLAG_MASK)
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#define PTIMER_STATUS_CH_SERR_FLAG_MASK 0xFFu
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#define PTIMER_STATUS_CH_SERR_FLAG_SHIFT 0u
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#define PTIMER_STATUS_CH_SERR_FLAG_WIDTH 8u
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#define PTIMER_STATUS_CH_SERR_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CH_SERR_FLAG_SHIFT))&PTIMER_STATUS_CH_SERR_FLAG_MASK)
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/* STATUS_CH Reg Mask */
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#define PTIMER_STATUS_CH_MASK 0x00FF00FFu
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/* DLYn_CHm Bit Fields */
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#define PTIMER_DLY_CH_CHNDLY_MASK 0xFFFFu
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#define PTIMER_DLY_CH_CHNDLY_SHIFT 0u
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#define PTIMER_DLY_CH_CHNDLY_WIDTH 16u
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#define PTIMER_DLY_CH_CHNDLY(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_DLY_CH_CHNDLY_SHIFT))&PTIMER_DLY_CH_CHNDLY_MASK)
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/* DLYn_CHm Reg Mask */
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#define PTIMER_DLY_CH_MASK 0x0000FFFFu
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/* POEN Bit Fields */
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#define PTIMER_POEN_POEN_MASK 0x1u
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#define PTIMER_POEN_POEN_SHIFT 0u
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#define PTIMER_POEN_POEN_WIDTH 1u
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#define PTIMER_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_POEN_POEN_SHIFT))&PTIMER_POEN_POEN_MASK)
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/* POEN Reg Mask */
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#define PTIMER_POEN_MASK 0x00000001u
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/* PODLY Bit Fields */
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#define PTIMER_PODLY_DLY1_MASK 0xFFFF0000u
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#define PTIMER_PODLY_DLY1_SHIFT 16u
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#define PTIMER_PODLY_DLY1_WIDTH 16u
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#define PTIMER_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_PODLY_DLY1_SHIFT))&PTIMER_PODLY_DLY1_MASK)
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#define PTIMER_PODLY_DLY2_MASK 0xFFFFu
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#define PTIMER_PODLY_DLY2_SHIFT 0u
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#define PTIMER_PODLY_DLY2_WIDTH 16u
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#define PTIMER_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_PODLY_DLY2_SHIFT))&PTIMER_PODLY_DLY2_MASK)
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/* PODLY Reg Mask */
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#define PTIMER_PODLY_MASK 0xFFFFFFFFu
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/*!
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* @}
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*/ /* end of group PTIMER_Register_Masks */
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/*!
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* @}
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*/ /* end of group PTIMER_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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