499 lines
12 KiB
C
499 lines
12 KiB
C
#ifndef _FC7240_PORT_NU_Tztufn47_REGS_H_
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#define _FC7240_PORT_NU_Tztufn47_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- PORT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
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* @{
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*/
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/** PORT - Size of Registers Arrays */
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/** PORT - Register Layout Typedef */
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#define PORT_PCR_COUNT 32
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typedef struct {
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__IO uint32_t PCR[PORT_PCR_COUNT] ; /* Port Control Register, offset: 0x0 */
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__O uint32_t GPCLR ; /* Global Pin Control Low Register, offset: 0x80 */
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__O uint32_t GPCHR ; /* Global Pin Control High Register, offset: 0x84 */
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__O uint32_t GICLR ; /* Global Interrupt Control Low Register, offset: 0x88 */
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__O uint32_t GICHR ; /* Global Interrupt Control High Register, offset: 0x8C */
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uint8_t RESERVED_0[16];
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__IO uint32_t ISFR ; /* Interrupt Status Flag Register, offset: 0xA0 */
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uint8_t RESERVED_1[28];
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__IO uint32_t DFER ; /* Digital Filter Enable Register, offset: 0xC0 */
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__IO uint32_t DFCR ; /* Digital Filter Clock Register, offset: 0xC4 */
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__IO uint32_t DFWR ; /* Digital Filter Width Register, offset: 0xC8 */
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__IO uint32_t GLDWP ; /* Global Domain Write Protection Register, offset: 0xCC */
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} PORT_Type, *PORT_MemMapPtr;
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/** Number of instances of the PORT module. */
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#define PORT_INSTANCE_COUNT (5u)
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/* PORT - Peripheral instance base addresses */
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/** Peripheral PORTA base address */
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#define PORTA_BASE (0x40047000u)
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/** Peripheral PORTA base pointer */
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#define PORTA ((PORT_Type *)PORTA_BASE)
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/** Peripheral PORTB base address */
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#define PORTB_BASE (0x40048000u)
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/** Peripheral PORTB base pointer */
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#define PORTB ((PORT_Type *)PORTB_BASE)
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/** Peripheral PORTC base address */
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#define PORTC_BASE (0x40049000u)
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/** Peripheral PORTC base pointer */
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#define PORTC ((PORT_Type *)PORTC_BASE)
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/** Peripheral PORTD base address */
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#define PORTD_BASE (0x4004a000u)
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/** Peripheral PORTD base pointer */
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#define PORTD ((PORT_Type *)PORTD_BASE)
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/** Peripheral PORTE base address */
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#define PORTE_BASE (0x4004b000u)
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/** Peripheral PORTE base pointer */
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#define PORTE ((PORT_Type *)PORTE_BASE)
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/** Array initializer of PORT peripheral base addresses */
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#define PORT_BASE_ADDRS {PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE}
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/** Array initializer of PORT peripheral base pointers */
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#define PORT_BASE_PTRS {PORTA, PORTB, PORTC, PORTD, PORTE}
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// need fill by yourself
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///** Number of interrupt vector arrays for the PORT module. */
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//#define PORT_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the PORT module. */
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//#define PORT_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the PORT peripheral type */
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//#define PORT_IRQS {PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn}
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/* ----------------------------------------------------------------------------
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-- PORT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PORT_Register_Masks PORT Register Masks
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* @{
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*/
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/* PCR Bit Fields */
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#define PORT_PCR_DWPLK_MASK 0x80000000u
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#define PORT_PCR_DWPLK_SHIFT 31u
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#define PORT_PCR_DWPLK_WIDTH 1u
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#define PORT_PCR_DWPLK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DWPLK_SHIFT))&PORT_PCR_DWPLK_MASK)
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#define PORT_PCR_DWP_MASK 0x3E000000u
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#define PORT_PCR_DWP_SHIFT 25u
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#define PORT_PCR_DWP_WIDTH 5u
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#define PORT_PCR_DWP(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DWP_SHIFT))&PORT_PCR_DWP_MASK)
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#define PORT_PCR_ISF_MASK 0x1000000u
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#define PORT_PCR_ISF_SHIFT 24u
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#define PORT_PCR_ISF_WIDTH 1u
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#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
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#define PORT_PCR_ESTOP_MASK 0x200000u
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#define PORT_PCR_ESTOP_SHIFT 21u
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#define PORT_PCR_ESTOP_WIDTH 1u
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#define PORT_PCR_ESTOP(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ESTOP_SHIFT))&PORT_PCR_ESTOP_MASK)
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#define PORT_PCR_WKUDIS_MASK 0x100000u
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#define PORT_PCR_WKUDIS_SHIFT 20u
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#define PORT_PCR_WKUDIS_WIDTH 1u
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#define PORT_PCR_WKUDIS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_WKUDIS_SHIFT))&PORT_PCR_WKUDIS_MASK)
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#define PORT_PCR_IRQC_MASK 0xF0000u
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#define PORT_PCR_IRQC_SHIFT 16u
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#define PORT_PCR_IRQC_WIDTH 4u
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#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
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#define PORT_PCR_LK_MASK 0x8000u
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#define PORT_PCR_LK_SHIFT 15u
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#define PORT_PCR_LK_WIDTH 1u
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#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
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#define PORT_PCR_MUX_MASK 0x700u
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#define PORT_PCR_MUX_SHIFT 8u
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#define PORT_PCR_MUX_WIDTH 3u
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#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
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#define PORT_PCR_DSE1_MASK 0x80u
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#define PORT_PCR_DSE1_SHIFT 7u
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#define PORT_PCR_DSE1_WIDTH 1u
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#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE1_SHIFT))&PORT_PCR_DSE1_MASK)
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#define PORT_PCR_DSE0_MASK 0x40u
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#define PORT_PCR_DSE0_SHIFT 6u
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#define PORT_PCR_DSE0_WIDTH 1u
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#define PORT_PCR_DSE0(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE0_SHIFT))&PORT_PCR_DSE0_MASK)
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#define PORT_PCR_ODE_MASK 0x20u
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#define PORT_PCR_ODE_SHIFT 5u
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#define PORT_PCR_ODE_WIDTH 1u
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#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
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#define PORT_PCR_PFE_MASK 0x10u
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#define PORT_PCR_PFE_SHIFT 4u
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#define PORT_PCR_PFE_WIDTH 1u
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#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
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#define PORT_PCR_SRE_MASK 0x4u
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#define PORT_PCR_SRE_SHIFT 2u
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#define PORT_PCR_SRE_WIDTH 1u
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#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
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#define PORT_PCR_PE_MASK 0x2u
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#define PORT_PCR_PE_SHIFT 1u
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#define PORT_PCR_PE_WIDTH 1u
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#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
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#define PORT_PCR_PS_MASK 0x1u
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#define PORT_PCR_PS_SHIFT 0u
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#define PORT_PCR_PS_WIDTH 1u
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#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
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#define PORT_PCR_LOW_16BITS_MASK 0xFFFFU
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#define PORT_PCR_HIGH_16BITS_MASK 0xFFFF0000U
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/* PCR0 Reg Mask */
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#define PORT_PCR_MASK 0xBF3F87F7u
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/* GPCLR Bit Fields */
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#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
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#define PORT_GPCLR_GPWE_SHIFT 16u
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#define PORT_GPCLR_GPWE_WIDTH 16u
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#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
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#define PORT_GPCLR_GPWD_MASK 0xFFFFu
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#define PORT_GPCLR_GPWD_SHIFT 0u
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#define PORT_GPCLR_GPWD_WIDTH 16u
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#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
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/* GPCLR Reg Mask */
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#define PORT_GPCLR_MASK 0xFFFFFFFFu
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/* GPCHR Bit Fields */
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#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
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#define PORT_GPCHR_GPWE_SHIFT 16u
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#define PORT_GPCHR_GPWE_WIDTH 16u
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#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
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#define PORT_GPCHR_GPWD_MASK 0xFFFFu
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#define PORT_GPCHR_GPWD_SHIFT 0u
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#define PORT_GPCHR_GPWD_WIDTH 16u
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#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
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/* GPCHR Reg Mask */
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#define PORT_GPCHR_MASK 0xFFFFFFFFu
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/* GICLR Bit Fields */
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#define PORT_GICLR_GIWD_MASK 0xFFFF0000u
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#define PORT_GICLR_GIWD_SHIFT 16u
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#define PORT_GICLR_GIWD_WIDTH 16u
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#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
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#define PORT_GICLR_GIWE_MASK 0xFFFFu
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#define PORT_GICLR_GIWE_SHIFT 0u
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#define PORT_GICLR_GIWE_WIDTH 16u
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#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
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/* GICLR Reg Mask */
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#define PORT_GICLR_MASK 0xFFFFFFFFu
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/* GICHR Bit Fields */
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#define PORT_GICHR_GIWD_MASK 0xFFFF0000u
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#define PORT_GICHR_GIWD_SHIFT 16u
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#define PORT_GICHR_GIWD_WIDTH 16u
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#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
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#define PORT_GICHR_GIWE_MASK 0xFFFFu
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#define PORT_GICHR_GIWE_SHIFT 0u
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#define PORT_GICHR_GIWE_WIDTH 16u
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#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
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/* GICHR Reg Mask */
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#define PORT_GICHR_MASK 0xFFFFFFFFu
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/* ISFR Bit Fields */
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#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
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#define PORT_ISFR_ISF_SHIFT 0u
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#define PORT_ISFR_ISF_WIDTH 32u
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#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
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/* ISFR Reg Mask */
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#define PORT_ISFR_MASK 0xFFFFFFFFu
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/* DFER Bit Fields */
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#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
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#define PORT_DFER_DFE_SHIFT 0u
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#define PORT_DFER_DFE_WIDTH 32u
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#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
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/* DFER Reg Mask */
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#define PORT_DFER_MASK 0xFFFFFFFFu
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/* DFCR Bit Fields */
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#define PORT_DFCR_CS_MASK 0x1u
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#define PORT_DFCR_CS_SHIFT 0u
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#define PORT_DFCR_CS_WIDTH 1u
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#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
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/* DFCR Reg Mask */
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#define PORT_DFCR_MASK 0x00000001u
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/* DFWR Bit Fields */
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#define PORT_DFWR_FILT_MASK 0x1Fu
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#define PORT_DFWR_FILT_SHIFT 0u
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#define PORT_DFWR_FILT_WIDTH 5u
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#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
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/* DFWR Reg Mask */
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#define PORT_DFWR_MASK 0x0000001Fu
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/* GLDWP Bit Fields */
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#define PORT_GLDWP_DWPLK_MASK 0x80000000u
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#define PORT_GLDWP_DWPLK_SHIFT 31u
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#define PORT_GLDWP_DWPLK_WIDTH 1u
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#define PORT_GLDWP_DWPLK(x) (((uint32_t)(((uint32_t)(x))<<PORT_GLDWP_DWPLK_SHIFT))&PORT_GLDWP_DWPLK_MASK)
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#define PORT_GLDWP_DWP_MASK 0x3E000000u
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#define PORT_GLDWP_DWP_SHIFT 25u
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#define PORT_GLDWP_DWP_WIDTH 5u
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#define PORT_GLDWP_DWP(x) (((uint32_t)(((uint32_t)(x))<<PORT_GLDWP_DWP_SHIFT))&PORT_GLDWP_DWP_MASK)
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/* GLDWP Reg Mask */
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#define PORT_GLDWP_MASK 0xBE000000u
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/*!
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* @}
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*/ /* end of group PORT_Register_Masks */
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/*!
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* @}
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*/ /* end of group PORT_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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