354 lines
9.0 KiB
C
354 lines
9.0 KiB
C
#ifndef _FC7240_PMC_NU_Tztufn12_REGS_H_
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#define _FC7240_PMC_NU_Tztufn12_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- PMC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
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* @{
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*/
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/** PMC - Size of Registers Arrays */
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/** PMC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t LVSCR ; /* Low Voltage Status and Control Register, offset: 0x0 */
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__IO uint32_t CONFIG ; /* PMC Configuration Register, offset: 0x4 */
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} PMC_Type, *PMC_MemMapPtr;
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/** Number of instances of the PMC module. */
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#define PMC_INSTANCE_COUNT (1u)
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/* PMC - Peripheral instance base addresses */
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/** Peripheral PMC base address */
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#define PMC_BASE (0x40044000u)
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/** Peripheral PMC base pointer */
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#define PMC ((PMC_Type *)PMC_BASE)
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/** Array initializer of PMC peripheral base addresses */
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#define PMC_BASE_ADDRS {PMC_BASE}
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/** Array initializer of PMC peripheral base pointers */
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#define PMC_BASE_PTRS {PMC}
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// need fill by yourself
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///** Number of interrupt vector arrays for the PMC module. */
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//#define PMC_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the PMC module. */
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//#define PMC_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the PMC peripheral type */
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//#define PMC_IRQS {PMC_IRQn}
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/* ----------------------------------------------------------------------------
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-- PMC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PMC_Register_Masks PMC Register Masks
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* @{
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*/
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/* LVSCR Bit Fields */
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#define PMC_LVSCR_POR_FLAG_MASK 0x80000000u
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#define PMC_LVSCR_POR_FLAG_SHIFT 31u
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#define PMC_LVSCR_POR_FLAG_WIDTH 1u
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#define PMC_LVSCR_POR_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_POR_FLAG_SHIFT))&PMC_LVSCR_POR_FLAG_MASK)
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#define PMC_LVSCR_V15_STATUS_MASK 0xC000000u
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#define PMC_LVSCR_V15_STATUS_SHIFT 26u
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#define PMC_LVSCR_V15_STATUS_WIDTH 2u
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#define PMC_LVSCR_V15_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_V15_STATUS_SHIFT))&PMC_LVSCR_V15_STATUS_MASK)
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#define PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK 0x800000u
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#define PMC_LVSCR_LVR1P1V_RPM_FLAG_SHIFT 23u
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#define PMC_LVSCR_LVR1P1V_RPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR1P1V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR1P1V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK)
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#define PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK 0x400000u
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#define PMC_LVSCR_LVR1P1V_FPM_FLAG_SHIFT 22u
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#define PMC_LVSCR_LVR1P1V_FPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR1P1V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR1P1V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK)
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#define PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK 0x200000u
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#define PMC_LVSCR_LVR2P5V_RPM_FLAG_SHIFT 21u
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#define PMC_LVSCR_LVR2P5V_RPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR2P5V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR2P5V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK)
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#define PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK 0x100000u
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#define PMC_LVSCR_LVR2P5V_FPM_FLAG_SHIFT 20u
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#define PMC_LVSCR_LVR2P5V_FPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR2P5V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR2P5V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK)
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#define PMC_LVSCR_LVR5V_RPM_FLAG_MASK 0x20000u
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#define PMC_LVSCR_LVR5V_RPM_FLAG_SHIFT 17u
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#define PMC_LVSCR_LVR5V_RPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR5V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR5V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR5V_RPM_FLAG_MASK)
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#define PMC_LVSCR_LVR5V_FPM_FLAG_MASK 0x10000u
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#define PMC_LVSCR_LVR5V_FPM_FLAG_SHIFT 16u
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#define PMC_LVSCR_LVR5V_FPM_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVR5V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR5V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR5V_FPM_FLAG_MASK)
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#define PMC_LVSCR_HVD1P5V_STATUS_MASK 0x4000u
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#define PMC_LVSCR_HVD1P5V_STATUS_SHIFT 14u
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#define PMC_LVSCR_HVD1P5V_STATUS_WIDTH 1u
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#define PMC_LVSCR_HVD1P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P5V_STATUS_SHIFT))&PMC_LVSCR_HVD1P5V_STATUS_MASK)
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#define PMC_LVSCR_LVD1P5V_STATUS_MASK 0x2000u
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#define PMC_LVSCR_LVD1P5V_STATUS_SHIFT 13u
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#define PMC_LVSCR_LVD1P5V_STATUS_WIDTH 1u
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#define PMC_LVSCR_LVD1P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD1P5V_STATUS_SHIFT))&PMC_LVSCR_LVD1P5V_STATUS_MASK)
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#define PMC_LVSCR_LVD5V_STATUS_MASK 0x1000u
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#define PMC_LVSCR_LVD5V_STATUS_SHIFT 12u
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#define PMC_LVSCR_LVD5V_STATUS_WIDTH 1u
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#define PMC_LVSCR_LVD5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD5V_STATUS_SHIFT))&PMC_LVSCR_LVD5V_STATUS_MASK)
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#define PMC_LVSCR_HVD1P1V_STATUS_MASK 0x800u
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#define PMC_LVSCR_HVD1P1V_STATUS_SHIFT 11u
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#define PMC_LVSCR_HVD1P1V_STATUS_WIDTH 1u
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#define PMC_LVSCR_HVD1P1V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P1V_STATUS_SHIFT))&PMC_LVSCR_HVD1P1V_STATUS_MASK)
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#define PMC_LVSCR_HVD2P5V_STATUS_MASK 0x400u
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#define PMC_LVSCR_HVD2P5V_STATUS_SHIFT 10u
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#define PMC_LVSCR_HVD2P5V_STATUS_WIDTH 1u
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#define PMC_LVSCR_HVD2P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD2P5V_STATUS_SHIFT))&PMC_LVSCR_HVD2P5V_STATUS_MASK)
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#define PMC_LVSCR_HVD5V_STATUS_MASK 0x100u
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#define PMC_LVSCR_HVD5V_STATUS_SHIFT 8u
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#define PMC_LVSCR_HVD5V_STATUS_WIDTH 1u
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#define PMC_LVSCR_HVD5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD5V_STATUS_SHIFT))&PMC_LVSCR_HVD5V_STATUS_MASK)
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#define PMC_LVSCR_HVD1P5V_FLAG_MASK 0x40u
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#define PMC_LVSCR_HVD1P5V_FLAG_SHIFT 6u
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#define PMC_LVSCR_HVD1P5V_FLAG_WIDTH 1u
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#define PMC_LVSCR_HVD1P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P5V_FLAG_SHIFT))&PMC_LVSCR_HVD1P5V_FLAG_MASK)
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#define PMC_LVSCR_LVD1P5V_FLAG_MASK 0x20u
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#define PMC_LVSCR_LVD1P5V_FLAG_SHIFT 5u
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#define PMC_LVSCR_LVD1P5V_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVD1P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD1P5V_FLAG_SHIFT))&PMC_LVSCR_LVD1P5V_FLAG_MASK)
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#define PMC_LVSCR_LVD5V_FLAG_MASK 0x10u
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#define PMC_LVSCR_LVD5V_FLAG_SHIFT 4u
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#define PMC_LVSCR_LVD5V_FLAG_WIDTH 1u
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#define PMC_LVSCR_LVD5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD5V_FLAG_SHIFT))&PMC_LVSCR_LVD5V_FLAG_MASK)
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#define PMC_LVSCR_HVD1P1V_FLAG_MASK 0x8u
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#define PMC_LVSCR_HVD1P1V_FLAG_SHIFT 3u
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#define PMC_LVSCR_HVD1P1V_FLAG_WIDTH 1u
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#define PMC_LVSCR_HVD1P1V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P1V_FLAG_SHIFT))&PMC_LVSCR_HVD1P1V_FLAG_MASK)
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#define PMC_LVSCR_HVD2P5V_FLAG_MASK 0x4u
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#define PMC_LVSCR_HVD2P5V_FLAG_SHIFT 2u
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#define PMC_LVSCR_HVD2P5V_FLAG_WIDTH 1u
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#define PMC_LVSCR_HVD2P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD2P5V_FLAG_SHIFT))&PMC_LVSCR_HVD2P5V_FLAG_MASK)
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#define PMC_LVSCR_HVD5V_FLAG_MASK 0x1u
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#define PMC_LVSCR_HVD5V_FLAG_SHIFT 0u
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#define PMC_LVSCR_HVD5V_FLAG_WIDTH 1u
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#define PMC_LVSCR_HVD5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD5V_FLAG_SHIFT))&PMC_LVSCR_HVD5V_FLAG_MASK)
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/* LVSCR Reg Mask */
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#define PMC_LVSCR_MASK 0x8CF37D7Du
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/* CONFIG Bit Fields */
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#define PMC_CONFIG_V15_LOCK_MASK 0x8000u
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#define PMC_CONFIG_V15_LOCK_SHIFT 15u
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#define PMC_CONFIG_V15_LOCK_WIDTH 1u
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#define PMC_CONFIG_V15_LOCK(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_LOCK_SHIFT))&PMC_CONFIG_V15_LOCK_MASK)
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#define PMC_CONFIG_LVD_IE_MASK 0x200u
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#define PMC_CONFIG_LVD_IE_SHIFT 9u
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#define PMC_CONFIG_LVD_IE_WIDTH 1u
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#define PMC_CONFIG_LVD_IE(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_LVD_IE_SHIFT))&PMC_CONFIG_LVD_IE_MASK)
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#define PMC_CONFIG_HVD_IE_MASK 0x100u
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#define PMC_CONFIG_HVD_IE_SHIFT 8u
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#define PMC_CONFIG_HVD_IE_WIDTH 1u
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#define PMC_CONFIG_HVD_IE(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_HVD_IE_SHIFT))&PMC_CONFIG_HVD_IE_MASK)
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#define PMC_CONFIG_V15_CTRL_EN_MASK 0x20u
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#define PMC_CONFIG_V15_CTRL_EN_SHIFT 5u
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#define PMC_CONFIG_V15_CTRL_EN_WIDTH 1u
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#define PMC_CONFIG_V15_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_CTRL_EN_SHIFT))&PMC_CONFIG_V15_CTRL_EN_MASK)
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#define PMC_CONFIG_V15_AUTOSW_MASK 0x10u
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#define PMC_CONFIG_V15_AUTOSW_SHIFT 4u
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#define PMC_CONFIG_V15_AUTOSW_WIDTH 1u
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#define PMC_CONFIG_V15_AUTOSW(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_AUTOSW_SHIFT))&PMC_CONFIG_V15_AUTOSW_MASK)
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#define PMC_CONFIG_RPM_VDD2P5_EN_MASK 0x8u
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#define PMC_CONFIG_RPM_VDD2P5_EN_SHIFT 3u
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#define PMC_CONFIG_RPM_VDD2P5_EN_WIDTH 1u
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#define PMC_CONFIG_RPM_VDD2P5_EN(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_RPM_VDD2P5_EN_SHIFT))&PMC_CONFIG_RPM_VDD2P5_EN_MASK)
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/* CONFIG Reg Mask */
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#define PMC_CONFIG_MASK 0x00008338u
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/*!
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* @}
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*/ /* end of group PMC_Register_Masks */
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/*!
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* @}
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*/ /* end of group PMC_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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