480 lines
13 KiB
C
480 lines
13 KiB
C
#ifndef _FC7240_MB_NU_Tztufn18_REGS_H_
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#define _FC7240_MB_NU_Tztufn18_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- MB Peripheral Access Layer
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---------------------------------------------------------------------------- */
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#define MB_CHANNEL_CONFIG_COUNT 4
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#define MB_INT_CONFIG_COUNT 2
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/*!
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* @addtogroup MB_Peripheral_Access_Layer MB Peripheral Access Layer
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* @{
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*/
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/** MB - Size of Registers Arrays */
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/** MB - Register Layout Typedef */
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typedef struct {
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struct
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{
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__I uint32_t MB_CCn_SEMA ; /* Communication Channel Smeaphore Register, offset: 0x0 */
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__IO uint32_t MB_CCn_SEMA_UNLK ; /* Communication Channel Smeaphore Unlock Register, offset: 0x4 */
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__O uint32_t MB_CCn_REQUEST ; /* Communication Channel Request Register, offset: 0x8 */
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__IO uint32_t MB_CCn_DONE ; /* Communication Channel Done Register, offset: 0xc */
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__IO uint32_t MB_CCn_DONE_MASK ; /* Communication Channel Done Mask Register, offset: 0x10 */
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__IO uint32_t MB_CCn_DATA0 ; /* Communication Channel Data Register0, offset: 0x14 */
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__IO uint32_t MB_CCn_DATA1 ; /* Communication Channel Data Register1, offset: 0x18 */
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__I uint32_t MB_CCn_STAT ; /* Communication Channel Status Register, offset: 0x1c */
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__O uint32_t MB_CCn_CLR ; /* Communication Channel Clear Register, offset: 0x20 */
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uint8_t RESERVED_0[12];
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} CHANNEL[MB_CHANNEL_CONFIG_COUNT];
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uint8_t RESERVED_15[1856];
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struct
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{
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__IO uint32_t MB_INTn_FLG ; /* Interrupt Channel Flag Register, offset: 0x800 */
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__IO uint32_t MB_INTn_FLG_MASK ; /* Interrupt Channel Flag Mask Register, offset: 0x804 */
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__IO uint32_t MB_INTn_INTEN ; /* Interrupt Channel Interrupt Enable Register, offset: 0x808 */
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__I uint32_t MB_INTn_FLG_STAT ; /* Interrupt Channel Flag Status Register, offset: 0x80c */
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__IO uint32_t MB_INTn_CTRL ; /* Interrupt Channel Control Register, offset: 0x810 */
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uint8_t RESERVED_2[12];
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} INTR[MB_INT_CONFIG_COUNT];
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} MB_Type, *MB_MemMapPtr;
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/** Number of instances of the MB module. */
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#define MB_INSTANCE_COUNT (1u)
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/* MB - Peripheral instance base addresses */
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/** Peripheral MB base address */
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#define MB_BASE (0x40058000u)
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/** Peripheral MB base pointer */
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#define MB ((MB_Type *)MB_BASE)
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/** Array initializer of MB peripheral base addresses */
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#define MB_BASE_ADDRS {MB_BASE}
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/** Array initializer of MB peripheral base pointers */
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#define MB_BASE_PTRS {MB}
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// need fill by yourself
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///** Number of interrupt vector arrays for the MB module. */
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//#define MB_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the MB module. */
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//#define MB_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the MB peripheral type */
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//#define MB_IRQS {MB_IRQn}
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/* ----------------------------------------------------------------------------
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-- MB Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MB_Register_Masks MB Register Masks
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* @{
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*/
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/* CCn_SEMA Bit Fields */
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#define MB_CCn_SEMA_LOCK_MASK 0x80000000u
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#define MB_CCn_SEMA_LOCK_SHIFT 31u
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#define MB_CCn_SEMA_LOCK_WIDTH 1u
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#define MB_CCn_SEMA_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_SHIFT))&MB_CCn_SEMA_LOCK_MASK)
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#define MB_CCn_SEMA_LOCK_MASTER_ID_MASK 0xF0u
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#define MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT 4u
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#define MB_CCn_SEMA_LOCK_MASTER_ID_WIDTH 4u
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#define MB_CCn_SEMA_LOCK_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_ID_MASK)
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#define MB_CCn_SEMA_LOCK_MASTER_SEC_MASK 0x2u
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#define MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT 1u
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#define MB_CCn_SEMA_LOCK_MASTER_SEC_WIDTH 1u
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#define MB_CCn_SEMA_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SEC_MASK)
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#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK 0x1u
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#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT 0u
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#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_WIDTH 1u
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#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK)
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/* CC0_SEMA Reg Mask */
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#define MB_CCn_SEMA_MASK 0x800000F3u
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/* CCn_SEMA_UNLK Bit Fields */
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#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_MASK 0x3u
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#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT 0u
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#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_WIDTH 2u
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#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT))&MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_MASK)
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/* CCn_REQUEST Bit Fields */
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#define MB_CCn_REQUEST_REQ_MASK 0x3u
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#define MB_CCn_REQUEST_REQ_SHIFT 0u
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#define MB_CCn_REQUEST_REQ_WIDTH 2u
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#define MB_CCn_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_REQUEST_REQ_SHIFT))&MB_CCn_REQUEST_REQ_MASK)
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/* CCn_DONE Bit Fields */
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#define MB_CCn_DONE_DONE_MASK 0x3u
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#define MB_CCn_DONE_DONE_SHIFT 0u
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#define MB_CCn_DONE_DONE_WIDTH 2u
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#define MB_CCn_DONE_DONE(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_DONE_SHIFT))&MB_CCn_DONE_DONE_MASK)
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/* CCn_DONE_MASK Bit Fields */
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#define MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK 0xF0000u
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#define MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT 16u
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#define MB_CCn_DONE_MASK_DONE_MASTER_ID_WIDTH 4u
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#define MB_CCn_DONE_MASK_DONE_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT))&MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)
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#define MB_CCn_DONE_MASK_DONE_MASK_MASK 0x3u
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#define MB_CCn_DONE_MASK_DONE_MASK_SHIFT 0u
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#define MB_CCn_DONE_MASK_DONE_MASK_WIDTH 2u
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#define MB_CCn_DONE_MASK_DONE_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASK_SHIFT))&MB_CCn_DONE_MASK_DONE_MASK_MASK)
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/* CC0_DONE_MASK Reg Mask */
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#define MB_CCn_DONE_MASK_MASK 0x000F0003u
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/* CCn_DATA0 Bit Fields */
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#define MB_CCn_DATA0_DATA0_MASK 0xFFFFFFFFu
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#define MB_CCn_DATA0_DATA0_SHIFT 0u
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#define MB_CCn_DATA0_DATA0_WIDTH 32u
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#define MB_CCn_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA0_DATA0_SHIFT))&MB_CCn_DATA0_DATA0_MASK)
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/* CC0_DATA0 Reg Mask */
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#define MB_CCn_DATA0_MASK 0xFFFFFFFFu
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/* CCn_DATA1 Bit Fields */
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#define MB_CCn_DATA1_DATA1_MASK 0xFFFFFFFFu
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#define MB_CCn_DATA1_DATA1_SHIFT 0u
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#define MB_CCn_DATA1_DATA1_WIDTH 32u
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#define MB_CCn_DATA1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA1_DATA1_SHIFT))&MB_CCn_DATA1_DATA1_MASK)
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/* CC0_DATA1 Reg Mask */
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#define MB_CCn_DATA1_MASK 0xFFFFFFFFu
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/* CCn_STAT Bit Fields */
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#define MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK 0x80000000u
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#define MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT 31u
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#define MB_CCn_STAT_CURRENT_LOCK_STATUS_WIDTH 1u
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#define MB_CCn_STAT_CURRENT_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK)
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#define MB_CCn_STAT_CURRENT_CPU_STATUS_MASK 0xFFFF00u
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#define MB_CCn_STAT_CURRENT_CPU_STATUS_SHIFT 8u
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#define MB_CCn_STAT_CURRENT_CPU_STATUS_WIDTH 16u
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#define MB_CCn_STAT_CURRENT_CPU_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_CPU_STATUS_SHIFT))&MB_CCn_STAT_CURRENT_CPU_STATUS_MASK)
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK 0xF0u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT 4u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_WIDTH 4u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK)
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK 0x2u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT 1u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_WIDTH 1u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK)
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK 0x1u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT 0u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_WIDTH 1u
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#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK)
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/* CC0_STAT Reg Mask */
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#define MB_CCn_STAT_MASK 0x80FFFFF3u
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/* CCn_CLR Bit Fields */
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#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK 0xFFFFFFFFu
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#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT 0u
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#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_WIDTH 32u
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#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT))&MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK)
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/* CC0_CLR Reg Mask */
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#define MB_CCn_CLR_MASK 0xFFFFFFFFu
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/* INTn_FLG Bit Fields */
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#define MB_INTn_FLG_DONE_FLAG_MASK 0xF0000u
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#define MB_INTn_FLG_DONE_FLAG_SHIFT 16u
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#define MB_INTn_FLG_DONE_FLAG_WIDTH 4u
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#define MB_INTn_FLG_DONE_FLAG(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_DONE_FLAG_SHIFT))&MB_INTn_FLG_DONE_FLAG_MASK)
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#define MB_INTn_FLG_REQ_FLAG_MASK 0xFu
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#define MB_INTn_FLG_REQ_FLAG_SHIFT 0u
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#define MB_INTn_FLG_REQ_FLAG_WIDTH 4u
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#define MB_INTn_FLG_REQ_FLAG(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_REQ_FLAG_SHIFT))&MB_INTn_FLG_REQ_FLAG_MASK)
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/* INTn_FLG_MASK Bit Fields */
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#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK 0xF0000u
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#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT 16u
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#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_WIDTH 4u
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#define MB_INTn_FLG_MASK_DONE_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK)
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#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK 0xFu
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#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT 0u
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#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_WIDTH 4u
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#define MB_INTn_FLG_MASK_REQ_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK)
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/* INT0_FLG_MASK Reg Mask */
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#define MB_INTn_FLG_MASK_MASK 0x000F000Fu
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/* INTn_INTEN Bit Fields */
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#define MB_INTn_INTEN_DONE_INT_EN_MASK 0xF0000u
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#define MB_INTn_INTEN_DONE_INT_EN_SHIFT 16u
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#define MB_INTn_INTEN_DONE_INT_EN_WIDTH 4u
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#define MB_INTn_INTEN_DONE_INT_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_DONE_INT_EN_SHIFT))&MB_INTn_INTEN_DONE_INT_EN_MASK)
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#define MB_INTn_INTEN_REQ_INT_EN_MASK 0xFu
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#define MB_INTn_INTEN_REQ_INT_EN_SHIFT 0u
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#define MB_INTn_INTEN_REQ_INT_EN_WIDTH 4u
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#define MB_INTn_INTEN_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_REQ_INT_EN_SHIFT))&MB_INTn_INTEN_REQ_INT_EN_MASK)
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/* INT0_INTEN Reg Mask */
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#define MB_INTn_INTEN_MASK 0x000F000Fu
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/* INTn_FLG_STAT Bit Fields */
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#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK 0xF0000u
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#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT 16u
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#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_WIDTH 4u
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#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK)
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#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK 0xFu
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#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT 0u
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#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_WIDTH 4u
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#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK)
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/* INT0_FLG_STAT Reg Mask */
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#define MB_INTn_FLG_STAT_MASK 0x000F000Fu
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/* INTn_CTRL Bit Fields */
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#define MB_INTn_CTRL_INTEN_LOCK_MASK 0x4u
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#define MB_INTn_CTRL_INTEN_LOCK_SHIFT 2u
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#define MB_INTn_CTRL_INTEN_LOCK_WIDTH 1u
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#define MB_INTn_CTRL_INTEN_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_INTEN_LOCK_SHIFT))&MB_INTn_CTRL_INTEN_LOCK_MASK)
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#define MB_INTn_CTRL_FLG_MASK_LOCK_MASK 0x2u
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#define MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT 1u
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#define MB_INTn_CTRL_FLG_MASK_LOCK_WIDTH 1u
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#define MB_INTn_CTRL_FLG_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT))&MB_INTn_CTRL_FLG_MASK_LOCK_MASK)
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#define MB_INTn_CTRL_FLG_LOCK_MASK 0x1u
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#define MB_INTn_CTRL_FLG_LOCK_SHIFT 0u
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#define MB_INTn_CTRL_FLG_LOCK_WIDTH 1u
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#define MB_INTn_CTRL_FLG_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_LOCK_SHIFT))&MB_INTn_CTRL_FLG_LOCK_MASK)
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/* INT0_CTRL Reg Mask */
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#define MB_INTn_CTRL_MASK 0x00000007u
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/* Channel master done code */
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#define MB_MASTER_DONE_CODE 0xFC730000u
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/* force unlock channel */
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#define MB_FORCE_UNLOCK_CODE 0xFC350000u
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/*!
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* @}
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*/ /* end of group MB_Register_Masks */
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/*!
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* @}
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*/ /* end of group MB_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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