274 lines
5.9 KiB
C
274 lines
5.9 KiB
C
#ifndef _FC7240_INTM_NU_Tztufn10_REGS_H_
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#define _FC7240_INTM_NU_Tztufn10_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- INTM Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer
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* @{
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*/
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/** INTM - Size of Registers Arrays */
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/** INTM - Register Layout Typedef */
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typedef struct {
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__IO uint32_t ER ; /* Enable Register, offset: 0x0 */
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__IO uint32_t IACKR ; /* Interrupt Acknowledge Register, offset: 0x4 */
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__IO uint32_t IRQSELR0 ; /* Interrupt Request Select Register, offset: 0x8 */
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__IO uint32_t LATR0 ; /* Latency Register, offset: 0xc */
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__IO uint32_t TMR0 ; /* Timer Register, offset: 0x10 */
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__I uint32_t SR0 ; /* Status Register, offset: 0x14 */
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__IO uint32_t IRQSELR1 ; /* Interrupt Request Select Register, offset: 0x18 */
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__IO uint32_t LATR1 ; /* Latency Register, offset: 0x1c */
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__IO uint32_t TMR1 ; /* Timer Register, offset: 0x20 */
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__I uint32_t SR1 ; /* Status Register, offset: 0x24 */
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} INTM_Type, *INTM_MemMapPtr;
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/** Number of instances of the INTM module. */
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#define INTM_INSTANCE_COUNT (1u)
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/* INTM - Peripheral instance base addresses */
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/** Peripheral INTM base address */
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#define INTM_BASE (0x4001a000u)
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/** Peripheral INTM base pointer */
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#define INTM ((INTM_Type *)INTM_BASE)
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/** Array initializer of INTM peripheral base addresses */
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#define INTM_BASE_ADDRS {INTM_BASE}
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/** Array initializer of INTM peripheral base pointers */
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#define INTM_BASE_PTRS {INTM}
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// need fill by yourself
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///** Number of interrupt vector arrays for the INTM module. */
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//#define INTM_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the INTM module. */
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//#define INTM_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the INTM peripheral type */
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//#define INTM_IRQS {INTM_IRQn}
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/* ----------------------------------------------------------------------------
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-- INTM Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup INTM_Register_Masks INTM Register Masks
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* @{
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*/
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/* ER Bit Fields */
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#define INTM_ER_EN_MASK 0x1u
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#define INTM_ER_EN_SHIFT 0u
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#define INTM_ER_EN_WIDTH 1u
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#define INTM_ER_EN(x) (((uint32_t)(((uint32_t)(x))<<INTM_ER_EN_SHIFT))&INTM_ER_EN_MASK)
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/* ER Reg Mask */
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#define INTM_ER_MASK 0x00000001u
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/* IACKR Bit Fields */
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#define INTM_IACKR_IRQ_MASK 0x3FFu
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#define INTM_IACKR_IRQ_SHIFT 0u
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#define INTM_IACKR_IRQ_WIDTH 10u
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#define INTM_IACKR_IRQ(x) (((uint32_t)(((uint32_t)(x))<<INTM_IACKR_IRQ_SHIFT))&INTM_IACKR_IRQ_MASK)
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/* IACKR Reg Mask */
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#define INTM_IACKR_MASK 0x000003FFu
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/* IRQSELR Bit Fields */
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#define INTM_IRQSELR_RSTE_MASK 0x80000000u
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#define INTM_IRQSELR_RSTE_SHIFT 31u
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#define INTM_IRQSELR_RSTE_WIDTH 1u
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#define INTM_IRQSELR_RSTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_RSTE_SHIFT))&INTM_IRQSELR_RSTE_MASK)
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#define INTM_IRQSELR_INTE_MASK 0x40000000u
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#define INTM_IRQSELR_INTE_SHIFT 30u
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#define INTM_IRQSELR_INTE_WIDTH 1u
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#define INTM_IRQSELR_INTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_INTE_SHIFT))&INTM_IRQSELR_INTE_MASK)
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#define INTM_IRQSELR_IACTE_MASK 0x20000000u
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#define INTM_IRQSELR_IACTE_SHIFT 29u
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#define INTM_IRQSELR_IACTE_WIDTH 1u
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#define INTM_IRQSELR_IACTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IACTE_SHIFT))&INTM_IRQSELR_IACTE_MASK)
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#define INTM_IRQSELR_IACTST_MASK 0x10000u
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#define INTM_IRQSELR_IACTST_SHIFT 16u
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#define INTM_IRQSELR_IACTST_WIDTH 1u
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#define INTM_IRQSELR_IACTST(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IACTST_SHIFT))&INTM_IRQSELR_IACTST_MASK)
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#define INTM_IRQSELR_IRQ_MASK 0x3FFu
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#define INTM_IRQSELR_IRQ_SHIFT 0u
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#define INTM_IRQSELR_IRQ_WIDTH 10u
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#define INTM_IRQSELR_IRQ(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IRQ_SHIFT))&INTM_IRQSELR_IRQ_MASK)
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/* IRQSELR0 Reg Mask */
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#define INTM_IRQSELR_MASK 0xE00103FFu
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/* LATR Bit Fields */
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#define INTM_LATR_LAT_MASK 0xFFFFFFu
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#define INTM_LATR_LAT_SHIFT 0u
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#define INTM_LATR_LAT_WIDTH 24u
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#define INTM_LATR_LAT(x) (((uint32_t)(((uint32_t)(x))<<INTM_LATR_LAT_SHIFT))&INTM_LATR_LAT_MASK)
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/* LATR0 Reg Mask */
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#define INTM_LATR_MASK 0x00FFFFFFu
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/* TMR Bit Fields */
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#define INTM_TMR_TIMER_MASK 0xFFFFFFu
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#define INTM_TMR_TIMER_SHIFT 0u
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#define INTM_TMR_TIMER_WIDTH 24u
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#define INTM_TMR_TIMER(x) (((uint32_t)(((uint32_t)(x))<<INTM_TMR_TIMER_SHIFT))&INTM_TMR_TIMER_MASK)
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/* TMR0 Reg Mask */
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#define INTM_TMR_MASK 0x00FFFFFFu
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/* SR Bit Fields */
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#define INTM_SR_STATUS_MASK 0x1u
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#define INTM_SR_STATUS_SHIFT 0u
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#define INTM_SR_STATUS_WIDTH 1u
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#define INTM_SR_STATUS(x) (((uint32_t)(((uint32_t)(x))<<INTM_SR_STATUS_SHIFT))&INTM_SR_STATUS_MASK)
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/* SR0 Reg Mask */
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#define INTM_SR_MASK 0x00000001u
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/*!
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* @}
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*/ /* end of group INTM_Register_Masks */
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/*!
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* @}
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*/ /* end of group INTM_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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