164 lines
2.9 KiB
C
164 lines
2.9 KiB
C
#ifndef _FC7240_SMC_NU_Tztufn46_REGS_H_
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#define _FC7240_SMC_NU_Tztufn46_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- SMC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
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* @{
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*/
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/** SMC - Size of Registers Arrays */
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/** SMC - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[12];
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__IO uint32_t PMCTRL ; /* Power Mode Control Register, offset: 0xc */
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__IO uint32_t STANDBY_CFG ; /* Standby Mode Configuration Register, offset: 0x10 */
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} SMC_Type, *SMC_MemMapPtr;
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/** Number of instances of the SMC module. */
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#define SMC_INSTANCE_COUNT (1u)
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/* SMC - Peripheral instance base addresses */
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/** Peripheral SMC base address */
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#define SMC_BASE (0x40045000u)
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/** Peripheral SMC base pointer */
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#define SMC ((SMC_Type *)SMC_BASE)
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/** Array initializer of SMC peripheral base addresses */
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#define SMC_BASE_ADDRS {SMC_BASE}
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/** Array initializer of SMC peripheral base pointers */
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#define SMC_BASE_PTRS {SMC}
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// need fill by yourself
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///** Number of interrupt vector arrays for the SMC module. */
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//#define SMC_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the SMC module. */
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//#define SMC_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the SMC peripheral type */
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//#define SMC_IRQS {SMC_IRQn}
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/* ----------------------------------------------------------------------------
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-- SMC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SMC_Register_Masks SMC Register Masks
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* @{
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*/
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/* PMCTRL Bit Fields */
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#define SMC_PMCTRL_STOP_MODE_MASK 0x7u
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#define SMC_PMCTRL_STOP_MODE_SHIFT 0u
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#define SMC_PMCTRL_STOP_MODE_WIDTH 3u
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#define SMC_PMCTRL_STOP_MODE(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOP_MODE_SHIFT))&SMC_PMCTRL_STOP_MODE_MASK)
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/* PMCTRL Reg Mask */
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#define SMC_PMCTRL_MASK 0x00000007u
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/* STANDBY_CFG Bit Fields */
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#define SMC_STANDBY_CFG_OPTION_MASK 0x3u
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#define SMC_STANDBY_CFG_OPTION_SHIFT 0u
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#define SMC_STANDBY_CFG_OPTION_WIDTH 2u
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#define SMC_STANDBY_CFG_OPTION(x) (((uint32_t)(((uint32_t)(x))<<SMC_STANDBY_CFG_OPTION_SHIFT))&SMC_STANDBY_CFG_OPTION_MASK)
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/* STANDBY_CFG Reg Mask */
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#define SMC_STANDBY_CFG_MASK 0x00000003u
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/*!
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* @}
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*/ /* end of group SMC_Register_Masks */
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/*!
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* @}
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*/ /* end of group SMC_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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