2296 lines
60 KiB
C
2296 lines
60 KiB
C
#ifndef _FC7240_PCC_NU_Tztufn5_REGS_H_
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#define _FC7240_PCC_NU_Tztufn5_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- PCC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer
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* @{
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*/
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/** PCC - Size of Registers Arrays */
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/** PCC - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[32];
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__IO uint32_t PCC_DMA0 ; /* DMA0 Clock Control Register, offset: 0x20 */
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uint8_t RESERVED_1[4];
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__IO uint32_t PCC_DMAMUX0 ; /* DMAMUX0 Clock Control Register, offset: 0x28 */
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uint8_t RESERVED_2[32];
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__IO uint32_t PCC_ROMC ; /* ROMC Clock Control Register, offset: 0x4C */
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uint8_t RESERVED_3[16];
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__IO uint32_t PCC_ERM ; /* ERM Clock Control Register, offset: 0x60 */
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__IO uint32_t PCC_EIM ; /* EIM Clock Control Register, offset: 0x64 */
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__IO uint32_t PCC_INTM0 ; /* INTM0 Clock Control Register, offset: 0x68 */
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__IO uint32_t PCC_ISM0 ; /* ISM0 Clock Control Register, offset: 0x6C */
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uint8_t RESERVED_4[24];
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__IO uint32_t PCC_WDOG0 ; /* WDOG0 Clock Control Register, offset: 0x88 */
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uint8_t RESERVED_5[12];
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__IO uint32_t PCC_TRGSEL0 ; /* TRGSEL0 Clock Control Register, offset: 0x98 */
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__IO uint32_t PCC_TRGSEL1 ; /* TRGSEL1 Clock Control Register, offset: 0x9C */
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__IO uint32_t PCC_TRGSEL2 ; /* TRGSEL2 Clock Control Register, offset: 0xA0 */
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__IO uint32_t PCC_TRGSEL3 ; /* TRGSEL3 Clock Control Register, offset: 0xA4 */
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__IO uint32_t PCC_CRC0 ; /* CRC0 Clock Control Register, offset: 0xA8 */
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__IO uint32_t PCC_CORDIC0 ; /* CORDIC0 Clock Control Register, offset: 0xAC */
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__IO uint32_t PCC_TSTMP0 ; /* TSTMP0 Clock Control Register, offset: 0xB0 */
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__IO uint32_t PCC_TSTMP1 ; /* TSTMP1 Clock Control Register, offset: 0xB4 */
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__IO uint32_t PCC_FCPIT0 ; /* FCPIT0 Clock Control Register, offset: 0xB8 */
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__IO uint32_t PCC_AONTIMER0 ; /* AONTIMER0 Clock Control Register, offset: 0xBC */
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__IO uint32_t PCC_RTC ; /* RTC Clock Control Register, offset: 0xC0 */
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__IO uint32_t PCC_CMU0 ; /* CMU0 Clock Control Register, offset: 0xC4 */
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__IO uint32_t PCC_CMU1 ; /* CMU1 Clock Control Register, offset: 0xC8 */
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__IO uint32_t PCC_CMU2 ; /* CMU2 Clock Control Register, offset: 0xCC */
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__IO uint32_t PCC_CMU3 ; /* CMU3 Clock Control Register, offset: 0xD0 */
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__IO uint32_t PCC_CMU4 ; /* CMU4 Clock Control Register, offset: 0xD4 */
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uint8_t RESERVED_6[4];
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__IO uint32_t PCC_PTIMER0 ; /* PTIMER0 Clock Control Register, offset: 0xDC */
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__IO uint32_t PCC_PTIMER1 ; /* PTIMER1 Clock Control Register, offset: 0xE0 */
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uint8_t RESERVED_7[8];
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__IO uint32_t PCC_ADC0 ; /* ADC0 Clock Control Register, offset: 0xEC */
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__IO uint32_t PCC_ADC1 ; /* ADC1 Clock Control Register, offset: 0xF0 */
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uint8_t RESERVED_8[8];
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__IO uint32_t PCC_WKU ; /* WKU Clock Control Register, offset: 0xFC */
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__IO uint32_t PCC_CMP0 ; /* CMP0 Clock Control Register, offset: 0x100 */
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__IO uint32_t PCC_CMP1 ; /* CMP1 Clock Control Register, offset: 0x104 */
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uint8_t RESERVED_9[4];
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__IO uint32_t PCC_TMU ; /* TMU Clock Control Register, offset: 0x10C */
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uint8_t RESERVED_10[64];
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__IO uint32_t PCC_SENT0 ; /* SENT0 Clock Control Register, offset: 0x150 */
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uint8_t RESERVED_11[12];
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__IO uint32_t PCC_MB ; /* MB Clock Control Register, offset: 0x160 */
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uint8_t RESERVED_12[12];
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__IO uint32_t PCC_FTU0 ; /* FTU0 Clock Control Register, offset: 0x170 */
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__IO uint32_t PCC_FTU1 ; /* FTU1 Clock Control Register, offset: 0x174 */
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__IO uint32_t PCC_FTU2 ; /* FTU2 Clock Control Register, offset: 0x178 */
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__IO uint32_t PCC_FTU3 ; /* FTU3 Clock Control Register, offset: 0x17C */
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uint8_t RESERVED_13[8];
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__IO uint32_t PCC_FCSPI0 ; /* FCSPI0 Clock Control Register, offset: 0x188 */
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__IO uint32_t PCC_FCSPI1 ; /* FCSPI1 Clock Control Register, offset: 0x18C */
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__IO uint32_t PCC_FCSPI2 ; /* FCSPI2 Clock Control Register, offset: 0x190 */
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uint8_t RESERVED_14[4];
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__IO uint32_t PCC_FCIIC0 ; /* FCIIC0 Clock Control Register, offset: 0x198 */
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uint8_t RESERVED_15[4];
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__IO uint32_t PCC_FCUART0 ; /* FCUART0 Clock Control Register, offset: 0x1A0 */
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__IO uint32_t PCC_FCUART1 ; /* FCUART1 Clock Control Register, offset: 0x1A4 */
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__IO uint32_t PCC_FCUART2 ; /* FCUART2 Clock Control Register, offset: 0x1A8 */
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__IO uint32_t PCC_FCUART3 ; /* FCUART3 Clock Control Register, offset: 0x1AC */
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uint8_t RESERVED_16[16];
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__IO uint32_t PCC_LU0 ; /* LU0 Clock Control Register, offset: 0x1C0 */
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uint8_t RESERVED_17[28];
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__IO uint32_t PCC_FREQM ; /* FREQM Clock Control Register, offset: 0x1E0 */
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uint8_t RESERVED_18[24];
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__IO uint32_t PCC_STCU ; /* STCU Clock Control Register, offset: 0x1FC */
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__IO uint32_t PCC_FLEXCAN0 ; /* FLEXCAN0 Clock Control Register, offset: 0x200 */
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uint8_t RESERVED_19[12];
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__IO uint32_t PCC_FLEXCAN1 ; /* FLEXCAN1 Clock Control Register, offset: 0x210 */
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uint8_t RESERVED_20[312];
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__IO uint32_t PCC_WDOG1 ; /* WDOG1 Clock Control Register, offset: 0x34C */
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uint8_t RESERVED_21[28];
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__IO uint32_t PCC_TRGSEL4 ; /* TRGSEL4 Clock Control Register, offset: 0x36C */
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__IO uint32_t PCC_TRGSEL5 ; /* TRGSEL5 Clock Control Register, offset: 0x370 */
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uint8_t RESERVED_22[8];
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__IO uint32_t PCC_FCSPI3 ; /* FCSPI3 Clock Control Register, offset: 0x37C */
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__IO uint32_t PCC_FCSPI4 ; /* FCSPI4 Clock Control Register, offset: 0x380 */
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__IO uint32_t PCC_FCSPI5 ; /* FCSPI5 Clock Control Register, offset: 0x384 */
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uint8_t RESERVED_23[116];
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__IO uint32_t PCC_FTU4 ; /* FTU4 Clock Control Register, offset: 0x3FC */
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__IO uint32_t PCC_FTU5 ; /* FTU5 Clock Control Register, offset: 0x400 */
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__IO uint32_t PCC_FTU6 ; /* FTU6 Clock Control Register, offset: 0x404 */
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__IO uint32_t PCC_FTU7 ; /* FTU7 Clock Control Register, offset: 0x408 */
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uint8_t RESERVED_24[16];
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__IO uint32_t PCC_FCIIC1 ; /* FCIIC1 Clock Control Register, offset: 0x41C */
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__IO uint32_t PCC_FCUART4 ; /* FCUART4 Clock Control Register, offset: 0x420 */
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__IO uint32_t PCC_FCUART5 ; /* FCUART5 Clock Control Register, offset: 0x424 */
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__IO uint32_t PCC_FCUART6 ; /* FCUART6 Clock Control Register, offset: 0x428 */
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__IO uint32_t PCC_FCUART7 ; /* FCUART7 Clock Control Register, offset: 0x42C */
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uint8_t RESERVED_25[32];
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__IO uint32_t PCC_MSC0 ; /* MSC0 Clock Control Register, offset: 0x450 */
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uint8_t RESERVED_26[44];
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__IO uint32_t PCC_FLEXCAN2 ; /* FLEXCAN2 Clock Control Register, offset: 0x480 */
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uint8_t RESERVED_27[12];
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__IO uint32_t PCC_FLEXCAN3 ; /* FLEXCAN3 Clock Control Register, offset: 0x490 */
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} PCC_Type, *PCC_MemMapPtr;
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/** Number of instances of the PCC module. */
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#define PCC_INSTANCE_COUNT (1u)
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/* PCC - Peripheral instance base addresses */
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/** Peripheral PCC base address */
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#define PCC_BASE (0x40024000u)
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/** Peripheral PCC base pointer */
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#define PCC ((PCC_Type *)PCC_BASE)
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/** Array initializer of PCC peripheral base addresses */
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#define PCC_BASE_ADDRS {PCC_BASE}
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/** Array initializer of PCC peripheral base pointers */
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#define PCC_BASE_PTRS {PCC}
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// need fill by yourself
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///** Number of interrupt vector arrays for the PCC module. */
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//#define PCC_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the PCC module. */
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//#define PCC_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the PCC peripheral type */
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//#define PCC_IRQS {PCC_IRQn}
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/* ----------------------------------------------------------------------------
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-- PCC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PCC_Register_Masks PCC Register Masks
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* @{
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*/
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/* DMA0 Bit Fields */
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#define PCC_DMA0_CGC_MASK 0x800000u
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#define PCC_DMA0_CGC_SHIFT 23u
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#define PCC_DMA0_CGC_WIDTH 1u
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#define PCC_DMA0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_DMA0_CGC_SHIFT))&PCC_DMA0_CGC_MASK)
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#define PCC_DMA0_SWR_MASK 0x10000u
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#define PCC_DMA0_SWR_SHIFT 16u
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#define PCC_DMA0_SWR_WIDTH 1u
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#define PCC_DMA0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_DMA0_SWR_SHIFT))&PCC_DMA0_SWR_MASK)
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/* DMA0 Reg Mask */
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#define PCC_DMA0_MASK 0x00810000u
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/* DMAMUX0 Bit Fields */
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#define PCC_DMAMUX0_CGC_MASK 0x800000u
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#define PCC_DMAMUX0_CGC_SHIFT 23u
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#define PCC_DMAMUX0_CGC_WIDTH 1u
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#define PCC_DMAMUX0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_DMAMUX0_CGC_SHIFT))&PCC_DMAMUX0_CGC_MASK)
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#define PCC_DMAMUX0_SWR_MASK 0x10000u
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#define PCC_DMAMUX0_SWR_SHIFT 16u
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#define PCC_DMAMUX0_SWR_WIDTH 1u
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#define PCC_DMAMUX0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_DMAMUX0_SWR_SHIFT))&PCC_DMAMUX0_SWR_MASK)
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/* DMAMUX0 Reg Mask */
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#define PCC_DMAMUX0_MASK 0x00810000u
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/* ROMC Bit Fields */
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#define PCC_ROMC_CGC_MASK 0x800000u
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#define PCC_ROMC_CGC_SHIFT 23u
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#define PCC_ROMC_CGC_WIDTH 1u
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#define PCC_ROMC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_ROMC_CGC_SHIFT))&PCC_ROMC_CGC_MASK)
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#define PCC_ROMC_SWR_MASK 0x10000u
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#define PCC_ROMC_SWR_SHIFT 16u
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#define PCC_ROMC_SWR_WIDTH 1u
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#define PCC_ROMC_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_ROMC_SWR_SHIFT))&PCC_ROMC_SWR_MASK)
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/* ROMC Reg Mask */
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#define PCC_ROMC_MASK 0x00810000u
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/* ERM Bit Fields */
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#define PCC_ERM_CGC_MASK 0x800000u
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#define PCC_ERM_CGC_SHIFT 23u
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#define PCC_ERM_CGC_WIDTH 1u
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#define PCC_ERM_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_ERM_CGC_SHIFT))&PCC_ERM_CGC_MASK)
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#define PCC_ERM_SWR_MASK 0x10000u
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#define PCC_ERM_SWR_SHIFT 16u
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#define PCC_ERM_SWR_WIDTH 1u
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#define PCC_ERM_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_ERM_SWR_SHIFT))&PCC_ERM_SWR_MASK)
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/* ERM Reg Mask */
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#define PCC_ERM_MASK 0x00810000u
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/* EIM Bit Fields */
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#define PCC_EIM_CGC_MASK 0x800000u
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#define PCC_EIM_CGC_SHIFT 23u
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#define PCC_EIM_CGC_WIDTH 1u
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#define PCC_EIM_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_EIM_CGC_SHIFT))&PCC_EIM_CGC_MASK)
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#define PCC_EIM_SWR_MASK 0x10000u
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#define PCC_EIM_SWR_SHIFT 16u
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#define PCC_EIM_SWR_WIDTH 1u
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#define PCC_EIM_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_EIM_SWR_SHIFT))&PCC_EIM_SWR_MASK)
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/* EIM Reg Mask */
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#define PCC_EIM_MASK 0x00810000u
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/* INTM0 Bit Fields */
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#define PCC_INTM0_CGC_MASK 0x800000u
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#define PCC_INTM0_CGC_SHIFT 23u
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#define PCC_INTM0_CGC_WIDTH 1u
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#define PCC_INTM0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_INTM0_CGC_SHIFT))&PCC_INTM0_CGC_MASK)
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#define PCC_INTM0_SWR_MASK 0x10000u
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#define PCC_INTM0_SWR_SHIFT 16u
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#define PCC_INTM0_SWR_WIDTH 1u
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#define PCC_INTM0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_INTM0_SWR_SHIFT))&PCC_INTM0_SWR_MASK)
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/* INTM0 Reg Mask */
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#define PCC_INTM0_MASK 0x00810000u
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/* ISM0 Bit Fields */
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#define PCC_ISM0_CGC_MASK 0x800000u
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#define PCC_ISM0_CGC_SHIFT 23u
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#define PCC_ISM0_CGC_WIDTH 1u
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#define PCC_ISM0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_ISM0_CGC_SHIFT))&PCC_ISM0_CGC_MASK)
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#define PCC_ISM0_SWR_MASK 0x10000u
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#define PCC_ISM0_SWR_SHIFT 16u
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#define PCC_ISM0_SWR_WIDTH 1u
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#define PCC_ISM0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_ISM0_SWR_SHIFT))&PCC_ISM0_SWR_MASK)
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/* ISM0 Reg Mask */
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#define PCC_ISM0_MASK 0x00810000u
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/* WDOG0 Bit Fields */
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#define PCC_WDOG0_SWR_MASK 0x10000u
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#define PCC_WDOG0_SWR_SHIFT 16u
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#define PCC_WDOG0_SWR_WIDTH 1u
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#define PCC_WDOG0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_WDOG0_SWR_SHIFT))&PCC_WDOG0_SWR_MASK)
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/* WDOG0 Reg Mask */
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#define PCC_WDOG0_MASK 0x00010000u
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/* TRGSEL0 Bit Fields */
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#define PCC_TRGSEL0_CGC_MASK 0x800000u
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#define PCC_TRGSEL0_CGC_SHIFT 23u
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#define PCC_TRGSEL0_CGC_WIDTH 1u
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#define PCC_TRGSEL0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL0_CGC_SHIFT))&PCC_TRGSEL0_CGC_MASK)
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#define PCC_TRGSEL0_SWR_MASK 0x10000u
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#define PCC_TRGSEL0_SWR_SHIFT 16u
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#define PCC_TRGSEL0_SWR_WIDTH 1u
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#define PCC_TRGSEL0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL0_SWR_SHIFT))&PCC_TRGSEL0_SWR_MASK)
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/* TRGSEL0 Reg Mask */
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#define PCC_TRGSEL0_MASK 0x00810000u
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/* TRGSEL1 Bit Fields */
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#define PCC_TRGSEL1_CGC_MASK 0x800000u
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#define PCC_TRGSEL1_CGC_SHIFT 23u
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#define PCC_TRGSEL1_CGC_WIDTH 1u
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#define PCC_TRGSEL1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL1_CGC_SHIFT))&PCC_TRGSEL1_CGC_MASK)
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#define PCC_TRGSEL1_SWR_MASK 0x10000u
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#define PCC_TRGSEL1_SWR_SHIFT 16u
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#define PCC_TRGSEL1_SWR_WIDTH 1u
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#define PCC_TRGSEL1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL1_SWR_SHIFT))&PCC_TRGSEL1_SWR_MASK)
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/* TRGSEL1 Reg Mask */
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#define PCC_TRGSEL1_MASK 0x00810000u
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/* TRGSEL2 Bit Fields */
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#define PCC_TRGSEL2_CGC_MASK 0x800000u
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#define PCC_TRGSEL2_CGC_SHIFT 23u
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#define PCC_TRGSEL2_CGC_WIDTH 1u
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#define PCC_TRGSEL2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL2_CGC_SHIFT))&PCC_TRGSEL2_CGC_MASK)
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#define PCC_TRGSEL2_SWR_MASK 0x10000u
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#define PCC_TRGSEL2_SWR_SHIFT 16u
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#define PCC_TRGSEL2_SWR_WIDTH 1u
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#define PCC_TRGSEL2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL2_SWR_SHIFT))&PCC_TRGSEL2_SWR_MASK)
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/* TRGSEL2 Reg Mask */
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#define PCC_TRGSEL2_MASK 0x00810000u
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/* TRGSEL3 Bit Fields */
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#define PCC_TRGSEL3_CGC_MASK 0x800000u
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#define PCC_TRGSEL3_CGC_SHIFT 23u
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#define PCC_TRGSEL3_CGC_WIDTH 1u
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#define PCC_TRGSEL3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL3_CGC_SHIFT))&PCC_TRGSEL3_CGC_MASK)
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#define PCC_TRGSEL3_SWR_MASK 0x10000u
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#define PCC_TRGSEL3_SWR_SHIFT 16u
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#define PCC_TRGSEL3_SWR_WIDTH 1u
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#define PCC_TRGSEL3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL3_SWR_SHIFT))&PCC_TRGSEL3_SWR_MASK)
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/* TRGSEL3 Reg Mask */
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#define PCC_TRGSEL3_MASK 0x00810000u
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/* CRC0 Bit Fields */
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#define PCC_CRC0_CGC_MASK 0x800000u
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#define PCC_CRC0_CGC_SHIFT 23u
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#define PCC_CRC0_CGC_WIDTH 1u
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#define PCC_CRC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CRC0_CGC_SHIFT))&PCC_CRC0_CGC_MASK)
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#define PCC_CRC0_SWR_MASK 0x10000u
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#define PCC_CRC0_SWR_SHIFT 16u
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#define PCC_CRC0_SWR_WIDTH 1u
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#define PCC_CRC0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CRC0_SWR_SHIFT))&PCC_CRC0_SWR_MASK)
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/* CRC0 Reg Mask */
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#define PCC_CRC0_MASK 0x00810000u
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/* CORDIC0 Bit Fields */
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#define PCC_CORDIC0_CGC_MASK 0x800000u
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#define PCC_CORDIC0_CGC_SHIFT 23u
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#define PCC_CORDIC0_CGC_WIDTH 1u
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#define PCC_CORDIC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CORDIC0_CGC_SHIFT))&PCC_CORDIC0_CGC_MASK)
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#define PCC_CORDIC0_SWR_MASK 0x10000u
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#define PCC_CORDIC0_SWR_SHIFT 16u
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#define PCC_CORDIC0_SWR_WIDTH 1u
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#define PCC_CORDIC0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CORDIC0_SWR_SHIFT))&PCC_CORDIC0_SWR_MASK)
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/* CORDIC0 Reg Mask */
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#define PCC_CORDIC0_MASK 0x00810000u
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/* TSTMP0 Bit Fields */
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#define PCC_TSTMP0_CGC_MASK 0x800000u
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#define PCC_TSTMP0_CGC_SHIFT 23u
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#define PCC_TSTMP0_CGC_WIDTH 1u
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#define PCC_TSTMP0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TSTMP0_CGC_SHIFT))&PCC_TSTMP0_CGC_MASK)
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#define PCC_TSTMP0_SWR_MASK 0x10000u
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#define PCC_TSTMP0_SWR_SHIFT 16u
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#define PCC_TSTMP0_SWR_WIDTH 1u
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#define PCC_TSTMP0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TSTMP0_SWR_SHIFT))&PCC_TSTMP0_SWR_MASK)
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/* TSTMP0 Reg Mask */
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#define PCC_TSTMP0_MASK 0x00810000u
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/* TSTMP1 Bit Fields */
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#define PCC_TSTMP1_CGC_MASK 0x800000u
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#define PCC_TSTMP1_CGC_SHIFT 23u
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#define PCC_TSTMP1_CGC_WIDTH 1u
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#define PCC_TSTMP1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TSTMP1_CGC_SHIFT))&PCC_TSTMP1_CGC_MASK)
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#define PCC_TSTMP1_SWR_MASK 0x10000u
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#define PCC_TSTMP1_SWR_SHIFT 16u
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#define PCC_TSTMP1_SWR_WIDTH 1u
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#define PCC_TSTMP1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TSTMP1_SWR_SHIFT))&PCC_TSTMP1_SWR_MASK)
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/* TSTMP1 Reg Mask */
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#define PCC_TSTMP1_MASK 0x00810000u
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/* FCPIT0 Bit Fields */
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#define PCC_FCPIT0_CGC_MASK 0x800000u
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#define PCC_FCPIT0_CGC_SHIFT 23u
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#define PCC_FCPIT0_CGC_WIDTH 1u
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#define PCC_FCPIT0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCPIT0_CGC_SHIFT))&PCC_FCPIT0_CGC_MASK)
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#define PCC_FCPIT0_SEL_MASK 0x700000u
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#define PCC_FCPIT0_SEL_SHIFT 20u
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#define PCC_FCPIT0_SEL_WIDTH 3u
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#define PCC_FCPIT0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCPIT0_SEL_SHIFT))&PCC_FCPIT0_SEL_MASK)
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#define PCC_FCPIT0_SWR_MASK 0x10000u
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#define PCC_FCPIT0_SWR_SHIFT 16u
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#define PCC_FCPIT0_SWR_WIDTH 1u
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#define PCC_FCPIT0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCPIT0_SWR_SHIFT))&PCC_FCPIT0_SWR_MASK)
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/* FCPIT0 Reg Mask */
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#define PCC_FCPIT0_MASK 0x00F10000u
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/* AONTIMER0 Bit Fields */
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#define PCC_AONTIMER0_CGC_MASK 0x800000u
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#define PCC_AONTIMER0_CGC_SHIFT 23u
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#define PCC_AONTIMER0_CGC_WIDTH 1u
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#define PCC_AONTIMER0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_AONTIMER0_CGC_SHIFT))&PCC_AONTIMER0_CGC_MASK)
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#define PCC_AONTIMER0_SEL_MASK 0x700000u
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#define PCC_AONTIMER0_SEL_SHIFT 20u
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#define PCC_AONTIMER0_SEL_WIDTH 3u
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#define PCC_AONTIMER0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_AONTIMER0_SEL_SHIFT))&PCC_AONTIMER0_SEL_MASK)
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#define PCC_AONTIMER0_SWR_MASK 0x10000u
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#define PCC_AONTIMER0_SWR_SHIFT 16u
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#define PCC_AONTIMER0_SWR_WIDTH 1u
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#define PCC_AONTIMER0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_AONTIMER0_SWR_SHIFT))&PCC_AONTIMER0_SWR_MASK)
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#define PCC_AONTIMER0_DIV_MASK 0x7u
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#define PCC_AONTIMER0_DIV_SHIFT 0u
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#define PCC_AONTIMER0_DIV_WIDTH 3u
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#define PCC_AONTIMER0_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_AONTIMER0_DIV_SHIFT))&PCC_AONTIMER0_DIV_MASK)
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/* AONTIMER0 Reg Mask */
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#define PCC_AONTIMER0_MASK 0x00F10007u
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/* RTC Bit Fields */
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#define PCC_RTC_SWR_MASK 0x10000u
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#define PCC_RTC_SWR_SHIFT 16u
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#define PCC_RTC_SWR_WIDTH 1u
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#define PCC_RTC_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_RTC_SWR_SHIFT))&PCC_RTC_SWR_MASK)
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/* RTC Reg Mask */
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#define PCC_RTC_MASK 0x00010000u
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/* CMU0 Bit Fields */
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#define PCC_CMU0_CGC_MASK 0x800000u
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#define PCC_CMU0_CGC_SHIFT 23u
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#define PCC_CMU0_CGC_WIDTH 1u
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#define PCC_CMU0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU0_CGC_SHIFT))&PCC_CMU0_CGC_MASK)
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#define PCC_CMU0_SWR_MASK 0x10000u
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#define PCC_CMU0_SWR_SHIFT 16u
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#define PCC_CMU0_SWR_WIDTH 1u
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#define PCC_CMU0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU0_SWR_SHIFT))&PCC_CMU0_SWR_MASK)
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/* CMU0 Reg Mask */
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#define PCC_CMU0_MASK 0x00810000u
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/* CMU1 Bit Fields */
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#define PCC_CMU1_CGC_MASK 0x800000u
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#define PCC_CMU1_CGC_SHIFT 23u
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#define PCC_CMU1_CGC_WIDTH 1u
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#define PCC_CMU1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU1_CGC_SHIFT))&PCC_CMU1_CGC_MASK)
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#define PCC_CMU1_SWR_MASK 0x10000u
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#define PCC_CMU1_SWR_SHIFT 16u
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#define PCC_CMU1_SWR_WIDTH 1u
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#define PCC_CMU1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU1_SWR_SHIFT))&PCC_CMU1_SWR_MASK)
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/* CMU1 Reg Mask */
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#define PCC_CMU1_MASK 0x00810000u
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/* CMU2 Bit Fields */
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#define PCC_CMU2_CGC_MASK 0x800000u
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#define PCC_CMU2_CGC_SHIFT 23u
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#define PCC_CMU2_CGC_WIDTH 1u
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#define PCC_CMU2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU2_CGC_SHIFT))&PCC_CMU2_CGC_MASK)
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#define PCC_CMU2_SWR_MASK 0x10000u
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#define PCC_CMU2_SWR_SHIFT 16u
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#define PCC_CMU2_SWR_WIDTH 1u
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#define PCC_CMU2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU2_SWR_SHIFT))&PCC_CMU2_SWR_MASK)
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/* CMU2 Reg Mask */
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#define PCC_CMU2_MASK 0x00810000u
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/* CMU3 Bit Fields */
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#define PCC_CMU3_CGC_MASK 0x800000u
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#define PCC_CMU3_CGC_SHIFT 23u
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#define PCC_CMU3_CGC_WIDTH 1u
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#define PCC_CMU3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU3_CGC_SHIFT))&PCC_CMU3_CGC_MASK)
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#define PCC_CMU3_SWR_MASK 0x10000u
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#define PCC_CMU3_SWR_SHIFT 16u
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#define PCC_CMU3_SWR_WIDTH 1u
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#define PCC_CMU3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU3_SWR_SHIFT))&PCC_CMU3_SWR_MASK)
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/* CMU3 Reg Mask */
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#define PCC_CMU3_MASK 0x00810000u
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/* CMU4 Bit Fields */
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#define PCC_CMU4_CGC_MASK 0x800000u
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#define PCC_CMU4_CGC_SHIFT 23u
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#define PCC_CMU4_CGC_WIDTH 1u
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#define PCC_CMU4_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU4_CGC_SHIFT))&PCC_CMU4_CGC_MASK)
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#define PCC_CMU4_SWR_MASK 0x10000u
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#define PCC_CMU4_SWR_SHIFT 16u
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#define PCC_CMU4_SWR_WIDTH 1u
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#define PCC_CMU4_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMU4_SWR_SHIFT))&PCC_CMU4_SWR_MASK)
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/* CMU4 Reg Mask */
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#define PCC_CMU4_MASK 0x00810000u
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/* PTIMER0 Bit Fields */
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#define PCC_PTIMER0_CGC_MASK 0x800000u
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#define PCC_PTIMER0_CGC_SHIFT 23u
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#define PCC_PTIMER0_CGC_WIDTH 1u
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#define PCC_PTIMER0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PTIMER0_CGC_SHIFT))&PCC_PTIMER0_CGC_MASK)
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#define PCC_PTIMER0_SWR_MASK 0x10000u
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#define PCC_PTIMER0_SWR_SHIFT 16u
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#define PCC_PTIMER0_SWR_WIDTH 1u
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#define PCC_PTIMER0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PTIMER0_SWR_SHIFT))&PCC_PTIMER0_SWR_MASK)
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/* PTIMER0 Reg Mask */
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#define PCC_PTIMER0_MASK 0x00810000u
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/* PTIMER1 Bit Fields */
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#define PCC_PTIMER1_CGC_MASK 0x800000u
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#define PCC_PTIMER1_CGC_SHIFT 23u
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#define PCC_PTIMER1_CGC_WIDTH 1u
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#define PCC_PTIMER1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PTIMER1_CGC_SHIFT))&PCC_PTIMER1_CGC_MASK)
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#define PCC_PTIMER1_SWR_MASK 0x10000u
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#define PCC_PTIMER1_SWR_SHIFT 16u
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#define PCC_PTIMER1_SWR_WIDTH 1u
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#define PCC_PTIMER1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PTIMER1_SWR_SHIFT))&PCC_PTIMER1_SWR_MASK)
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/* PTIMER1 Reg Mask */
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#define PCC_PTIMER1_MASK 0x00810000u
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/* ADC0 Bit Fields */
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#define PCC_ADC0_CGC_MASK 0x800000u
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#define PCC_ADC0_CGC_SHIFT 23u
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#define PCC_ADC0_CGC_WIDTH 1u
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#define PCC_ADC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC0_CGC_SHIFT))&PCC_ADC0_CGC_MASK)
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#define PCC_ADC0_SEL_MASK 0x700000u
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#define PCC_ADC0_SEL_SHIFT 20u
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#define PCC_ADC0_SEL_WIDTH 3u
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#define PCC_ADC0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC0_SEL_SHIFT))&PCC_ADC0_SEL_MASK)
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#define PCC_ADC0_SWR_MASK 0x10000u
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#define PCC_ADC0_SWR_SHIFT 16u
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#define PCC_ADC0_SWR_WIDTH 1u
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#define PCC_ADC0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC0_SWR_SHIFT))&PCC_ADC0_SWR_MASK)
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#define PCC_ADC0_DIV_MASK 0x7u
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#define PCC_ADC0_DIV_SHIFT 0u
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#define PCC_ADC0_DIV_WIDTH 3u
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#define PCC_ADC0_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC0_DIV_SHIFT))&PCC_ADC0_DIV_MASK)
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/* ADC0 Reg Mask */
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#define PCC_ADC0_MASK 0x00F10007u
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/* ADC1 Bit Fields */
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#define PCC_ADC1_CGC_MASK 0x800000u
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#define PCC_ADC1_CGC_SHIFT 23u
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#define PCC_ADC1_CGC_WIDTH 1u
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#define PCC_ADC1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC1_CGC_SHIFT))&PCC_ADC1_CGC_MASK)
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#define PCC_ADC1_SEL_MASK 0x700000u
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#define PCC_ADC1_SEL_SHIFT 20u
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#define PCC_ADC1_SEL_WIDTH 3u
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#define PCC_ADC1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC1_SEL_SHIFT))&PCC_ADC1_SEL_MASK)
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#define PCC_ADC1_SWR_MASK 0x10000u
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#define PCC_ADC1_SWR_SHIFT 16u
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#define PCC_ADC1_SWR_WIDTH 1u
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#define PCC_ADC1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC1_SWR_SHIFT))&PCC_ADC1_SWR_MASK)
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#define PCC_ADC1_DIV_MASK 0x7u
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#define PCC_ADC1_DIV_SHIFT 0u
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#define PCC_ADC1_DIV_WIDTH 3u
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#define PCC_ADC1_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_ADC1_DIV_SHIFT))&PCC_ADC1_DIV_MASK)
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/* ADC1 Reg Mask */
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#define PCC_ADC1_MASK 0x00F10007u
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/* WKU Bit Fields */
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#define PCC_WKU_CGC_MASK 0x800000u
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#define PCC_WKU_CGC_SHIFT 23u
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#define PCC_WKU_CGC_WIDTH 1u
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#define PCC_WKU_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_WKU_CGC_SHIFT))&PCC_WKU_CGC_MASK)
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#define PCC_WKU_SWR_MASK 0x10000u
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#define PCC_WKU_SWR_SHIFT 16u
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#define PCC_WKU_SWR_WIDTH 1u
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#define PCC_WKU_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_WKU_SWR_SHIFT))&PCC_WKU_SWR_MASK)
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/* WKU Reg Mask */
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#define PCC_WKU_MASK 0x00810000u
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/* CMP0 Bit Fields */
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#define PCC_CMP0_CGC_MASK 0x800000u
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#define PCC_CMP0_CGC_SHIFT 23u
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#define PCC_CMP0_CGC_WIDTH 1u
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#define PCC_CMP0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMP0_CGC_SHIFT))&PCC_CMP0_CGC_MASK)
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#define PCC_CMP0_SWR_MASK 0x10000u
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#define PCC_CMP0_SWR_SHIFT 16u
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#define PCC_CMP0_SWR_WIDTH 1u
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#define PCC_CMP0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMP0_SWR_SHIFT))&PCC_CMP0_SWR_MASK)
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/* CMP0 Reg Mask */
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#define PCC_CMP0_MASK 0x00810000u
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/* CMP1 Bit Fields */
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#define PCC_CMP1_CGC_MASK 0x800000u
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#define PCC_CMP1_CGC_SHIFT 23u
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#define PCC_CMP1_CGC_WIDTH 1u
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#define PCC_CMP1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMP1_CGC_SHIFT))&PCC_CMP1_CGC_MASK)
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#define PCC_CMP1_SWR_MASK 0x10000u
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#define PCC_CMP1_SWR_SHIFT 16u
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#define PCC_CMP1_SWR_WIDTH 1u
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#define PCC_CMP1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_CMP1_SWR_SHIFT))&PCC_CMP1_SWR_MASK)
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/* CMP1 Reg Mask */
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#define PCC_CMP1_MASK 0x00810000u
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/* TMU Bit Fields */
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#define PCC_TMU_CGC_MASK 0x800000u
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#define PCC_TMU_CGC_SHIFT 23u
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#define PCC_TMU_CGC_WIDTH 1u
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#define PCC_TMU_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TMU_CGC_SHIFT))&PCC_TMU_CGC_MASK)
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#define PCC_TMU_SEL_MASK 0x700000u
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#define PCC_TMU_SEL_SHIFT 20u
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#define PCC_TMU_SEL_WIDTH 3u
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#define PCC_TMU_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_TMU_SEL_SHIFT))&PCC_TMU_SEL_MASK)
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#define PCC_TMU_SWR_MASK 0x10000u
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#define PCC_TMU_SWR_SHIFT 16u
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#define PCC_TMU_SWR_WIDTH 1u
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#define PCC_TMU_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TMU_SWR_SHIFT))&PCC_TMU_SWR_MASK)
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/* TMU Reg Mask */
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#define PCC_TMU_MASK 0x00F10000u
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/* SENT0 Bit Fields */
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#define PCC_SENT0_CGC_MASK 0x800000u
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#define PCC_SENT0_CGC_SHIFT 23u
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#define PCC_SENT0_CGC_WIDTH 1u
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#define PCC_SENT0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_SENT0_CGC_SHIFT))&PCC_SENT0_CGC_MASK)
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#define PCC_SENT0_SEL_MASK 0x700000u
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#define PCC_SENT0_SEL_SHIFT 20u
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#define PCC_SENT0_SEL_WIDTH 3u
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#define PCC_SENT0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_SENT0_SEL_SHIFT))&PCC_SENT0_SEL_MASK)
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#define PCC_SENT0_SWR_MASK 0x10000u
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#define PCC_SENT0_SWR_SHIFT 16u
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#define PCC_SENT0_SWR_WIDTH 1u
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#define PCC_SENT0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_SENT0_SWR_SHIFT))&PCC_SENT0_SWR_MASK)
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#define PCC_SENT0_DIV_MASK 0x7u
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#define PCC_SENT0_DIV_SHIFT 0u
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#define PCC_SENT0_DIV_WIDTH 3u
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#define PCC_SENT0_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_SENT0_DIV_SHIFT))&PCC_SENT0_DIV_MASK)
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/* SENT0 Reg Mask */
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#define PCC_SENT0_MASK 0x00F10007u
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/* MB Bit Fields */
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#define PCC_MB_SWR_MASK 0x10000u
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#define PCC_MB_SWR_SHIFT 16u
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#define PCC_MB_SWR_WIDTH 1u
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#define PCC_MB_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_MB_SWR_SHIFT))&PCC_MB_SWR_MASK)
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/* MB Reg Mask */
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#define PCC_MB_MASK 0x00010000u
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/* FTU0 Bit Fields */
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#define PCC_FTU0_CGC_MASK 0x800000u
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#define PCC_FTU0_CGC_SHIFT 23u
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#define PCC_FTU0_CGC_WIDTH 1u
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#define PCC_FTU0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU0_CGC_SHIFT))&PCC_FTU0_CGC_MASK)
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#define PCC_FTU0_SEL_MASK 0x700000u
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#define PCC_FTU0_SEL_SHIFT 20u
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#define PCC_FTU0_SEL_WIDTH 3u
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#define PCC_FTU0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU0_SEL_SHIFT))&PCC_FTU0_SEL_MASK)
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#define PCC_FTU0_SWR_MASK 0x10000u
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#define PCC_FTU0_SWR_SHIFT 16u
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#define PCC_FTU0_SWR_WIDTH 1u
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#define PCC_FTU0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU0_SWR_SHIFT))&PCC_FTU0_SWR_MASK)
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/* FTU0 Reg Mask */
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#define PCC_FTU0_MASK 0x00F10000u
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/* FTU1 Bit Fields */
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#define PCC_FTU1_CGC_MASK 0x800000u
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#define PCC_FTU1_CGC_SHIFT 23u
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#define PCC_FTU1_CGC_WIDTH 1u
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#define PCC_FTU1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU1_CGC_SHIFT))&PCC_FTU1_CGC_MASK)
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#define PCC_FTU1_SEL_MASK 0x700000u
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#define PCC_FTU1_SEL_SHIFT 20u
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#define PCC_FTU1_SEL_WIDTH 3u
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#define PCC_FTU1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU1_SEL_SHIFT))&PCC_FTU1_SEL_MASK)
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#define PCC_FTU1_SWR_MASK 0x10000u
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#define PCC_FTU1_SWR_SHIFT 16u
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#define PCC_FTU1_SWR_WIDTH 1u
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#define PCC_FTU1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU1_SWR_SHIFT))&PCC_FTU1_SWR_MASK)
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/* FTU1 Reg Mask */
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#define PCC_FTU1_MASK 0x00F10000u
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/* FTU2 Bit Fields */
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#define PCC_FTU2_CGC_MASK 0x800000u
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#define PCC_FTU2_CGC_SHIFT 23u
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#define PCC_FTU2_CGC_WIDTH 1u
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#define PCC_FTU2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU2_CGC_SHIFT))&PCC_FTU2_CGC_MASK)
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#define PCC_FTU2_SEL_MASK 0x700000u
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#define PCC_FTU2_SEL_SHIFT 20u
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#define PCC_FTU2_SEL_WIDTH 3u
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#define PCC_FTU2_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU2_SEL_SHIFT))&PCC_FTU2_SEL_MASK)
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#define PCC_FTU2_SWR_MASK 0x10000u
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#define PCC_FTU2_SWR_SHIFT 16u
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#define PCC_FTU2_SWR_WIDTH 1u
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#define PCC_FTU2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU2_SWR_SHIFT))&PCC_FTU2_SWR_MASK)
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/* FTU2 Reg Mask */
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#define PCC_FTU2_MASK 0x00F10000u
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/* FTU3 Bit Fields */
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#define PCC_FTU3_CGC_MASK 0x800000u
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#define PCC_FTU3_CGC_SHIFT 23u
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#define PCC_FTU3_CGC_WIDTH 1u
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#define PCC_FTU3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU3_CGC_SHIFT))&PCC_FTU3_CGC_MASK)
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#define PCC_FTU3_SEL_MASK 0x700000u
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#define PCC_FTU3_SEL_SHIFT 20u
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#define PCC_FTU3_SEL_WIDTH 3u
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#define PCC_FTU3_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU3_SEL_SHIFT))&PCC_FTU3_SEL_MASK)
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#define PCC_FTU3_SWR_MASK 0x10000u
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#define PCC_FTU3_SWR_SHIFT 16u
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#define PCC_FTU3_SWR_WIDTH 1u
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#define PCC_FTU3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU3_SWR_SHIFT))&PCC_FTU3_SWR_MASK)
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/* FTU3 Reg Mask */
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#define PCC_FTU3_MASK 0x00F10000u
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/* FCSPI0 Bit Fields */
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#define PCC_FCSPI0_CGC_MASK 0x800000u
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#define PCC_FCSPI0_CGC_SHIFT 23u
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#define PCC_FCSPI0_CGC_WIDTH 1u
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#define PCC_FCSPI0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI0_CGC_SHIFT))&PCC_FCSPI0_CGC_MASK)
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#define PCC_FCSPI0_SEL_MASK 0x700000u
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#define PCC_FCSPI0_SEL_SHIFT 20u
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#define PCC_FCSPI0_SEL_WIDTH 3u
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#define PCC_FCSPI0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI0_SEL_SHIFT))&PCC_FCSPI0_SEL_MASK)
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#define PCC_FCSPI0_SWR_MASK 0x10000u
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#define PCC_FCSPI0_SWR_SHIFT 16u
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#define PCC_FCSPI0_SWR_WIDTH 1u
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#define PCC_FCSPI0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI0_SWR_SHIFT))&PCC_FCSPI0_SWR_MASK)
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/* FCSPI0 Reg Mask */
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#define PCC_FCSPI0_MASK 0x00F10000u
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/* FCSPI1 Bit Fields */
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#define PCC_FCSPI1_CGC_MASK 0x800000u
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#define PCC_FCSPI1_CGC_SHIFT 23u
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#define PCC_FCSPI1_CGC_WIDTH 1u
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#define PCC_FCSPI1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI1_CGC_SHIFT))&PCC_FCSPI1_CGC_MASK)
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#define PCC_FCSPI1_SEL_MASK 0x700000u
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#define PCC_FCSPI1_SEL_SHIFT 20u
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#define PCC_FCSPI1_SEL_WIDTH 3u
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#define PCC_FCSPI1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI1_SEL_SHIFT))&PCC_FCSPI1_SEL_MASK)
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#define PCC_FCSPI1_SWR_MASK 0x10000u
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#define PCC_FCSPI1_SWR_SHIFT 16u
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#define PCC_FCSPI1_SWR_WIDTH 1u
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#define PCC_FCSPI1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI1_SWR_SHIFT))&PCC_FCSPI1_SWR_MASK)
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/* FCSPI1 Reg Mask */
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#define PCC_FCSPI1_MASK 0x00F10000u
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/* FCSPI2 Bit Fields */
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#define PCC_FCSPI2_CGC_MASK 0x800000u
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#define PCC_FCSPI2_CGC_SHIFT 23u
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#define PCC_FCSPI2_CGC_WIDTH 1u
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#define PCC_FCSPI2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI2_CGC_SHIFT))&PCC_FCSPI2_CGC_MASK)
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#define PCC_FCSPI2_SEL_MASK 0x700000u
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#define PCC_FCSPI2_SEL_SHIFT 20u
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#define PCC_FCSPI2_SEL_WIDTH 3u
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#define PCC_FCSPI2_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI2_SEL_SHIFT))&PCC_FCSPI2_SEL_MASK)
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#define PCC_FCSPI2_SWR_MASK 0x10000u
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#define PCC_FCSPI2_SWR_SHIFT 16u
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#define PCC_FCSPI2_SWR_WIDTH 1u
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#define PCC_FCSPI2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI2_SWR_SHIFT))&PCC_FCSPI2_SWR_MASK)
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/* FCSPI2 Reg Mask */
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#define PCC_FCSPI2_MASK 0x00F10000u
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/* FCIIC0 Bit Fields */
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#define PCC_FCIIC0_CGC_MASK 0x800000u
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#define PCC_FCIIC0_CGC_SHIFT 23u
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#define PCC_FCIIC0_CGC_WIDTH 1u
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#define PCC_FCIIC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC0_CGC_SHIFT))&PCC_FCIIC0_CGC_MASK)
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#define PCC_FCIIC0_SEL_MASK 0x700000u
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#define PCC_FCIIC0_SEL_SHIFT 20u
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#define PCC_FCIIC0_SEL_WIDTH 3u
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#define PCC_FCIIC0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC0_SEL_SHIFT))&PCC_FCIIC0_SEL_MASK)
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#define PCC_FCIIC0_SWR_MASK 0x10000u
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#define PCC_FCIIC0_SWR_SHIFT 16u
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#define PCC_FCIIC0_SWR_WIDTH 1u
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#define PCC_FCIIC0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC0_SWR_SHIFT))&PCC_FCIIC0_SWR_MASK)
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/* FCIIC0 Reg Mask */
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#define PCC_FCIIC0_MASK 0x00F10000u
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/* FCUART0 Bit Fields */
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#define PCC_FCUART0_CGC_MASK 0x800000u
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#define PCC_FCUART0_CGC_SHIFT 23u
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#define PCC_FCUART0_CGC_WIDTH 1u
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#define PCC_FCUART0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART0_CGC_SHIFT))&PCC_FCUART0_CGC_MASK)
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#define PCC_FCUART0_SEL_MASK 0x700000u
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#define PCC_FCUART0_SEL_SHIFT 20u
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#define PCC_FCUART0_SEL_WIDTH 3u
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#define PCC_FCUART0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART0_SEL_SHIFT))&PCC_FCUART0_SEL_MASK)
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#define PCC_FCUART0_SWR_MASK 0x10000u
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#define PCC_FCUART0_SWR_SHIFT 16u
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#define PCC_FCUART0_SWR_WIDTH 1u
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#define PCC_FCUART0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART0_SWR_SHIFT))&PCC_FCUART0_SWR_MASK)
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/* FCUART0 Reg Mask */
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#define PCC_FCUART0_MASK 0x00F10000u
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/* FCUART1 Bit Fields */
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#define PCC_FCUART1_CGC_MASK 0x800000u
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#define PCC_FCUART1_CGC_SHIFT 23u
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#define PCC_FCUART1_CGC_WIDTH 1u
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#define PCC_FCUART1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART1_CGC_SHIFT))&PCC_FCUART1_CGC_MASK)
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#define PCC_FCUART1_SEL_MASK 0x700000u
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#define PCC_FCUART1_SEL_SHIFT 20u
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#define PCC_FCUART1_SEL_WIDTH 3u
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#define PCC_FCUART1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART1_SEL_SHIFT))&PCC_FCUART1_SEL_MASK)
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#define PCC_FCUART1_SWR_MASK 0x10000u
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#define PCC_FCUART1_SWR_SHIFT 16u
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#define PCC_FCUART1_SWR_WIDTH 1u
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#define PCC_FCUART1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART1_SWR_SHIFT))&PCC_FCUART1_SWR_MASK)
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/* FCUART1 Reg Mask */
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#define PCC_FCUART1_MASK 0x00F10000u
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/* FCUART2 Bit Fields */
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#define PCC_FCUART2_CGC_MASK 0x800000u
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#define PCC_FCUART2_CGC_SHIFT 23u
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#define PCC_FCUART2_CGC_WIDTH 1u
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#define PCC_FCUART2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART2_CGC_SHIFT))&PCC_FCUART2_CGC_MASK)
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#define PCC_FCUART2_SEL_MASK 0x700000u
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#define PCC_FCUART2_SEL_SHIFT 20u
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#define PCC_FCUART2_SEL_WIDTH 3u
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#define PCC_FCUART2_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART2_SEL_SHIFT))&PCC_FCUART2_SEL_MASK)
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#define PCC_FCUART2_SWR_MASK 0x10000u
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#define PCC_FCUART2_SWR_SHIFT 16u
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#define PCC_FCUART2_SWR_WIDTH 1u
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#define PCC_FCUART2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART2_SWR_SHIFT))&PCC_FCUART2_SWR_MASK)
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/* FCUART2 Reg Mask */
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#define PCC_FCUART2_MASK 0x00F10000u
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/* FCUART3 Bit Fields */
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#define PCC_FCUART3_CGC_MASK 0x800000u
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#define PCC_FCUART3_CGC_SHIFT 23u
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#define PCC_FCUART3_CGC_WIDTH 1u
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#define PCC_FCUART3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART3_CGC_SHIFT))&PCC_FCUART3_CGC_MASK)
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#define PCC_FCUART3_SEL_MASK 0x700000u
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#define PCC_FCUART3_SEL_SHIFT 20u
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#define PCC_FCUART3_SEL_WIDTH 3u
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#define PCC_FCUART3_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART3_SEL_SHIFT))&PCC_FCUART3_SEL_MASK)
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#define PCC_FCUART3_SWR_MASK 0x10000u
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#define PCC_FCUART3_SWR_SHIFT 16u
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#define PCC_FCUART3_SWR_WIDTH 1u
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#define PCC_FCUART3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART3_SWR_SHIFT))&PCC_FCUART3_SWR_MASK)
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/* FCUART3 Reg Mask */
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#define PCC_FCUART3_MASK 0x00F10000u
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/* LU0 Bit Fields */
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#define PCC_LU0_CGC_MASK 0x800000u
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#define PCC_LU0_CGC_SHIFT 23u
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#define PCC_LU0_CGC_WIDTH 1u
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#define PCC_LU0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_LU0_CGC_SHIFT))&PCC_LU0_CGC_MASK)
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#define PCC_LU0_SWR_MASK 0x10000u
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#define PCC_LU0_SWR_SHIFT 16u
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#define PCC_LU0_SWR_WIDTH 1u
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#define PCC_LU0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_LU0_SWR_SHIFT))&PCC_LU0_SWR_MASK)
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/* LU0 Reg Mask */
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#define PCC_LU0_MASK 0x00810000u
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/* FREQM Bit Fields */
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#define PCC_FREQM_CGC_MASK 0x800000u
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#define PCC_FREQM_CGC_SHIFT 23u
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#define PCC_FREQM_CGC_WIDTH 1u
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#define PCC_FREQM_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FREQM_CGC_SHIFT))&PCC_FREQM_CGC_MASK)
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#define PCC_FREQM_SWR_MASK 0x10000u
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#define PCC_FREQM_SWR_SHIFT 16u
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#define PCC_FREQM_SWR_WIDTH 1u
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#define PCC_FREQM_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FREQM_SWR_SHIFT))&PCC_FREQM_SWR_MASK)
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/* FREQM Reg Mask */
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#define PCC_FREQM_MASK 0x00810000u
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/* STCU Bit Fields */
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#define PCC_STCU_CGC_MASK 0x800000u
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#define PCC_STCU_CGC_SHIFT 23u
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#define PCC_STCU_CGC_WIDTH 1u
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#define PCC_STCU_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_STCU_CGC_SHIFT))&PCC_STCU_CGC_MASK)
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#define PCC_STCU_SWR_MASK 0x10000u
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#define PCC_STCU_SWR_SHIFT 16u
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#define PCC_STCU_SWR_WIDTH 1u
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#define PCC_STCU_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_STCU_SWR_SHIFT))&PCC_STCU_SWR_MASK)
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/* STCU Reg Mask */
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#define PCC_STCU_MASK 0x00810000u
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/* FLEXCAN0 Bit Fields */
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#define PCC_FLEXCAN0_CGC_MASK 0x800000u
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#define PCC_FLEXCAN0_CGC_SHIFT 23u
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#define PCC_FLEXCAN0_CGC_WIDTH 1u
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#define PCC_FLEXCAN0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN0_CGC_SHIFT))&PCC_FLEXCAN0_CGC_MASK)
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#define PCC_FLEXCAN0_SEL_MASK 0x700000u
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#define PCC_FLEXCAN0_SEL_SHIFT 20u
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#define PCC_FLEXCAN0_SEL_WIDTH 3u
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#define PCC_FLEXCAN0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN0_SEL_SHIFT))&PCC_FLEXCAN0_SEL_MASK)
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#define PCC_FLEXCAN0_SWR_MASK 0x10000u
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#define PCC_FLEXCAN0_SWR_SHIFT 16u
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#define PCC_FLEXCAN0_SWR_WIDTH 1u
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#define PCC_FLEXCAN0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN0_SWR_SHIFT))&PCC_FLEXCAN0_SWR_MASK)
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#define PCC_FLEXCAN0_DIV_MASK 0x7u
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#define PCC_FLEXCAN0_DIV_SHIFT 0u
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#define PCC_FLEXCAN0_DIV_WIDTH 3u
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#define PCC_FLEXCAN0_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN0_DIV_SHIFT))&PCC_FLEXCAN0_DIV_MASK)
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/* FLEXCAN0 Reg Mask */
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#define PCC_FLEXCAN0_MASK 0x00F10007u
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/* FLEXCAN1 Bit Fields */
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#define PCC_FLEXCAN1_CGC_MASK 0x800000u
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#define PCC_FLEXCAN1_CGC_SHIFT 23u
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#define PCC_FLEXCAN1_CGC_WIDTH 1u
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#define PCC_FLEXCAN1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN1_CGC_SHIFT))&PCC_FLEXCAN1_CGC_MASK)
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#define PCC_FLEXCAN1_SEL_MASK 0x700000u
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#define PCC_FLEXCAN1_SEL_SHIFT 20u
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#define PCC_FLEXCAN1_SEL_WIDTH 3u
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#define PCC_FLEXCAN1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN1_SEL_SHIFT))&PCC_FLEXCAN1_SEL_MASK)
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#define PCC_FLEXCAN1_SWR_MASK 0x10000u
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#define PCC_FLEXCAN1_SWR_SHIFT 16u
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#define PCC_FLEXCAN1_SWR_WIDTH 1u
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#define PCC_FLEXCAN1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN1_SWR_SHIFT))&PCC_FLEXCAN1_SWR_MASK)
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#define PCC_FLEXCAN1_DIV_MASK 0x7u
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#define PCC_FLEXCAN1_DIV_SHIFT 0u
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#define PCC_FLEXCAN1_DIV_WIDTH 3u
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#define PCC_FLEXCAN1_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN1_DIV_SHIFT))&PCC_FLEXCAN1_DIV_MASK)
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/* FLEXCAN1 Reg Mask */
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#define PCC_FLEXCAN1_MASK 0x00F10007u
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/* WDOG1 Bit Fields */
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#define PCC_WDOG1_SWR_MASK 0x10000u
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#define PCC_WDOG1_SWR_SHIFT 16u
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#define PCC_WDOG1_SWR_WIDTH 1u
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#define PCC_WDOG1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_WDOG1_SWR_SHIFT))&PCC_WDOG1_SWR_MASK)
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/* WDOG1 Reg Mask */
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#define PCC_WDOG1_MASK 0x00010000u
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/* TRGSEL4 Bit Fields */
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#define PCC_TRGSEL4_CGC_MASK 0x800000u
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#define PCC_TRGSEL4_CGC_SHIFT 23u
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#define PCC_TRGSEL4_CGC_WIDTH 1u
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#define PCC_TRGSEL4_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL4_CGC_SHIFT))&PCC_TRGSEL4_CGC_MASK)
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#define PCC_TRGSEL4_SWR_MASK 0x10000u
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#define PCC_TRGSEL4_SWR_SHIFT 16u
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#define PCC_TRGSEL4_SWR_WIDTH 1u
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#define PCC_TRGSEL4_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL4_SWR_SHIFT))&PCC_TRGSEL4_SWR_MASK)
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/* TRGSEL4 Reg Mask */
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#define PCC_TRGSEL4_MASK 0x00810000u
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/* TRGSEL5 Bit Fields */
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#define PCC_TRGSEL5_CGC_MASK 0x800000u
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#define PCC_TRGSEL5_CGC_SHIFT 23u
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#define PCC_TRGSEL5_CGC_WIDTH 1u
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#define PCC_TRGSEL5_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL5_CGC_SHIFT))&PCC_TRGSEL5_CGC_MASK)
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#define PCC_TRGSEL5_SWR_MASK 0x10000u
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#define PCC_TRGSEL5_SWR_SHIFT 16u
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#define PCC_TRGSEL5_SWR_WIDTH 1u
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#define PCC_TRGSEL5_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_TRGSEL5_SWR_SHIFT))&PCC_TRGSEL5_SWR_MASK)
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/* TRGSEL5 Reg Mask */
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#define PCC_TRGSEL5_MASK 0x00810000u
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/* FCSPI3 Bit Fields */
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#define PCC_FCSPI3_CGC_MASK 0x800000u
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#define PCC_FCSPI3_CGC_SHIFT 23u
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#define PCC_FCSPI3_CGC_WIDTH 1u
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#define PCC_FCSPI3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI3_CGC_SHIFT))&PCC_FCSPI3_CGC_MASK)
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#define PCC_FCSPI3_SEL_MASK 0x700000u
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#define PCC_FCSPI3_SEL_SHIFT 20u
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#define PCC_FCSPI3_SEL_WIDTH 3u
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#define PCC_FCSPI3_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI3_SEL_SHIFT))&PCC_FCSPI3_SEL_MASK)
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#define PCC_FCSPI3_SWR_MASK 0x10000u
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#define PCC_FCSPI3_SWR_SHIFT 16u
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#define PCC_FCSPI3_SWR_WIDTH 1u
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#define PCC_FCSPI3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI3_SWR_SHIFT))&PCC_FCSPI3_SWR_MASK)
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/* FCSPI3 Reg Mask */
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#define PCC_FCSPI3_MASK 0x00F10000u
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/* FCSPI4 Bit Fields */
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#define PCC_FCSPI4_CGC_MASK 0x800000u
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#define PCC_FCSPI4_CGC_SHIFT 23u
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#define PCC_FCSPI4_CGC_WIDTH 1u
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#define PCC_FCSPI4_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI4_CGC_SHIFT))&PCC_FCSPI4_CGC_MASK)
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#define PCC_FCSPI4_SEL_MASK 0x700000u
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#define PCC_FCSPI4_SEL_SHIFT 20u
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#define PCC_FCSPI4_SEL_WIDTH 3u
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#define PCC_FCSPI4_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI4_SEL_SHIFT))&PCC_FCSPI4_SEL_MASK)
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#define PCC_FCSPI4_SWR_MASK 0x10000u
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#define PCC_FCSPI4_SWR_SHIFT 16u
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#define PCC_FCSPI4_SWR_WIDTH 1u
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#define PCC_FCSPI4_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI4_SWR_SHIFT))&PCC_FCSPI4_SWR_MASK)
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/* FCSPI4 Reg Mask */
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#define PCC_FCSPI4_MASK 0x00F10000u
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/* FCSPI5 Bit Fields */
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#define PCC_FCSPI5_CGC_MASK 0x800000u
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#define PCC_FCSPI5_CGC_SHIFT 23u
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#define PCC_FCSPI5_CGC_WIDTH 1u
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#define PCC_FCSPI5_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI5_CGC_SHIFT))&PCC_FCSPI5_CGC_MASK)
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#define PCC_FCSPI5_SEL_MASK 0x700000u
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#define PCC_FCSPI5_SEL_SHIFT 20u
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#define PCC_FCSPI5_SEL_WIDTH 3u
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#define PCC_FCSPI5_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI5_SEL_SHIFT))&PCC_FCSPI5_SEL_MASK)
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#define PCC_FCSPI5_SWR_MASK 0x10000u
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#define PCC_FCSPI5_SWR_SHIFT 16u
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#define PCC_FCSPI5_SWR_WIDTH 1u
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#define PCC_FCSPI5_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCSPI5_SWR_SHIFT))&PCC_FCSPI5_SWR_MASK)
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/* FCSPI5 Reg Mask */
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#define PCC_FCSPI5_MASK 0x00F10000u
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/* FTU4 Bit Fields */
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#define PCC_FTU4_CGC_MASK 0x800000u
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#define PCC_FTU4_CGC_SHIFT 23u
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#define PCC_FTU4_CGC_WIDTH 1u
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#define PCC_FTU4_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU4_CGC_SHIFT))&PCC_FTU4_CGC_MASK)
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#define PCC_FTU4_SEL_MASK 0x700000u
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#define PCC_FTU4_SEL_SHIFT 20u
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#define PCC_FTU4_SEL_WIDTH 3u
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#define PCC_FTU4_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU4_SEL_SHIFT))&PCC_FTU4_SEL_MASK)
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#define PCC_FTU4_SWR_MASK 0x10000u
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#define PCC_FTU4_SWR_SHIFT 16u
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#define PCC_FTU4_SWR_WIDTH 1u
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#define PCC_FTU4_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU4_SWR_SHIFT))&PCC_FTU4_SWR_MASK)
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/* FTU4 Reg Mask */
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#define PCC_FTU4_MASK 0x00F10000u
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/* FTU5 Bit Fields */
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#define PCC_FTU5_CGC_MASK 0x800000u
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#define PCC_FTU5_CGC_SHIFT 23u
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#define PCC_FTU5_CGC_WIDTH 1u
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#define PCC_FTU5_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU5_CGC_SHIFT))&PCC_FTU5_CGC_MASK)
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#define PCC_FTU5_SEL_MASK 0x700000u
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#define PCC_FTU5_SEL_SHIFT 20u
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#define PCC_FTU5_SEL_WIDTH 3u
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#define PCC_FTU5_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU5_SEL_SHIFT))&PCC_FTU5_SEL_MASK)
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#define PCC_FTU5_SWR_MASK 0x10000u
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#define PCC_FTU5_SWR_SHIFT 16u
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#define PCC_FTU5_SWR_WIDTH 1u
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#define PCC_FTU5_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU5_SWR_SHIFT))&PCC_FTU5_SWR_MASK)
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/* FTU5 Reg Mask */
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#define PCC_FTU5_MASK 0x00F10000u
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/* FTU6 Bit Fields */
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#define PCC_FTU6_CGC_MASK 0x800000u
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#define PCC_FTU6_CGC_SHIFT 23u
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#define PCC_FTU6_CGC_WIDTH 1u
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#define PCC_FTU6_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU6_CGC_SHIFT))&PCC_FTU6_CGC_MASK)
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#define PCC_FTU6_SEL_MASK 0x700000u
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#define PCC_FTU6_SEL_SHIFT 20u
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#define PCC_FTU6_SEL_WIDTH 3u
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#define PCC_FTU6_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU6_SEL_SHIFT))&PCC_FTU6_SEL_MASK)
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#define PCC_FTU6_SWR_MASK 0x10000u
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#define PCC_FTU6_SWR_SHIFT 16u
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#define PCC_FTU6_SWR_WIDTH 1u
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#define PCC_FTU6_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU6_SWR_SHIFT))&PCC_FTU6_SWR_MASK)
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/* FTU6 Reg Mask */
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#define PCC_FTU6_MASK 0x00F10000u
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/* FTU7 Bit Fields */
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#define PCC_FTU7_CGC_MASK 0x800000u
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#define PCC_FTU7_CGC_SHIFT 23u
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#define PCC_FTU7_CGC_WIDTH 1u
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#define PCC_FTU7_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU7_CGC_SHIFT))&PCC_FTU7_CGC_MASK)
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#define PCC_FTU7_SEL_MASK 0x700000u
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#define PCC_FTU7_SEL_SHIFT 20u
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#define PCC_FTU7_SEL_WIDTH 3u
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#define PCC_FTU7_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU7_SEL_SHIFT))&PCC_FTU7_SEL_MASK)
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#define PCC_FTU7_SWR_MASK 0x10000u
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#define PCC_FTU7_SWR_SHIFT 16u
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#define PCC_FTU7_SWR_WIDTH 1u
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#define PCC_FTU7_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FTU7_SWR_SHIFT))&PCC_FTU7_SWR_MASK)
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/* FTU7 Reg Mask */
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#define PCC_FTU7_MASK 0x00F10000u
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/* FCIIC1 Bit Fields */
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#define PCC_FCIIC1_CGC_MASK 0x800000u
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#define PCC_FCIIC1_CGC_SHIFT 23u
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#define PCC_FCIIC1_CGC_WIDTH 1u
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#define PCC_FCIIC1_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC1_CGC_SHIFT))&PCC_FCIIC1_CGC_MASK)
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#define PCC_FCIIC1_SEL_MASK 0x700000u
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#define PCC_FCIIC1_SEL_SHIFT 20u
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#define PCC_FCIIC1_SEL_WIDTH 3u
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#define PCC_FCIIC1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC1_SEL_SHIFT))&PCC_FCIIC1_SEL_MASK)
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#define PCC_FCIIC1_SWR_MASK 0x10000u
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#define PCC_FCIIC1_SWR_SHIFT 16u
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#define PCC_FCIIC1_SWR_WIDTH 1u
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#define PCC_FCIIC1_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCIIC1_SWR_SHIFT))&PCC_FCIIC1_SWR_MASK)
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/* FCIIC1 Reg Mask */
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#define PCC_FCIIC1_MASK 0x00F10000u
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/* FCUART4 Bit Fields */
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#define PCC_FCUART4_CGC_MASK 0x800000u
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#define PCC_FCUART4_CGC_SHIFT 23u
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#define PCC_FCUART4_CGC_WIDTH 1u
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#define PCC_FCUART4_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART4_CGC_SHIFT))&PCC_FCUART4_CGC_MASK)
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#define PCC_FCUART4_SEL_MASK 0x700000u
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#define PCC_FCUART4_SEL_SHIFT 20u
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#define PCC_FCUART4_SEL_WIDTH 3u
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#define PCC_FCUART4_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART4_SEL_SHIFT))&PCC_FCUART4_SEL_MASK)
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#define PCC_FCUART4_SWR_MASK 0x10000u
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#define PCC_FCUART4_SWR_SHIFT 16u
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#define PCC_FCUART4_SWR_WIDTH 1u
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#define PCC_FCUART4_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART4_SWR_SHIFT))&PCC_FCUART4_SWR_MASK)
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/* FCUART4 Reg Mask */
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#define PCC_FCUART4_MASK 0x00F10000u
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/* FCUART5 Bit Fields */
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#define PCC_FCUART5_CGC_MASK 0x800000u
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#define PCC_FCUART5_CGC_SHIFT 23u
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#define PCC_FCUART5_CGC_WIDTH 1u
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#define PCC_FCUART5_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART5_CGC_SHIFT))&PCC_FCUART5_CGC_MASK)
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#define PCC_FCUART5_SEL_MASK 0x700000u
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#define PCC_FCUART5_SEL_SHIFT 20u
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#define PCC_FCUART5_SEL_WIDTH 3u
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#define PCC_FCUART5_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART5_SEL_SHIFT))&PCC_FCUART5_SEL_MASK)
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#define PCC_FCUART5_SWR_MASK 0x10000u
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#define PCC_FCUART5_SWR_SHIFT 16u
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#define PCC_FCUART5_SWR_WIDTH 1u
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#define PCC_FCUART5_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART5_SWR_SHIFT))&PCC_FCUART5_SWR_MASK)
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/* FCUART5 Reg Mask */
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#define PCC_FCUART5_MASK 0x00F10000u
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/* FCUART6 Bit Fields */
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#define PCC_FCUART6_CGC_MASK 0x800000u
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#define PCC_FCUART6_CGC_SHIFT 23u
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#define PCC_FCUART6_CGC_WIDTH 1u
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#define PCC_FCUART6_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART6_CGC_SHIFT))&PCC_FCUART6_CGC_MASK)
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#define PCC_FCUART6_SEL_MASK 0x700000u
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#define PCC_FCUART6_SEL_SHIFT 20u
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#define PCC_FCUART6_SEL_WIDTH 3u
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#define PCC_FCUART6_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART6_SEL_SHIFT))&PCC_FCUART6_SEL_MASK)
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#define PCC_FCUART6_SWR_MASK 0x10000u
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#define PCC_FCUART6_SWR_SHIFT 16u
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#define PCC_FCUART6_SWR_WIDTH 1u
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#define PCC_FCUART6_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART6_SWR_SHIFT))&PCC_FCUART6_SWR_MASK)
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/* FCUART6 Reg Mask */
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#define PCC_FCUART6_MASK 0x00F10000u
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/* FCUART7 Bit Fields */
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#define PCC_FCUART7_CGC_MASK 0x800000u
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#define PCC_FCUART7_CGC_SHIFT 23u
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#define PCC_FCUART7_CGC_WIDTH 1u
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#define PCC_FCUART7_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART7_CGC_SHIFT))&PCC_FCUART7_CGC_MASK)
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#define PCC_FCUART7_SEL_MASK 0x700000u
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#define PCC_FCUART7_SEL_SHIFT 20u
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#define PCC_FCUART7_SEL_WIDTH 3u
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#define PCC_FCUART7_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART7_SEL_SHIFT))&PCC_FCUART7_SEL_MASK)
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#define PCC_FCUART7_SWR_MASK 0x10000u
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#define PCC_FCUART7_SWR_SHIFT 16u
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#define PCC_FCUART7_SWR_WIDTH 1u
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#define PCC_FCUART7_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FCUART7_SWR_SHIFT))&PCC_FCUART7_SWR_MASK)
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/* FCUART7 Reg Mask */
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#define PCC_FCUART7_MASK 0x00F10000u
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/* MSC0 Bit Fields */
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#define PCC_MSC0_CGC_MASK 0x800000u
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#define PCC_MSC0_CGC_SHIFT 23u
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#define PCC_MSC0_CGC_WIDTH 1u
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#define PCC_MSC0_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_MSC0_CGC_SHIFT))&PCC_MSC0_CGC_MASK)
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#define PCC_MSC0_SEL_MASK 0x700000u
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#define PCC_MSC0_SEL_SHIFT 20u
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#define PCC_MSC0_SEL_WIDTH 3u
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#define PCC_MSC0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_MSC0_SEL_SHIFT))&PCC_MSC0_SEL_MASK)
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#define PCC_MSC0_SWR_MASK 0x10000u
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#define PCC_MSC0_SWR_SHIFT 16u
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#define PCC_MSC0_SWR_WIDTH 1u
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#define PCC_MSC0_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_MSC0_SWR_SHIFT))&PCC_MSC0_SWR_MASK)
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#define PCC_MSC0_DIV_MASK 0x7u
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#define PCC_MSC0_DIV_SHIFT 0u
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#define PCC_MSC0_DIV_WIDTH 3u
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#define PCC_MSC0_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_MSC0_DIV_SHIFT))&PCC_MSC0_DIV_MASK)
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/* MSC0 Reg Mask */
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#define PCC_MSC0_MASK 0x00F10007u
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/* FLEXCAN2 Bit Fields */
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#define PCC_FLEXCAN2_CGC_MASK 0x800000u
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#define PCC_FLEXCAN2_CGC_SHIFT 23u
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#define PCC_FLEXCAN2_CGC_WIDTH 1u
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#define PCC_FLEXCAN2_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN2_CGC_SHIFT))&PCC_FLEXCAN2_CGC_MASK)
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#define PCC_FLEXCAN2_SEL_MASK 0x700000u
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#define PCC_FLEXCAN2_SEL_SHIFT 20u
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#define PCC_FLEXCAN2_SEL_WIDTH 3u
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#define PCC_FLEXCAN2_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN2_SEL_SHIFT))&PCC_FLEXCAN2_SEL_MASK)
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#define PCC_FLEXCAN2_SWR_MASK 0x10000u
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#define PCC_FLEXCAN2_SWR_SHIFT 16u
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#define PCC_FLEXCAN2_SWR_WIDTH 1u
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#define PCC_FLEXCAN2_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN2_SWR_SHIFT))&PCC_FLEXCAN2_SWR_MASK)
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#define PCC_FLEXCAN2_DIV_MASK 0x7u
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#define PCC_FLEXCAN2_DIV_SHIFT 0u
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#define PCC_FLEXCAN2_DIV_WIDTH 3u
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#define PCC_FLEXCAN2_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN2_DIV_SHIFT))&PCC_FLEXCAN2_DIV_MASK)
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/* FLEXCAN2 Reg Mask */
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#define PCC_FLEXCAN2_MASK 0x00F10007u
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/* FLEXCAN3 Bit Fields */
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#define PCC_FLEXCAN3_CGC_MASK 0x800000u
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#define PCC_FLEXCAN3_CGC_SHIFT 23u
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#define PCC_FLEXCAN3_CGC_WIDTH 1u
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#define PCC_FLEXCAN3_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN3_CGC_SHIFT))&PCC_FLEXCAN3_CGC_MASK)
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#define PCC_FLEXCAN3_SEL_MASK 0x700000u
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#define PCC_FLEXCAN3_SEL_SHIFT 20u
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#define PCC_FLEXCAN3_SEL_WIDTH 3u
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#define PCC_FLEXCAN3_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN3_SEL_SHIFT))&PCC_FLEXCAN3_SEL_MASK)
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#define PCC_FLEXCAN3_SWR_MASK 0x10000u
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#define PCC_FLEXCAN3_SWR_SHIFT 16u
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#define PCC_FLEXCAN3_SWR_WIDTH 1u
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#define PCC_FLEXCAN3_SWR(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN3_SWR_SHIFT))&PCC_FLEXCAN3_SWR_MASK)
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#define PCC_FLEXCAN3_DIV_MASK 0x7u
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#define PCC_FLEXCAN3_DIV_SHIFT 0u
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#define PCC_FLEXCAN3_DIV_WIDTH 3u
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#define PCC_FLEXCAN3_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_FLEXCAN3_DIV_SHIFT))&PCC_FLEXCAN3_DIV_MASK)
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/* FLEXCAN3 Reg Mask */
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#define PCC_FLEXCAN3_MASK 0x00F10007u
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/*!
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* @}
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*/ /* end of group PCC_Register_Masks */
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/*!
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* @}
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*/ /* end of group PCC_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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