284 lines
5.9 KiB
C
284 lines
5.9 KiB
C
#ifndef _FC7240_GPIO_NU_Tztufn42_REGS_H_
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#define _FC7240_GPIO_NU_Tztufn42_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- GPIO Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
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* @{
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*/
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/** GPIO - Size of Registers Arrays */
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/** GPIO - Register Layout Typedef */
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typedef struct {
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__IO uint32_t PDOR ; /* Port Data Output Register, offset: 0x0 */
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__O uint32_t PSOR ; /* Port Set Output Register, offset: 0x4 */
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__O uint32_t PCOR ; /* Port Clear Output Register, offset: 0x8 */
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__O uint32_t PTOR ; /* Port Toggle Output Register, offset: 0xC */
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__I uint32_t PDIR ; /* Port Data Input Register, offset: 0x10 */
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__IO uint32_t PDDR ; /* Port Data Direction Register, offset: 0x14 */
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__IO uint32_t PIDR ; /* Port Input Disable Register, offset: 0x18 */
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} GPIO_Type, *GPIO_MemMapPtr;
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/** Number of instances of the GPIO module. */
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#define GPIO_INSTANCE_COUNT (5u)
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/* GPIO - Peripheral instance base addresses */
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/** Peripheral GPIOA base address */
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#define GPIOA_BASE (0x41000000u)
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/** Peripheral GPIOA base pointer */
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#define GPIOA ((GPIO_Type *)GPIOA_BASE)
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/** Peripheral GPIOB base address */
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#define GPIOB_BASE (0x41000040u)
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/** Peripheral GPIOB base pointer */
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#define GPIOB ((GPIO_Type *)GPIOB_BASE)
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/** Peripheral GPIOC base address */
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#define GPIOC_BASE (0x41000080u)
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/** Peripheral GPIOC base pointer */
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#define GPIOC ((GPIO_Type *)GPIOC_BASE)
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/** Peripheral GPIOD base address */
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#define GPIOD_BASE (0x410000c0u)
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/** Peripheral GPIOD base pointer */
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#define GPIOD ((GPIO_Type *)GPIOD_BASE)
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/** Peripheral GPIOE base address */
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#define GPIOE_BASE (0x41000100u)
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/** Peripheral GPIOE base pointer */
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#define GPIOE ((GPIO_Type *)GPIOE_BASE)
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/** Array initializer of GPIO peripheral base addresses */
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#define GPIO_BASE_ADDRS {GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE}
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/** Array initializer of GPIO peripheral base pointers */
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#define GPIO_BASE_PTRS {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}
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// need fill by yourself
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///** Number of interrupt vector arrays for the GPIO module. */
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//#define GPIO_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the GPIO module. */
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//#define GPIO_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the GPIO peripheral type */
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//#define GPIO_IRQS {GPIOA_IRQn, GPIOB_IRQn, GPIOC_IRQn, GPIOD_IRQn, GPIOE_IRQn}
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/* ----------------------------------------------------------------------------
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-- GPIO Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup GPIO_Register_Masks GPIO Register Masks
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* @{
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*/
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/* PDOR Bit Fields */
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#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
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#define GPIO_PDOR_PDO_SHIFT 0u
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#define GPIO_PDOR_PDO_WIDTH 32u
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#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
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/* PDOR Reg Mask */
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#define GPIO_PDOR_MASK 0xFFFFFFFFu
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/* PSOR Bit Fields */
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#define GPIO_PSOR_PSO_MASK 0xFFFFFFFFu
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#define GPIO_PSOR_PSO_SHIFT 0u
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#define GPIO_PSOR_PSO_WIDTH 32u
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#define GPIO_PSOR_PSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PSO_SHIFT))&GPIO_PSOR_PSO_MASK)
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/* PSOR Reg Mask */
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#define GPIO_PSOR_MASK 0xFFFFFFFFu
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/* PCOR Bit Fields */
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#define GPIO_PCOR_PCO_MASK 0xFFFFFFFFu
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#define GPIO_PCOR_PCO_SHIFT 0u
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#define GPIO_PCOR_PCO_WIDTH 32u
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#define GPIO_PCOR_PCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PCO_SHIFT))&GPIO_PCOR_PCO_MASK)
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/* PCOR Reg Mask */
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#define GPIO_PCOR_MASK 0xFFFFFFFFu
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/* PTOR Bit Fields */
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#define GPIO_PTOR_PTO_MASK 0xFFFFFFFFu
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#define GPIO_PTOR_PTO_SHIFT 0u
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#define GPIO_PTOR_PTO_WIDTH 32u
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#define GPIO_PTOR_PTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTO_SHIFT))&GPIO_PTOR_PTO_MASK)
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/* PTOR Reg Mask */
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#define GPIO_PTOR_MASK 0xFFFFFFFFu
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/* PDIR Bit Fields */
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#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
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#define GPIO_PDIR_PDI_SHIFT 0u
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#define GPIO_PDIR_PDI_WIDTH 32u
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#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
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/* PDIR Reg Mask */
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#define GPIO_PDIR_MASK 0xFFFFFFFFu
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/* PDDR Bit Fields */
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#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
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#define GPIO_PDDR_PDD_SHIFT 0u
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#define GPIO_PDDR_PDD_WIDTH 32u
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#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
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/* PDDR Reg Mask */
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#define GPIO_PDDR_MASK 0xFFFFFFFFu
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/* PIDR Bit Fields */
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#define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
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#define GPIO_PIDR_PID_SHIFT 0u
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#define GPIO_PIDR_PID_WIDTH 32u
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#define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
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/* PIDR Reg Mask */
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#define GPIO_PIDR_MASK 0xFFFFFFFFu
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/*!
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* @}
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*/ /* end of group GPIO_Register_Masks */
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/*!
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* @}
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*/ /* end of group GPIO_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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