457 lines
11 KiB
C
457 lines
11 KiB
C
#ifndef _FC7240_FCPIT_NU_Tztufn30_REGS_H_
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#define _FC7240_FCPIT_NU_Tztufn30_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- FCPIT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup FCPIT_Peripheral_Access_Layer FCPIT Peripheral Access Layer
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* @{
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*/
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/** FCPIT - Size of Registers Arrays */
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#define FCPIT_CHANNEL_NUM 4u
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/** FCPIT - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[8];
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__IO uint32_t MCR ; /* Module Control Register, offset: 0x8 */
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__IO uint32_t MSR ; /* Module Status Register, offset: 0xC */
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__IO uint32_t MIER ; /* Module Interrupt Enable Register, offset: 0x10 */
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__IO uint32_t SETTEN ; /* Set Timer Enable Register, offset: 0x14 */
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__IO uint32_t CLRTEN ; /* Clear Timer Enable Register, offset: 0x18 */
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uint8_t RESERVED_1[4];
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struct
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{
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__IO uint32_t TVAL ; /* Timer Value Register, offset: 0x20 */
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__I uint32_t CVAL ; /* Current Timer Value Register, offset: 0x24 */
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__IO uint32_t TCTRL ; /* Timer Control Register, offset: 0x28 */
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uint8_t RESERVED_2[4];
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}CONTROLS[FCPIT_CHANNEL_NUM];
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} FCPIT_Type, *FCPIT_MemMapPtr;
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/** Number of instances of the FCPIT module. */
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#define FCPIT_INSTANCE_COUNT (1u)
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#define MAX_FCPIT_CHANNEL_NUM (4u)
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/* FCPIT - Peripheral instance base addresses */
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/** Peripheral FCPIT base address */
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#define FCPIT_BASE (0x4002e000u)
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/** Peripheral FCPIT base pointer */
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#define FCPIT ((FCPIT_Type *)FCPIT_BASE)
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/** Array initializer of FCPIT peripheral base addresses */
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#define FCPIT_BASE_ADDRS {FCPIT_BASE}
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/** Array initializer of FCPIT peripheral base pointers */
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#define FCPIT_BASE_PTRS {FCPIT}
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// need fill by yourself
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///** Number of interrupt vector arrays for the FCPIT module. */
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//#define FCPIT_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the FCPIT module. */
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//#define FCPIT_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the FCPIT peripheral type */
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//#define FCPIT_IRQS {FCPIT_IRQn}
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/* ----------------------------------------------------------------------------
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-- FCPIT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup FCPIT_Register_Masks FCPIT Register Masks
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* @{
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*/
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/* MCR Bit Fields */
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#define FCPIT_MCR_DBG_EN_MASK 0x8u
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#define FCPIT_MCR_DBG_EN_SHIFT 3u
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#define FCPIT_MCR_DBG_EN_WIDTH 1u
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#define FCPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_DBG_EN_SHIFT))&FCPIT_MCR_DBG_EN_MASK)
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#define FCPIT_MCR_LPM_EN_MASK 0x4u
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#define FCPIT_MCR_LPM_EN_SHIFT 2u
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#define FCPIT_MCR_LPM_EN_WIDTH 1u
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#define FCPIT_MCR_LPM_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_LPM_EN_SHIFT))&FCPIT_MCR_LPM_EN_MASK)
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#define FCPIT_MCR_SW_RST_MASK 0x2u
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#define FCPIT_MCR_SW_RST_SHIFT 1u
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#define FCPIT_MCR_SW_RST_WIDTH 1u
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#define FCPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_SW_RST_SHIFT))&FCPIT_MCR_SW_RST_MASK)
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#define FCPIT_MCR_M_CEN_MASK 0x1u
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#define FCPIT_MCR_M_CEN_SHIFT 0u
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#define FCPIT_MCR_M_CEN_WIDTH 1u
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#define FCPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_M_CEN_SHIFT))&FCPIT_MCR_M_CEN_MASK)
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/* MCR Reg Mask */
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#define FCPIT_MCR_MASK 0x0000000Fu
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/* MSR Bit Fields */
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#define FCPIT_MSR_TIF3_MASK 0x8u
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#define FCPIT_MSR_TIF3_SHIFT 3u
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#define FCPIT_MSR_TIF3_WIDTH 1u
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#define FCPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF3_SHIFT))&FCPIT_MSR_TIF3_MASK)
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#define FCPIT_MSR_TIF2_MASK 0x4u
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#define FCPIT_MSR_TIF2_SHIFT 2u
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#define FCPIT_MSR_TIF2_WIDTH 1u
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#define FCPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF2_SHIFT))&FCPIT_MSR_TIF2_MASK)
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#define FCPIT_MSR_TIF1_MASK 0x2u
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#define FCPIT_MSR_TIF1_SHIFT 1u
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#define FCPIT_MSR_TIF1_WIDTH 1u
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#define FCPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF1_SHIFT))&FCPIT_MSR_TIF1_MASK)
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#define FCPIT_MSR_TIF0_MASK 0x1u
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#define FCPIT_MSR_TIF0_SHIFT 0u
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#define FCPIT_MSR_TIF0_WIDTH 1u
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#define FCPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF0_SHIFT))&FCPIT_MSR_TIF0_MASK)
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/* MSR Reg Mask */
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#define FCPIT_MSR_MASK 0x0000000Fu
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/* MIER Bit Fields */
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#define FCPIT_MIER_TIE3_MASK 0x8u
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#define FCPIT_MIER_TIE3_SHIFT 3u
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#define FCPIT_MIER_TIE3_WIDTH 1u
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#define FCPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE3_SHIFT))&FCPIT_MIER_TIE3_MASK)
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#define FCPIT_MIER_TIE2_MASK 0x4u
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#define FCPIT_MIER_TIE2_SHIFT 2u
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#define FCPIT_MIER_TIE2_WIDTH 1u
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#define FCPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE2_SHIFT))&FCPIT_MIER_TIE2_MASK)
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#define FCPIT_MIER_TIE1_MASK 0x2u
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#define FCPIT_MIER_TIE1_SHIFT 1u
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#define FCPIT_MIER_TIE1_WIDTH 1u
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#define FCPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE1_SHIFT))&FCPIT_MIER_TIE1_MASK)
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#define FCPIT_MIER_TIE0_MASK 0x1u
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#define FCPIT_MIER_TIE0_SHIFT 0u
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#define FCPIT_MIER_TIE0_WIDTH 1u
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#define FCPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE0_SHIFT))&FCPIT_MIER_TIE0_MASK)
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/* MIER Reg Mask */
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#define FCPIT_MIER_MASK 0x0000000Fu
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/* SETTEN Bit Fields */
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#define FCPIT_SETTEN_SET_T_EN_3_MASK 0x8u
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#define FCPIT_SETTEN_SET_T_EN_3_SHIFT 3u
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#define FCPIT_SETTEN_SET_T_EN_3_WIDTH 1u
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#define FCPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_3_SHIFT))&FCPIT_SETTEN_SET_T_EN_3_MASK)
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#define FCPIT_SETTEN_SET_T_EN_2_MASK 0x4u
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#define FCPIT_SETTEN_SET_T_EN_2_SHIFT 2u
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#define FCPIT_SETTEN_SET_T_EN_2_WIDTH 1u
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#define FCPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_2_SHIFT))&FCPIT_SETTEN_SET_T_EN_2_MASK)
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#define FCPIT_SETTEN_SET_T_EN_1_MASK 0x2u
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#define FCPIT_SETTEN_SET_T_EN_1_SHIFT 1u
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#define FCPIT_SETTEN_SET_T_EN_1_WIDTH 1u
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#define FCPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_1_SHIFT))&FCPIT_SETTEN_SET_T_EN_1_MASK)
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#define FCPIT_SETTEN_SET_T_EN_0_MASK 0x1u
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#define FCPIT_SETTEN_SET_T_EN_0_SHIFT 0u
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#define FCPIT_SETTEN_SET_T_EN_0_WIDTH 1u
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#define FCPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_0_SHIFT))&FCPIT_SETTEN_SET_T_EN_0_MASK)
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/* SETTEN Reg Mask */
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#define FCPIT_SETTEN_MASK 0x0000000Fu
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/* CLRTEN Bit Fields */
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#define FCPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
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#define FCPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
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#define FCPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
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#define FCPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_3_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_3_MASK)
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#define FCPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
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#define FCPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
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#define FCPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
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#define FCPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_2_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_2_MASK)
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#define FCPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
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#define FCPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
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#define FCPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
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#define FCPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_1_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_1_MASK)
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#define FCPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
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#define FCPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
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#define FCPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
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#define FCPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_0_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_0_MASK)
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/* CLRTEN Reg Mask */
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#define FCPIT_CLRTEN_MASK 0x0000000Fu
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/* TVAL Bit Fields */
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#define FCPIT_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
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#define FCPIT_TVAL_TMR_VAL_SHIFT 0u
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#define FCPIT_TVAL_TMR_VAL_WIDTH 32u
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#define FCPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TVAL_TMR_VAL_SHIFT))&FCPIT_TVAL_TMR_VAL_MASK)
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/* TVAL0 Reg Mask */
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#define FCPIT_TVAL_MASK 0xFFFFFFFFu
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/* CVAL Bit Fields */
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#define FCPIT_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
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#define FCPIT_CVAL_TMR_CUR_VAL_SHIFT 0u
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#define FCPIT_CVAL_TMR_CUR_VAL_WIDTH 32u
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#define FCPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CVAL_TMR_CUR_VAL_SHIFT))&FCPIT_CVAL_TMR_CUR_VAL_MASK)
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/* CVAL0 Reg Mask */
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#define FCPIT_CVAL_MASK 0xFFFFFFFFu
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/* TCTRL Bit Fields */
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#define FCPIT_TCTRL_TRG_SEL_MASK 0xF000000u
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#define FCPIT_TCTRL_TRG_SEL_SHIFT 24u
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#define FCPIT_TCTRL_TRG_SEL_WIDTH 4u
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#define FCPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SEL_SHIFT))&FCPIT_TCTRL_TRG_SEL_MASK)
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#define FCPIT_TCTRL_TRG_SRC_MASK 0x800000u
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#define FCPIT_TCTRL_TRG_SRC_SHIFT 23u
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#define FCPIT_TCTRL_TRG_SRC_WIDTH 1u
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#define FCPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SRC_SHIFT))&FCPIT_TCTRL_TRG_SRC_MASK)
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#define FCPIT_TCTRL_TROT_MASK 0x40000u
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#define FCPIT_TCTRL_TROT_SHIFT 18u
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#define FCPIT_TCTRL_TROT_WIDTH 1u
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#define FCPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TROT_SHIFT))&FCPIT_TCTRL_TROT_MASK)
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#define FCPIT_TCTRL_TSOI_MASK 0x20000u
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#define FCPIT_TCTRL_TSOI_SHIFT 17u
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#define FCPIT_TCTRL_TSOI_WIDTH 1u
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#define FCPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOI_SHIFT))&FCPIT_TCTRL_TSOI_MASK)
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#define FCPIT_TCTRL_TSOT_MASK 0x10000u
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#define FCPIT_TCTRL_TSOT_SHIFT 16u
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#define FCPIT_TCTRL_TSOT_WIDTH 1u
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#define FCPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOT_SHIFT))&FCPIT_TCTRL_TSOT_MASK)
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#define FCPIT_TCTRL_MODE_MASK 0xCu
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#define FCPIT_TCTRL_MODE_SHIFT 2u
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#define FCPIT_TCTRL_MODE_WIDTH 2u
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#define FCPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_MODE_SHIFT))&FCPIT_TCTRL_MODE_MASK)
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#define FCPIT_TCTRL_CHAIN_MASK 0x2u
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#define FCPIT_TCTRL_CHAIN_SHIFT 1u
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#define FCPIT_TCTRL_CHAIN_WIDTH 1u
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#define FCPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_CHAIN_SHIFT))&FCPIT_TCTRL_CHAIN_MASK)
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#define FCPIT_TCTRL_T_EN_MASK 0x1u
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#define FCPIT_TCTRL_T_EN_SHIFT 0u
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#define FCPIT_TCTRL_T_EN_WIDTH 1u
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#define FCPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_T_EN_SHIFT))&FCPIT_TCTRL_T_EN_MASK)
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/* TCTRL0 Reg Mask */
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#define FCPIT_TCTRL_MASK 0x0F87000Fu
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/*!
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* @}
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*/ /* end of group FCPIT_Register_Masks */
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/*!
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* @}
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*/ /* end of group FCPIT_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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