380 lines
9.7 KiB
C
380 lines
9.7 KiB
C
#ifndef _FC7240_EIM_NU_Tztufn26_REGS_H_
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#define _FC7240_EIM_NU_Tztufn26_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- EIM Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
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* @{
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*/
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/** EIM - Size of Registers Arrays */
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/** EIM - Register Layout Typedef */
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#define EIM_CTRL_REG_COUNT 83
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#define EIM_BUS_REG_COUNT 4
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typedef struct {
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__IO uint32_t CR ; /* Configuration Register, offset: 0x0 */
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uint8_t RESERVED_0[12];
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__IO uint32_t CTRL_REG[EIM_CTRL_REG_COUNT] ; /* Channel N Control Register, offset: 0x10 */
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uint8_t RESERVED_1[676];
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__IO uint32_t CPU0_LOCKSTEP ; /* CPU0 LOCKSTEP Error Injection Register, offset: 0x400 */
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uint8_t RESERVED_2[4];
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__IO uint32_t DMA0_LOCKSTEP ; /* DMA0 LOCKSTEP Error Injection Register, offset: 0x408 */
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uint8_t RESERVED_3[1012];
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__IO uint32_t BUS_REG[EIM_BUS_REG_COUNT] ; /* Bus Register, offset: 0x800 */
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} EIM_Type, *EIM_MemMapPtr;
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/** Number of instances of the EIM module. */
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#define EIM_INSTANCE_COUNT (1u)
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/* EIM - Peripheral instance base addresses */
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/** Peripheral EIM base address */
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#define EIM_BASE (0x40019000u)
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/** Peripheral EIM base pointer */
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#define EIM ((EIM_Type *)EIM_BASE)
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/** Array initializer of EIM peripheral base addresses */
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#define EIM_BASE_ADDRS {EIM_BASE}
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/** Array initializer of EIM peripheral base pointers */
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#define EIM_BASE_PTRS {EIM}
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// need fill by yourself
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///** Number of interrupt vector arrays for the EIM module. */
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//#define EIM_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the EIM module. */
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//#define EIM_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the EIM peripheral type */
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//#define EIM_IRQS {EIM_IRQn}
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/* ----------------------------------------------------------------------------
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-- EIM Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup EIM_Register_Masks EIM Register Masks
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* @{
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*/
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/* CR Bit Fields */
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#define EIM_CR_GEIEN_MASK 0x1u
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#define EIM_CR_GEIEN_SHIFT 0u
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#define EIM_CR_GEIEN_WIDTH 1u
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#define EIM_CR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CR_GEIEN_SHIFT))&EIM_CR_GEIEN_MASK)
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/* CR Reg Mask */
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#define EIM_CR_MASK 0x00000001u
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/* CTRL_REG Bit Fields */
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#define EIM_CTRL_REG_DWP_LOCK_MASK 0x80000000u
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#define EIM_CTRL_REG_DWP_LOCK_SHIFT 31u
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#define EIM_CTRL_REG_DWP_LOCK_WIDTH 1u
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#define EIM_CTRL_REG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_LOCK_SHIFT))&EIM_CTRL_REG_DWP_LOCK_MASK)
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#define EIM_CTRL_REG_DWP_MASK 0x70000000u
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#define EIM_CTRL_REG_DWP_SHIFT 28u
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#define EIM_CTRL_REG_DWP_WIDTH 3u
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#define EIM_CTRL_REG_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_SHIFT))&EIM_CTRL_REG_DWP_MASK)
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#define EIM_CTRL_REG_BUS_SEL_MASK 0x30u
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#define EIM_CTRL_REG_BUS_SEL_SHIFT 4u
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#define EIM_CTRL_REG_BUS_SEL_WIDTH 2u
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#define EIM_CTRL_REG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_BUS_SEL_SHIFT))&EIM_CTRL_REG_BUS_SEL_MASK)
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#define EIM_CTRL_REG_ATTREIE_MASK 0x8u
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#define EIM_CTRL_REG_ATTREIE_SHIFT 3u
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#define EIM_CTRL_REG_ATTREIE_WIDTH 1u
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#define EIM_CTRL_REG_ATTREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ATTREIE_SHIFT))&EIM_CTRL_REG_ATTREIE_MASK)
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#define EIM_CTRL_REG_ADDREIE_MASK 0x4u
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#define EIM_CTRL_REG_ADDREIE_SHIFT 2u
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#define EIM_CTRL_REG_ADDREIE_WIDTH 1u
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#define EIM_CTRL_REG_ADDREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ADDREIE_SHIFT))&EIM_CTRL_REG_ADDREIE_MASK)
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#define EIM_CTRL_REG_DATA1EIE_MASK 0x2u
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#define EIM_CTRL_REG_DATA1EIE_SHIFT 1u
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#define EIM_CTRL_REG_DATA1EIE_WIDTH 1u
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#define EIM_CTRL_REG_DATA1EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA1EIE_SHIFT))&EIM_CTRL_REG_DATA1EIE_MASK)
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#define EIM_CTRL_REG_DATA0EIE_MASK 0x1u
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#define EIM_CTRL_REG_DATA0EIE_SHIFT 0u
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#define EIM_CTRL_REG_DATA0EIE_WIDTH 1u
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#define EIM_CTRL_REG_DATA0EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA0EIE_SHIFT))&EIM_CTRL_REG_DATA0EIE_MASK)
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/* CTRL_REG0 Reg Mask */
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#define EIM_CTRL_REG_MASK 0xF000003Fu
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/* CPU0_LOCKSTEP Bit Fields */
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#define EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
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#define EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT 31u
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#define EIM_CPU0_LOCKSTEP_DWP_LOCK_WIDTH 1u
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#define EIM_CPU0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK)
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#define EIM_CPU0_LOCKSTEP_DWP_MASK 0x70000000u
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#define EIM_CPU0_LOCKSTEP_DWP_SHIFT 28u
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#define EIM_CPU0_LOCKSTEP_DWP_WIDTH 3u
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#define EIM_CPU0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_MASK)
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
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#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
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/* CPU0_LOCKSTEP Reg Mask */
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#define EIM_CPU0_LOCKSTEP_MASK 0xF000000Fu
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/* DMA0_LOCKSTEP Bit Fields */
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#define EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
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#define EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT 31u
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#define EIM_DMA0_LOCKSTEP_DWP_LOCK_WIDTH 1u
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#define EIM_DMA0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK)
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#define EIM_DMA0_LOCKSTEP_DWP_MASK 0x70000000u
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#define EIM_DMA0_LOCKSTEP_DWP_SHIFT 28u
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#define EIM_DMA0_LOCKSTEP_DWP_WIDTH 3u
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#define EIM_DMA0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_MASK)
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
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#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
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/* DMA0_LOCKSTEP Reg Mask */
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#define EIM_DMA0_LOCKSTEP_MASK 0xF000000Fu
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/* BUS_REG Bit Fields */
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#define EIM_BUS_REG_ATTR_MASK 0x1F000000u
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#define EIM_BUS_REG_ATTR_SHIFT 24u
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#define EIM_BUS_REG_ATTR_WIDTH 5u
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#define EIM_BUS_REG_ATTR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ATTR_SHIFT))&EIM_BUS_REG_ATTR_MASK)
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#define EIM_BUS_REG_ADDR_MASK 0x1F0000u
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#define EIM_BUS_REG_ADDR_SHIFT 16u
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#define EIM_BUS_REG_ADDR_WIDTH 5u
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#define EIM_BUS_REG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ADDR_SHIFT))&EIM_BUS_REG_ADDR_MASK)
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#define EIM_BUS_REG_DATA1_MASK 0x7F00u
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#define EIM_BUS_REG_DATA1_SHIFT 8u
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#define EIM_BUS_REG_DATA1_WIDTH 7u
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#define EIM_BUS_REG_DATA1(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA1_SHIFT))&EIM_BUS_REG_DATA1_MASK)
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#define EIM_BUS_REG_DATA0_MASK 0x7Fu
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#define EIM_BUS_REG_DATA0_SHIFT 0u
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#define EIM_BUS_REG_DATA0_WIDTH 7u
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#define EIM_BUS_REG_DATA0(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA0_SHIFT))&EIM_BUS_REG_DATA0_MASK)
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/* BUS_REG0 Reg Mask */
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#define EIM_BUS_REG_MASK 0x1F1F7F7Fu
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/*!
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* @}
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*/ /* end of group EIM_Register_Masks */
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/*!
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* @}
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*/ /* end of group EIM_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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