175 lines
3.2 KiB
C
175 lines
3.2 KiB
C
#ifndef _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
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#define _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- DMAMUX Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
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* @{
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*/
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/** DMAMUX - Size of Registers Arrays */
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/** DMAMUX - Register Layout Typedef */
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#define DMAMUX_CHCFG_COUNT 16
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#define DMAMUX_CHTRG_TRG_COUNT 4
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typedef struct {
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__IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT] ; /* Channel N Configuration Register, offset: 0x0 */
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uint8_t RESERVED_0[16];
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__IO uint8_t CHTRG ; /* Channel N Trigger Register, offset: 0x20 */
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} DMAMUX_Type, *DMAMUX_MemMapPtr;
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/** Number of instances of the DMAMUX module. */
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#define DMAMUX_INSTANCE_COUNT (1u)
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/* DMAMUX - Peripheral instance base addresses */
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/** Peripheral DMAMUX base address */
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#define DMAMUX_BASE (0x4000a000u)
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/** Peripheral DMAMUX base pointer */
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#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
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/** Array initializer of DMAMUX peripheral base addresses */
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#define DMAMUX_BASE_ADDRS {DMAMUX_BASE}
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/** Array initializer of DMAMUX peripheral base pointers */
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#define DMAMUX_BASE_PTRS {DMAMUX}
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// need fill by yourself
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///** Number of interrupt vector arrays for the DMAMUX module. */
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//#define DMAMUX_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the DMAMUX module. */
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//#define DMAMUX_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the DMAMUX peripheral type */
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//#define DMAMUX_IRQS {DMAMUX_IRQn}
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/* ----------------------------------------------------------------------------
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-- DMAMUX Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
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* @{
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*/
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/* CHCFG Bit Fields */
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#define DMAMUX_CHCFG_ENBL_MASK 0x80u
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#define DMAMUX_CHCFG_ENBL_SHIFT 7u
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#define DMAMUX_CHCFG_ENBL_WIDTH 1u
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#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
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#define DMAMUX_CHCFG_SOURCE_MASK 0x7Fu
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#define DMAMUX_CHCFG_SOURCE_SHIFT 0u
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#define DMAMUX_CHCFG_SOURCE_WIDTH 7u
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#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
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/* CHCFG Reg Mask */
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#define DMAMUX_CHCFG_MASK 0xFFu
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/* CHTRG Bit Fields */
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#define DMAMUX_CHTRG_TRIG_MASK 0x1u
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#define DMAMUX_CHTRG_TRIG_SHIFT 0u
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#define DMAMUX_CHTRG_TRIG_WIDTH 1u
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#define DMAMUX_CHTRG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHTRG_TRIG_SHIFT))&DMAMUX_CHTRG_TRIG_MASK)
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/* CHTRG Reg Mask */
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#define DMAMUX_CHTRG_MASK 0x0Fu
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/*!
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* @}
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*/ /* end of group DMAMUX_Register_Masks */
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/*!
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* @}
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*/ /* end of group DMAMUX_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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