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Device_Flagchip_FC7240/fc/fc7240_csc0_regs.h

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#ifndef _FC7240_CSC0_NU_Tztufn51_REGS_H_
#define _FC7240_CSC0_NU_Tztufn51_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- CSC0 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSC0_Peripheral_Access_Layer CSC0 Peripheral Access Layer
* @{
*/
/** CSC0 - Size of Registers Arrays */
/** CSC0 - Register Layout Typedef */
typedef struct {
__IO uint32_t STOP_MODER0 ; /* STOP Mode Control Register 0, offset: 0x0 */
__IO uint32_t STOP_REQR0 ; /* STOP Request Register 0, offset: 0x4 */
__I uint32_t STOP_ACKR0 ; /* STOP Acknowledge Register 0, offset: 0x8 */
__IO uint32_t STOP_MODER1 ; /* STOP Mode Control Register 1, offset: 0xC */
__IO uint32_t STOP_REQR1 ; /* STOP Request Register 1, offset: 0x10 */
__I uint32_t STOP_ACKR1 ; /* STOP Acknowledge Register 1, offset: 0x14 */
__IO uint32_t STOP_MODER2 ; /* STOP Mode Control Register 2, offset: 0x18 */
__IO uint32_t STOP_REQR2 ; /* STOP Request Register 2, offset: 0x1C */
__I uint32_t STOP_ACKR2 ; /* STOP Acknowledge Register 2, offset: 0x20 */
__IO uint32_t CCM0_CFG ; /* CCM0 Configuration Register, offset: 0x24 */
__I uint32_t CCM0_STATUS ; /* CCM0 Status Register, offset: 0x28 */
__IO uint32_t SCG_MAM_STALL ; /* SCG MAM Stall Request Register, offset: 0x2C */
__IO uint32_t CPU0_INT ; /* CPU0 Software Interrupt Register, offset: 0x30 */
uint8_t RESERVED_0[12];
__IO uint32_t CLKOUT_CTRL ; /* Clkout Control Register, offset: 0x40 */
__IO uint32_t AONCLKSR ; /* AON Clock Select Register, offset: 0x44 */
__IO uint32_t PCU_CTRL ; /* PCU Control Register, offset: 0x48 */
uint8_t RESERVED_1[4];
__IO uint32_t SMU_CTRL0 ; /* FCSMU Control Register 0, offset: 0x50 */
__IO uint32_t SMU_CTRL1 ; /* FCSMU Control Register 1, offset: 0x54 */
uint8_t RESERVED_2[8];
__IO uint32_t SMU_CTRL4 ; /* FCSMU Control Register 4, offset: 0x60 */
__IO uint32_t CMU_CTRL ; /* CMU Control Register, offset: 0x64 */
__IO uint32_t SMU_CTRL5 ; /* FCSMU Control Register 5, offset: 0x68 */
uint8_t RESERVED_3[4];
__IO uint32_t LP_WAKEUP ; /* Low Power Wakeup Register, offset: 0x70 */
} CSC0_Type, *CSC0_MemMapPtr;
/** Number of instances of the CSC0 module. */
#define CSC0_INSTANCE_COUNT (1u)
/* CSC0 - Peripheral instance base addresses */
/** Peripheral CSC0 base address */
#define CSC0_BASE (0x40079000u)
/** Peripheral CSC0 base pointer */
#define CSC0 ((CSC0_Type *)CSC0_BASE)
/** Array initializer of CSC0 peripheral base addresses */
#define CSC0_BASE_ADDRS {CSC0_BASE}
/** Array initializer of CSC0 peripheral base pointers */
#define CSC0_BASE_PTRS {CSC0}
// need fill by yourself
///** Number of interrupt vector arrays for the CSC0 module. */
//#define CSC0_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the CSC0 module. */
//#define CSC0_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the CSC0 peripheral type */
//#define CSC0_IRQS {CSC0_IRQn}
/* ----------------------------------------------------------------------------
-- CSC0 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSC0_Register_Masks CSC0 Register Masks
* @{
*/
/* STOP_MODER0 Bit Fields */
#define CSC0_STOP_MODER0_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER0_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER0_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER0_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WPB_LOCK_SHIFT))&CSC0_STOP_MODER0_WPB_LOCK_MASK)
#define CSC0_STOP_MODER0_WPB_MASK 0x70000000u
#define CSC0_STOP_MODER0_WPB_SHIFT 28u
#define CSC0_STOP_MODER0_WPB_WIDTH 3u
#define CSC0_STOP_MODER0_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WPB_SHIFT))&CSC0_STOP_MODER0_WPB_MASK)
#define CSC0_STOP_MODER0_FLEXCAN1_MASK 0x400000u
#define CSC0_STOP_MODER0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_MODER0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN1_SHIFT))&CSC0_STOP_MODER0_FLEXCAN1_MASK)
#define CSC0_STOP_MODER0_FLEXCAN0_MASK 0x200000u
#define CSC0_STOP_MODER0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_MODER0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_MODER0_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FLEXCAN0_SHIFT))&CSC0_STOP_MODER0_FLEXCAN0_MASK)
#define CSC0_STOP_MODER0_FREQM_MASK 0x100000u
#define CSC0_STOP_MODER0_FREQM_SHIFT 20u
#define CSC0_STOP_MODER0_FREQM_WIDTH 1u
#define CSC0_STOP_MODER0_FREQM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FREQM_SHIFT))&CSC0_STOP_MODER0_FREQM_MASK)
#define CSC0_STOP_MODER0_FCUART3_MASK 0x10000u
#define CSC0_STOP_MODER0_FCUART3_SHIFT 16u
#define CSC0_STOP_MODER0_FCUART3_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART3_SHIFT))&CSC0_STOP_MODER0_FCUART3_MASK)
#define CSC0_STOP_MODER0_FCUART2_MASK 0x8000u
#define CSC0_STOP_MODER0_FCUART2_SHIFT 15u
#define CSC0_STOP_MODER0_FCUART2_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART2_SHIFT))&CSC0_STOP_MODER0_FCUART2_MASK)
#define CSC0_STOP_MODER0_FCUART1_MASK 0x4000u
#define CSC0_STOP_MODER0_FCUART1_SHIFT 14u
#define CSC0_STOP_MODER0_FCUART1_WIDTH 1u
#define CSC0_STOP_MODER0_FCUART1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCUART1_SHIFT))&CSC0_STOP_MODER0_FCUART1_MASK)
#define CSC0_STOP_MODER0_FCSPI2_MASK 0x1000u
#define CSC0_STOP_MODER0_FCSPI2_SHIFT 12u
#define CSC0_STOP_MODER0_FCSPI2_WIDTH 1u
#define CSC0_STOP_MODER0_FCSPI2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCSPI2_SHIFT))&CSC0_STOP_MODER0_FCSPI2_MASK)
#define CSC0_STOP_MODER0_FCSPI1_MASK 0x800u
#define CSC0_STOP_MODER0_FCSPI1_SHIFT 11u
#define CSC0_STOP_MODER0_FCSPI1_WIDTH 1u
#define CSC0_STOP_MODER0_FCSPI1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_FCSPI1_SHIFT))&CSC0_STOP_MODER0_FCSPI1_MASK)
#define CSC0_STOP_MODER0_SENT0_MASK 0x400u
#define CSC0_STOP_MODER0_SENT0_SHIFT 10u
#define CSC0_STOP_MODER0_SENT0_WIDTH 1u
#define CSC0_STOP_MODER0_SENT0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_SENT0_SHIFT))&CSC0_STOP_MODER0_SENT0_MASK)
#define CSC0_STOP_MODER0_TMU_MASK 0x200u
#define CSC0_STOP_MODER0_TMU_SHIFT 9u
#define CSC0_STOP_MODER0_TMU_WIDTH 1u
#define CSC0_STOP_MODER0_TMU(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_TMU_SHIFT))&CSC0_STOP_MODER0_TMU_MASK)
#define CSC0_STOP_MODER0_ADC1_MASK 0x80u
#define CSC0_STOP_MODER0_ADC1_SHIFT 7u
#define CSC0_STOP_MODER0_ADC1_WIDTH 1u
#define CSC0_STOP_MODER0_ADC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC1_SHIFT))&CSC0_STOP_MODER0_ADC1_MASK)
#define CSC0_STOP_MODER0_ADC0_MASK 0x40u
#define CSC0_STOP_MODER0_ADC0_SHIFT 6u
#define CSC0_STOP_MODER0_ADC0_WIDTH 1u
#define CSC0_STOP_MODER0_ADC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ADC0_SHIFT))&CSC0_STOP_MODER0_ADC0_MASK)
#define CSC0_STOP_MODER0_CMU4_MASK 0x20u
#define CSC0_STOP_MODER0_CMU4_SHIFT 5u
#define CSC0_STOP_MODER0_CMU4_WIDTH 1u
#define CSC0_STOP_MODER0_CMU4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_CMU4_SHIFT))&CSC0_STOP_MODER0_CMU4_MASK)
#define CSC0_STOP_MODER0_WDOG0_MASK 0x10u
#define CSC0_STOP_MODER0_WDOG0_SHIFT 4u
#define CSC0_STOP_MODER0_WDOG0_WIDTH 1u
#define CSC0_STOP_MODER0_WDOG0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_WDOG0_SHIFT))&CSC0_STOP_MODER0_WDOG0_MASK)
#define CSC0_STOP_MODER0_ISM0_MASK 0x2u
#define CSC0_STOP_MODER0_ISM0_SHIFT 1u
#define CSC0_STOP_MODER0_ISM0_WIDTH 1u
#define CSC0_STOP_MODER0_ISM0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_ISM0_SHIFT))&CSC0_STOP_MODER0_ISM0_MASK)
#define CSC0_STOP_MODER0_DMA0_MASK 0x1u
#define CSC0_STOP_MODER0_DMA0_SHIFT 0u
#define CSC0_STOP_MODER0_DMA0_WIDTH 1u
#define CSC0_STOP_MODER0_DMA0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER0_DMA0_SHIFT))&CSC0_STOP_MODER0_DMA0_MASK)
/* STOP_MODER0 Reg Mask */
#define CSC0_STOP_MODER0_MASK 0xF071DEF3u
/* STOP_REQR0 Bit Fields */
#define CSC0_STOP_REQR0_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_REQR0_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR0_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR0_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WPB_LOCK_SHIFT))&CSC0_STOP_REQR0_WPB_LOCK_MASK)
#define CSC0_STOP_REQR0_WPB_MASK 0x70000000u
#define CSC0_STOP_REQR0_WPB_SHIFT 28u
#define CSC0_STOP_REQR0_WPB_WIDTH 3u
#define CSC0_STOP_REQR0_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WPB_SHIFT))&CSC0_STOP_REQR0_WPB_MASK)
#define CSC0_STOP_REQR0_FLEXCAN1_MASK 0x400000u
#define CSC0_STOP_REQR0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_REQR0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN1_SHIFT))&CSC0_STOP_REQR0_FLEXCAN1_MASK)
#define CSC0_STOP_REQR0_FLEXCAN0_MASK 0x200000u
#define CSC0_STOP_REQR0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_REQR0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_REQR0_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FLEXCAN0_SHIFT))&CSC0_STOP_REQR0_FLEXCAN0_MASK)
#define CSC0_STOP_REQR0_FREQM_MASK 0x100000u
#define CSC0_STOP_REQR0_FREQM_SHIFT 20u
#define CSC0_STOP_REQR0_FREQM_WIDTH 1u
#define CSC0_STOP_REQR0_FREQM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FREQM_SHIFT))&CSC0_STOP_REQR0_FREQM_MASK)
#define CSC0_STOP_REQR0_FCUART3_MASK 0x10000u
#define CSC0_STOP_REQR0_FCUART3_SHIFT 16u
#define CSC0_STOP_REQR0_FCUART3_WIDTH 1u
#define CSC0_STOP_REQR0_FCUART3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART3_SHIFT))&CSC0_STOP_REQR0_FCUART3_MASK)
#define CSC0_STOP_REQR0_FCUART2_MASK 0x8000u
#define CSC0_STOP_REQR0_FCUART2_SHIFT 15u
#define CSC0_STOP_REQR0_FCUART2_WIDTH 1u
#define CSC0_STOP_REQR0_FCUART2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART2_SHIFT))&CSC0_STOP_REQR0_FCUART2_MASK)
#define CSC0_STOP_REQR0_FCUART1_MASK 0x4000u
#define CSC0_STOP_REQR0_FCUART1_SHIFT 14u
#define CSC0_STOP_REQR0_FCUART1_WIDTH 1u
#define CSC0_STOP_REQR0_FCUART1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCUART1_SHIFT))&CSC0_STOP_REQR0_FCUART1_MASK)
#define CSC0_STOP_REQR0_FCSPI2_MASK 0x1000u
#define CSC0_STOP_REQR0_FCSPI2_SHIFT 12u
#define CSC0_STOP_REQR0_FCSPI2_WIDTH 1u
#define CSC0_STOP_REQR0_FCSPI2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCSPI2_SHIFT))&CSC0_STOP_REQR0_FCSPI2_MASK)
#define CSC0_STOP_REQR0_FCSPI1_MASK 0x800u
#define CSC0_STOP_REQR0_FCSPI1_SHIFT 11u
#define CSC0_STOP_REQR0_FCSPI1_WIDTH 1u
#define CSC0_STOP_REQR0_FCSPI1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_FCSPI1_SHIFT))&CSC0_STOP_REQR0_FCSPI1_MASK)
#define CSC0_STOP_REQR0_SENT0_MASK 0x400u
#define CSC0_STOP_REQR0_SENT0_SHIFT 10u
#define CSC0_STOP_REQR0_SENT0_WIDTH 1u
#define CSC0_STOP_REQR0_SENT0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_SENT0_SHIFT))&CSC0_STOP_REQR0_SENT0_MASK)
#define CSC0_STOP_REQR0_TMU_MASK 0x200u
#define CSC0_STOP_REQR0_TMU_SHIFT 9u
#define CSC0_STOP_REQR0_TMU_WIDTH 1u
#define CSC0_STOP_REQR0_TMU(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_TMU_SHIFT))&CSC0_STOP_REQR0_TMU_MASK)
#define CSC0_STOP_REQR0_ADC1_MASK 0x80u
#define CSC0_STOP_REQR0_ADC1_SHIFT 7u
#define CSC0_STOP_REQR0_ADC1_WIDTH 1u
#define CSC0_STOP_REQR0_ADC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC1_SHIFT))&CSC0_STOP_REQR0_ADC1_MASK)
#define CSC0_STOP_REQR0_ADC0_MASK 0x40u
#define CSC0_STOP_REQR0_ADC0_SHIFT 6u
#define CSC0_STOP_REQR0_ADC0_WIDTH 1u
#define CSC0_STOP_REQR0_ADC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ADC0_SHIFT))&CSC0_STOP_REQR0_ADC0_MASK)
#define CSC0_STOP_REQR0_CMU4_MASK 0x20u
#define CSC0_STOP_REQR0_CMU4_SHIFT 5u
#define CSC0_STOP_REQR0_CMU4_WIDTH 1u
#define CSC0_STOP_REQR0_CMU4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_CMU4_SHIFT))&CSC0_STOP_REQR0_CMU4_MASK)
#define CSC0_STOP_REQR0_WDOG0_MASK 0x10u
#define CSC0_STOP_REQR0_WDOG0_SHIFT 4u
#define CSC0_STOP_REQR0_WDOG0_WIDTH 1u
#define CSC0_STOP_REQR0_WDOG0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_WDOG0_SHIFT))&CSC0_STOP_REQR0_WDOG0_MASK)
#define CSC0_STOP_REQR0_ISM0_MASK 0x2u
#define CSC0_STOP_REQR0_ISM0_SHIFT 1u
#define CSC0_STOP_REQR0_ISM0_WIDTH 1u
#define CSC0_STOP_REQR0_ISM0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_ISM0_SHIFT))&CSC0_STOP_REQR0_ISM0_MASK)
#define CSC0_STOP_REQR0_DMA0_MASK 0x1u
#define CSC0_STOP_REQR0_DMA0_SHIFT 0u
#define CSC0_STOP_REQR0_DMA0_WIDTH 1u
#define CSC0_STOP_REQR0_DMA0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR0_DMA0_SHIFT))&CSC0_STOP_REQR0_DMA0_MASK)
/* STOP_REQR0 Reg Mask */
#define CSC0_STOP_REQR0_MASK 0xF071DEF3u
/* STOP_ACKR0 Bit Fields */
#define CSC0_STOP_ACKR0_FLEXCAN1_MASK 0x400000u
#define CSC0_STOP_ACKR0_FLEXCAN1_SHIFT 22u
#define CSC0_STOP_ACKR0_FLEXCAN1_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN1_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN1_MASK)
#define CSC0_STOP_ACKR0_FLEXCAN0_MASK 0x200000u
#define CSC0_STOP_ACKR0_FLEXCAN0_SHIFT 21u
#define CSC0_STOP_ACKR0_FLEXCAN0_WIDTH 1u
#define CSC0_STOP_ACKR0_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FLEXCAN0_SHIFT))&CSC0_STOP_ACKR0_FLEXCAN0_MASK)
#define CSC0_STOP_ACKR0_FREQM_MASK 0x100000u
#define CSC0_STOP_ACKR0_FREQM_SHIFT 20u
#define CSC0_STOP_ACKR0_FREQM_WIDTH 1u
#define CSC0_STOP_ACKR0_FREQM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FREQM_SHIFT))&CSC0_STOP_ACKR0_FREQM_MASK)
#define CSC0_STOP_ACKR0_FCUART3_MASK 0x10000u
#define CSC0_STOP_ACKR0_FCUART3_SHIFT 16u
#define CSC0_STOP_ACKR0_FCUART3_WIDTH 1u
#define CSC0_STOP_ACKR0_FCUART3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART3_SHIFT))&CSC0_STOP_ACKR0_FCUART3_MASK)
#define CSC0_STOP_ACKR0_FCUART2_MASK 0x8000u
#define CSC0_STOP_ACKR0_FCUART2_SHIFT 15u
#define CSC0_STOP_ACKR0_FCUART2_WIDTH 1u
#define CSC0_STOP_ACKR0_FCUART2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART2_SHIFT))&CSC0_STOP_ACKR0_FCUART2_MASK)
#define CSC0_STOP_ACKR0_FCUART1_MASK 0x4000u
#define CSC0_STOP_ACKR0_FCUART1_SHIFT 14u
#define CSC0_STOP_ACKR0_FCUART1_WIDTH 1u
#define CSC0_STOP_ACKR0_FCUART1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCUART1_SHIFT))&CSC0_STOP_ACKR0_FCUART1_MASK)
#define CSC0_STOP_ACKR0_FCSPI2_MASK 0x1000u
#define CSC0_STOP_ACKR0_FCSPI2_SHIFT 12u
#define CSC0_STOP_ACKR0_FCSPI2_WIDTH 1u
#define CSC0_STOP_ACKR0_FCSPI2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCSPI2_SHIFT))&CSC0_STOP_ACKR0_FCSPI2_MASK)
#define CSC0_STOP_ACKR0_FCSPI1_MASK 0x800u
#define CSC0_STOP_ACKR0_FCSPI1_SHIFT 11u
#define CSC0_STOP_ACKR0_FCSPI1_WIDTH 1u
#define CSC0_STOP_ACKR0_FCSPI1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_FCSPI1_SHIFT))&CSC0_STOP_ACKR0_FCSPI1_MASK)
#define CSC0_STOP_ACKR0_SENT0_MASK 0x400u
#define CSC0_STOP_ACKR0_SENT0_SHIFT 10u
#define CSC0_STOP_ACKR0_SENT0_WIDTH 1u
#define CSC0_STOP_ACKR0_SENT0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_SENT0_SHIFT))&CSC0_STOP_ACKR0_SENT0_MASK)
#define CSC0_STOP_ACKR0_TMU_MASK 0x200u
#define CSC0_STOP_ACKR0_TMU_SHIFT 9u
#define CSC0_STOP_ACKR0_TMU_WIDTH 1u
#define CSC0_STOP_ACKR0_TMU(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_TMU_SHIFT))&CSC0_STOP_ACKR0_TMU_MASK)
#define CSC0_STOP_ACKR0_ADC1_MASK 0x80u
#define CSC0_STOP_ACKR0_ADC1_SHIFT 7u
#define CSC0_STOP_ACKR0_ADC1_WIDTH 1u
#define CSC0_STOP_ACKR0_ADC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC1_SHIFT))&CSC0_STOP_ACKR0_ADC1_MASK)
#define CSC0_STOP_ACKR0_ADC0_MASK 0x40u
#define CSC0_STOP_ACKR0_ADC0_SHIFT 6u
#define CSC0_STOP_ACKR0_ADC0_WIDTH 1u
#define CSC0_STOP_ACKR0_ADC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ADC0_SHIFT))&CSC0_STOP_ACKR0_ADC0_MASK)
#define CSC0_STOP_ACKR0_CMU4_MASK 0x20u
#define CSC0_STOP_ACKR0_CMU4_SHIFT 5u
#define CSC0_STOP_ACKR0_CMU4_WIDTH 1u
#define CSC0_STOP_ACKR0_CMU4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_CMU4_SHIFT))&CSC0_STOP_ACKR0_CMU4_MASK)
#define CSC0_STOP_ACKR0_WDOG0_MASK 0x10u
#define CSC0_STOP_ACKR0_WDOG0_SHIFT 4u
#define CSC0_STOP_ACKR0_WDOG0_WIDTH 1u
#define CSC0_STOP_ACKR0_WDOG0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_WDOG0_SHIFT))&CSC0_STOP_ACKR0_WDOG0_MASK)
#define CSC0_STOP_ACKR0_ISM0_MASK 0x2u
#define CSC0_STOP_ACKR0_ISM0_SHIFT 1u
#define CSC0_STOP_ACKR0_ISM0_WIDTH 1u
#define CSC0_STOP_ACKR0_ISM0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_ISM0_SHIFT))&CSC0_STOP_ACKR0_ISM0_MASK)
#define CSC0_STOP_ACKR0_DMA0_MASK 0x1u
#define CSC0_STOP_ACKR0_DMA0_SHIFT 0u
#define CSC0_STOP_ACKR0_DMA0_WIDTH 1u
#define CSC0_STOP_ACKR0_DMA0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR0_DMA0_SHIFT))&CSC0_STOP_ACKR0_DMA0_MASK)
/* STOP_ACKR0 Reg Mask */
#define CSC0_STOP_ACKR0_MASK 0x0071DEF3u
/* STOP_MODER1 Bit Fields */
#define CSC0_STOP_MODER1_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER1_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER1_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER1_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WPB_LOCK_SHIFT))&CSC0_STOP_MODER1_WPB_LOCK_MASK)
#define CSC0_STOP_MODER1_WPB_MASK 0x70000000u
#define CSC0_STOP_MODER1_WPB_SHIFT 28u
#define CSC0_STOP_MODER1_WPB_WIDTH 3u
#define CSC0_STOP_MODER1_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WPB_SHIFT))&CSC0_STOP_MODER1_WPB_MASK)
#define CSC0_STOP_MODER1_FLEXCAN3_MASK 0x1000000u
#define CSC0_STOP_MODER1_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_MODER1_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_MODER1_FLEXCAN3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FLEXCAN3_SHIFT))&CSC0_STOP_MODER1_FLEXCAN3_MASK)
#define CSC0_STOP_MODER1_FLEXCAN2_MASK 0x800000u
#define CSC0_STOP_MODER1_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_MODER1_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_MODER1_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FLEXCAN2_SHIFT))&CSC0_STOP_MODER1_FLEXCAN2_MASK)
#define CSC0_STOP_MODER1_MSC0_MASK 0x200000u
#define CSC0_STOP_MODER1_MSC0_SHIFT 21u
#define CSC0_STOP_MODER1_MSC0_WIDTH 1u
#define CSC0_STOP_MODER1_MSC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_MSC0_SHIFT))&CSC0_STOP_MODER1_MSC0_MASK)
#define CSC0_STOP_MODER1_FCUART7_MASK 0x4000u
#define CSC0_STOP_MODER1_FCUART7_SHIFT 14u
#define CSC0_STOP_MODER1_FCUART7_WIDTH 1u
#define CSC0_STOP_MODER1_FCUART7(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCUART7_SHIFT))&CSC0_STOP_MODER1_FCUART7_MASK)
#define CSC0_STOP_MODER1_FCUART6_MASK 0x2000u
#define CSC0_STOP_MODER1_FCUART6_SHIFT 13u
#define CSC0_STOP_MODER1_FCUART6_WIDTH 1u
#define CSC0_STOP_MODER1_FCUART6(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCUART6_SHIFT))&CSC0_STOP_MODER1_FCUART6_MASK)
#define CSC0_STOP_MODER1_FCUART5_MASK 0x1000u
#define CSC0_STOP_MODER1_FCUART5_SHIFT 12u
#define CSC0_STOP_MODER1_FCUART5_WIDTH 1u
#define CSC0_STOP_MODER1_FCUART5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCUART5_SHIFT))&CSC0_STOP_MODER1_FCUART5_MASK)
#define CSC0_STOP_MODER1_FCUART4_MASK 0x800u
#define CSC0_STOP_MODER1_FCUART4_SHIFT 11u
#define CSC0_STOP_MODER1_FCUART4_WIDTH 1u
#define CSC0_STOP_MODER1_FCUART4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCUART4_SHIFT))&CSC0_STOP_MODER1_FCUART4_MASK)
#define CSC0_STOP_MODER1_FCIIC1_MASK 0x400u
#define CSC0_STOP_MODER1_FCIIC1_SHIFT 10u
#define CSC0_STOP_MODER1_FCIIC1_WIDTH 1u
#define CSC0_STOP_MODER1_FCIIC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCIIC1_SHIFT))&CSC0_STOP_MODER1_FCIIC1_MASK)
#define CSC0_STOP_MODER1_FCSPI5_MASK 0x100u
#define CSC0_STOP_MODER1_FCSPI5_SHIFT 8u
#define CSC0_STOP_MODER1_FCSPI5_WIDTH 1u
#define CSC0_STOP_MODER1_FCSPI5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCSPI5_SHIFT))&CSC0_STOP_MODER1_FCSPI5_MASK)
#define CSC0_STOP_MODER1_FCSPI4_MASK 0x80u
#define CSC0_STOP_MODER1_FCSPI4_SHIFT 7u
#define CSC0_STOP_MODER1_FCSPI4_WIDTH 1u
#define CSC0_STOP_MODER1_FCSPI4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCSPI4_SHIFT))&CSC0_STOP_MODER1_FCSPI4_MASK)
#define CSC0_STOP_MODER1_FCSPI3_MASK 0x40u
#define CSC0_STOP_MODER1_FCSPI3_SHIFT 6u
#define CSC0_STOP_MODER1_FCSPI3_WIDTH 1u
#define CSC0_STOP_MODER1_FCSPI3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_FCSPI3_SHIFT))&CSC0_STOP_MODER1_FCSPI3_MASK)
#define CSC0_STOP_MODER1_WDOG1_MASK 0x2u
#define CSC0_STOP_MODER1_WDOG1_SHIFT 1u
#define CSC0_STOP_MODER1_WDOG1_WIDTH 1u
#define CSC0_STOP_MODER1_WDOG1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER1_WDOG1_SHIFT))&CSC0_STOP_MODER1_WDOG1_MASK)
/* STOP_MODER1 Reg Mask */
#define CSC0_STOP_MODER1_MASK 0xF1A07DC2u
/* STOP_REQR1 Bit Fields */
#define CSC0_STOP_REQR1_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_REQR1_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR1_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR1_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WPB_LOCK_SHIFT))&CSC0_STOP_REQR1_WPB_LOCK_MASK)
#define CSC0_STOP_REQR1_WPB_MASK 0x70000000u
#define CSC0_STOP_REQR1_WPB_SHIFT 28u
#define CSC0_STOP_REQR1_WPB_WIDTH 3u
#define CSC0_STOP_REQR1_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WPB_SHIFT))&CSC0_STOP_REQR1_WPB_MASK)
#define CSC0_STOP_REQR1_FLEXCAN3_MASK 0x1000000u
#define CSC0_STOP_REQR1_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_REQR1_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_REQR1_FLEXCAN3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FLEXCAN3_SHIFT))&CSC0_STOP_REQR1_FLEXCAN3_MASK)
#define CSC0_STOP_REQR1_FLEXCAN2_MASK 0x800000u
#define CSC0_STOP_REQR1_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_REQR1_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_REQR1_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FLEXCAN2_SHIFT))&CSC0_STOP_REQR1_FLEXCAN2_MASK)
#define CSC0_STOP_REQR1_MSC0_MASK 0x200000u
#define CSC0_STOP_REQR1_MSC0_SHIFT 21u
#define CSC0_STOP_REQR1_MSC0_WIDTH 1u
#define CSC0_STOP_REQR1_MSC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_MSC0_SHIFT))&CSC0_STOP_REQR1_MSC0_MASK)
#define CSC0_STOP_REQR1_FCUART7_MASK 0x4000u
#define CSC0_STOP_REQR1_FCUART7_SHIFT 14u
#define CSC0_STOP_REQR1_FCUART7_WIDTH 1u
#define CSC0_STOP_REQR1_FCUART7(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCUART7_SHIFT))&CSC0_STOP_REQR1_FCUART7_MASK)
#define CSC0_STOP_REQR1_FCUART6_MASK 0x2000u
#define CSC0_STOP_REQR1_FCUART6_SHIFT 13u
#define CSC0_STOP_REQR1_FCUART6_WIDTH 1u
#define CSC0_STOP_REQR1_FCUART6(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCUART6_SHIFT))&CSC0_STOP_REQR1_FCUART6_MASK)
#define CSC0_STOP_REQR1_FCUART5_MASK 0x1000u
#define CSC0_STOP_REQR1_FCUART5_SHIFT 12u
#define CSC0_STOP_REQR1_FCUART5_WIDTH 1u
#define CSC0_STOP_REQR1_FCUART5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCUART5_SHIFT))&CSC0_STOP_REQR1_FCUART5_MASK)
#define CSC0_STOP_REQR1_FCUART4_MASK 0x800u
#define CSC0_STOP_REQR1_FCUART4_SHIFT 11u
#define CSC0_STOP_REQR1_FCUART4_WIDTH 1u
#define CSC0_STOP_REQR1_FCUART4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCUART4_SHIFT))&CSC0_STOP_REQR1_FCUART4_MASK)
#define CSC0_STOP_REQR1_FCIIC1_MASK 0x400u
#define CSC0_STOP_REQR1_FCIIC1_SHIFT 10u
#define CSC0_STOP_REQR1_FCIIC1_WIDTH 1u
#define CSC0_STOP_REQR1_FCIIC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCIIC1_SHIFT))&CSC0_STOP_REQR1_FCIIC1_MASK)
#define CSC0_STOP_REQR1_FCSPI5_MASK 0x100u
#define CSC0_STOP_REQR1_FCSPI5_SHIFT 8u
#define CSC0_STOP_REQR1_FCSPI5_WIDTH 1u
#define CSC0_STOP_REQR1_FCSPI5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCSPI5_SHIFT))&CSC0_STOP_REQR1_FCSPI5_MASK)
#define CSC0_STOP_REQR1_FCSPI4_MASK 0x80u
#define CSC0_STOP_REQR1_FCSPI4_SHIFT 7u
#define CSC0_STOP_REQR1_FCSPI4_WIDTH 1u
#define CSC0_STOP_REQR1_FCSPI4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCSPI4_SHIFT))&CSC0_STOP_REQR1_FCSPI4_MASK)
#define CSC0_STOP_REQR1_FCSPI3_MASK 0x40u
#define CSC0_STOP_REQR1_FCSPI3_SHIFT 6u
#define CSC0_STOP_REQR1_FCSPI3_WIDTH 1u
#define CSC0_STOP_REQR1_FCSPI3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_FCSPI3_SHIFT))&CSC0_STOP_REQR1_FCSPI3_MASK)
#define CSC0_STOP_REQR1_WDOG1_MASK 0x2u
#define CSC0_STOP_REQR1_WDOG1_SHIFT 1u
#define CSC0_STOP_REQR1_WDOG1_WIDTH 1u
#define CSC0_STOP_REQR1_WDOG1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR1_WDOG1_SHIFT))&CSC0_STOP_REQR1_WDOG1_MASK)
/* STOP_REQR1 Reg Mask */
#define CSC0_STOP_REQR1_MASK 0xF1A07DC2u
/* STOP_ACKR1 Bit Fields */
#define CSC0_STOP_ACKR1_FLEXCAN3_MASK 0x1000000u
#define CSC0_STOP_ACKR1_FLEXCAN3_SHIFT 24u
#define CSC0_STOP_ACKR1_FLEXCAN3_WIDTH 1u
#define CSC0_STOP_ACKR1_FLEXCAN3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FLEXCAN3_SHIFT))&CSC0_STOP_ACKR1_FLEXCAN3_MASK)
#define CSC0_STOP_ACKR1_FLEXCAN2_MASK 0x800000u
#define CSC0_STOP_ACKR1_FLEXCAN2_SHIFT 23u
#define CSC0_STOP_ACKR1_FLEXCAN2_WIDTH 1u
#define CSC0_STOP_ACKR1_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FLEXCAN2_SHIFT))&CSC0_STOP_ACKR1_FLEXCAN2_MASK)
#define CSC0_STOP_ACKR1_MSC0_MASK 0x200000u
#define CSC0_STOP_ACKR1_MSC0_SHIFT 21u
#define CSC0_STOP_ACKR1_MSC0_WIDTH 1u
#define CSC0_STOP_ACKR1_MSC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_MSC0_SHIFT))&CSC0_STOP_ACKR1_MSC0_MASK)
#define CSC0_STOP_ACKR1_FCUART7_MASK 0x4000u
#define CSC0_STOP_ACKR1_FCUART7_SHIFT 14u
#define CSC0_STOP_ACKR1_FCUART7_WIDTH 1u
#define CSC0_STOP_ACKR1_FCUART7(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCUART7_SHIFT))&CSC0_STOP_ACKR1_FCUART7_MASK)
#define CSC0_STOP_ACKR1_FCUART6_MASK 0x2000u
#define CSC0_STOP_ACKR1_FCUART6_SHIFT 13u
#define CSC0_STOP_ACKR1_FCUART6_WIDTH 1u
#define CSC0_STOP_ACKR1_FCUART6(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCUART6_SHIFT))&CSC0_STOP_ACKR1_FCUART6_MASK)
#define CSC0_STOP_ACKR1_FCUART5_MASK 0x1000u
#define CSC0_STOP_ACKR1_FCUART5_SHIFT 12u
#define CSC0_STOP_ACKR1_FCUART5_WIDTH 1u
#define CSC0_STOP_ACKR1_FCUART5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCUART5_SHIFT))&CSC0_STOP_ACKR1_FCUART5_MASK)
#define CSC0_STOP_ACKR1_FCUART4_MASK 0x800u
#define CSC0_STOP_ACKR1_FCUART4_SHIFT 11u
#define CSC0_STOP_ACKR1_FCUART4_WIDTH 1u
#define CSC0_STOP_ACKR1_FCUART4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCUART4_SHIFT))&CSC0_STOP_ACKR1_FCUART4_MASK)
#define CSC0_STOP_ACKR1_FCIIC1_MASK 0x400u
#define CSC0_STOP_ACKR1_FCIIC1_SHIFT 10u
#define CSC0_STOP_ACKR1_FCIIC1_WIDTH 1u
#define CSC0_STOP_ACKR1_FCIIC1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCIIC1_SHIFT))&CSC0_STOP_ACKR1_FCIIC1_MASK)
#define CSC0_STOP_ACKR1_FCSPI5_MASK 0x100u
#define CSC0_STOP_ACKR1_FCSPI5_SHIFT 8u
#define CSC0_STOP_ACKR1_FCSPI5_WIDTH 1u
#define CSC0_STOP_ACKR1_FCSPI5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCSPI5_SHIFT))&CSC0_STOP_ACKR1_FCSPI5_MASK)
#define CSC0_STOP_ACKR1_FCSPI4_MASK 0x80u
#define CSC0_STOP_ACKR1_FCSPI4_SHIFT 7u
#define CSC0_STOP_ACKR1_FCSPI4_WIDTH 1u
#define CSC0_STOP_ACKR1_FCSPI4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCSPI4_SHIFT))&CSC0_STOP_ACKR1_FCSPI4_MASK)
#define CSC0_STOP_ACKR1_FCSPI3_MASK 0x40u
#define CSC0_STOP_ACKR1_FCSPI3_SHIFT 6u
#define CSC0_STOP_ACKR1_FCSPI3_WIDTH 1u
#define CSC0_STOP_ACKR1_FCSPI3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_FCSPI3_SHIFT))&CSC0_STOP_ACKR1_FCSPI3_MASK)
#define CSC0_STOP_ACKR1_WDOG1_MASK 0x2u
#define CSC0_STOP_ACKR1_WDOG1_SHIFT 1u
#define CSC0_STOP_ACKR1_WDOG1_WIDTH 1u
#define CSC0_STOP_ACKR1_WDOG1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR1_WDOG1_SHIFT))&CSC0_STOP_ACKR1_WDOG1_MASK)
/* STOP_ACKR1 Reg Mask */
#define CSC0_STOP_ACKR1_MASK 0x01A07DC2u
/* STOP_MODER2 Bit Fields */
#define CSC0_STOP_MODER2_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_MODER2_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_MODER2_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_MODER2_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_WPB_LOCK_SHIFT))&CSC0_STOP_MODER2_WPB_LOCK_MASK)
#define CSC0_STOP_MODER2_WPB_MASK 0x70000000u
#define CSC0_STOP_MODER2_WPB_SHIFT 28u
#define CSC0_STOP_MODER2_WPB_WIDTH 3u
#define CSC0_STOP_MODER2_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_WPB_SHIFT))&CSC0_STOP_MODER2_WPB_MASK)
#define CSC0_STOP_MODER2_FCUART0_MASK 0x400u
#define CSC0_STOP_MODER2_FCUART0_SHIFT 10u
#define CSC0_STOP_MODER2_FCUART0_WIDTH 1u
#define CSC0_STOP_MODER2_FCUART0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCUART0_SHIFT))&CSC0_STOP_MODER2_FCUART0_MASK)
#define CSC0_STOP_MODER2_FCIIC0_MASK 0x200u
#define CSC0_STOP_MODER2_FCIIC0_SHIFT 9u
#define CSC0_STOP_MODER2_FCIIC0_WIDTH 1u
#define CSC0_STOP_MODER2_FCIIC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCIIC0_SHIFT))&CSC0_STOP_MODER2_FCIIC0_MASK)
#define CSC0_STOP_MODER2_FCSPI0_MASK 0x100u
#define CSC0_STOP_MODER2_FCSPI0_SHIFT 8u
#define CSC0_STOP_MODER2_FCSPI0_WIDTH 1u
#define CSC0_STOP_MODER2_FCSPI0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_FCSPI0_SHIFT))&CSC0_STOP_MODER2_FCSPI0_MASK)
#define CSC0_STOP_MODER2_CMP1_MASK 0x80u
#define CSC0_STOP_MODER2_CMP1_SHIFT 7u
#define CSC0_STOP_MODER2_CMP1_WIDTH 1u
#define CSC0_STOP_MODER2_CMP1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMP1_SHIFT))&CSC0_STOP_MODER2_CMP1_MASK)
#define CSC0_STOP_MODER2_CMP0_MASK 0x40u
#define CSC0_STOP_MODER2_CMP0_SHIFT 6u
#define CSC0_STOP_MODER2_CMP0_WIDTH 1u
#define CSC0_STOP_MODER2_CMP0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMP0_SHIFT))&CSC0_STOP_MODER2_CMP0_MASK)
#define CSC0_STOP_MODER2_CMU3_MASK 0x20u
#define CSC0_STOP_MODER2_CMU3_SHIFT 5u
#define CSC0_STOP_MODER2_CMU3_WIDTH 1u
#define CSC0_STOP_MODER2_CMU3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU3_SHIFT))&CSC0_STOP_MODER2_CMU3_MASK)
#define CSC0_STOP_MODER2_CMU2_MASK 0x10u
#define CSC0_STOP_MODER2_CMU2_SHIFT 4u
#define CSC0_STOP_MODER2_CMU2_WIDTH 1u
#define CSC0_STOP_MODER2_CMU2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU2_SHIFT))&CSC0_STOP_MODER2_CMU2_MASK)
#define CSC0_STOP_MODER2_CMU1_MASK 0x8u
#define CSC0_STOP_MODER2_CMU1_SHIFT 3u
#define CSC0_STOP_MODER2_CMU1_WIDTH 1u
#define CSC0_STOP_MODER2_CMU1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU1_SHIFT))&CSC0_STOP_MODER2_CMU1_MASK)
#define CSC0_STOP_MODER2_CMU0_MASK 0x4u
#define CSC0_STOP_MODER2_CMU0_SHIFT 2u
#define CSC0_STOP_MODER2_CMU0_WIDTH 1u
#define CSC0_STOP_MODER2_CMU0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_MODER2_CMU0_SHIFT))&CSC0_STOP_MODER2_CMU0_MASK)
/* STOP_MODER2 Reg Mask */
#define CSC0_STOP_MODER2_MASK 0xF00007FCu
/* STOP_REQR2 Bit Fields */
#define CSC0_STOP_REQR2_WPB_LOCK_MASK 0x80000000u
#define CSC0_STOP_REQR2_WPB_LOCK_SHIFT 31u
#define CSC0_STOP_REQR2_WPB_LOCK_WIDTH 1u
#define CSC0_STOP_REQR2_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_WPB_LOCK_SHIFT))&CSC0_STOP_REQR2_WPB_LOCK_MASK)
#define CSC0_STOP_REQR2_WPB_MASK 0x70000000u
#define CSC0_STOP_REQR2_WPB_SHIFT 28u
#define CSC0_STOP_REQR2_WPB_WIDTH 3u
#define CSC0_STOP_REQR2_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_WPB_SHIFT))&CSC0_STOP_REQR2_WPB_MASK)
#define CSC0_STOP_REQR2_FCUART0_MASK 0x400u
#define CSC0_STOP_REQR2_FCUART0_SHIFT 10u
#define CSC0_STOP_REQR2_FCUART0_WIDTH 1u
#define CSC0_STOP_REQR2_FCUART0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCUART0_SHIFT))&CSC0_STOP_REQR2_FCUART0_MASK)
#define CSC0_STOP_REQR2_FCIIC0_MASK 0x200u
#define CSC0_STOP_REQR2_FCIIC0_SHIFT 9u
#define CSC0_STOP_REQR2_FCIIC0_WIDTH 1u
#define CSC0_STOP_REQR2_FCIIC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCIIC0_SHIFT))&CSC0_STOP_REQR2_FCIIC0_MASK)
#define CSC0_STOP_REQR2_FCSPI0_MASK 0x100u
#define CSC0_STOP_REQR2_FCSPI0_SHIFT 8u
#define CSC0_STOP_REQR2_FCSPI0_WIDTH 1u
#define CSC0_STOP_REQR2_FCSPI0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_FCSPI0_SHIFT))&CSC0_STOP_REQR2_FCSPI0_MASK)
#define CSC0_STOP_REQR2_CMP1_MASK 0x80u
#define CSC0_STOP_REQR2_CMP1_SHIFT 7u
#define CSC0_STOP_REQR2_CMP1_WIDTH 1u
#define CSC0_STOP_REQR2_CMP1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMP1_SHIFT))&CSC0_STOP_REQR2_CMP1_MASK)
#define CSC0_STOP_REQR2_CMP0_MASK 0x40u
#define CSC0_STOP_REQR2_CMP0_SHIFT 6u
#define CSC0_STOP_REQR2_CMP0_WIDTH 1u
#define CSC0_STOP_REQR2_CMP0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMP0_SHIFT))&CSC0_STOP_REQR2_CMP0_MASK)
#define CSC0_STOP_REQR2_CMU3_MASK 0x20u
#define CSC0_STOP_REQR2_CMU3_SHIFT 5u
#define CSC0_STOP_REQR2_CMU3_WIDTH 1u
#define CSC0_STOP_REQR2_CMU3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU3_SHIFT))&CSC0_STOP_REQR2_CMU3_MASK)
#define CSC0_STOP_REQR2_CMU2_MASK 0x10u
#define CSC0_STOP_REQR2_CMU2_SHIFT 4u
#define CSC0_STOP_REQR2_CMU2_WIDTH 1u
#define CSC0_STOP_REQR2_CMU2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU2_SHIFT))&CSC0_STOP_REQR2_CMU2_MASK)
#define CSC0_STOP_REQR2_CMU1_MASK 0x8u
#define CSC0_STOP_REQR2_CMU1_SHIFT 3u
#define CSC0_STOP_REQR2_CMU1_WIDTH 1u
#define CSC0_STOP_REQR2_CMU1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU1_SHIFT))&CSC0_STOP_REQR2_CMU1_MASK)
#define CSC0_STOP_REQR2_CMU0_MASK 0x4u
#define CSC0_STOP_REQR2_CMU0_SHIFT 2u
#define CSC0_STOP_REQR2_CMU0_WIDTH 1u
#define CSC0_STOP_REQR2_CMU0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_REQR2_CMU0_SHIFT))&CSC0_STOP_REQR2_CMU0_MASK)
/* STOP_REQR2 Reg Mask */
#define CSC0_STOP_REQR2_MASK 0xF00007FCu
/* STOP_ACKR2 Bit Fields */
#define CSC0_STOP_ACKR2_FCUART0_MASK 0x400u
#define CSC0_STOP_ACKR2_FCUART0_SHIFT 10u
#define CSC0_STOP_ACKR2_FCUART0_WIDTH 1u
#define CSC0_STOP_ACKR2_FCUART0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCUART0_SHIFT))&CSC0_STOP_ACKR2_FCUART0_MASK)
#define CSC0_STOP_ACKR2_FCIIC0_MASK 0x200u
#define CSC0_STOP_ACKR2_FCIIC0_SHIFT 9u
#define CSC0_STOP_ACKR2_FCIIC0_WIDTH 1u
#define CSC0_STOP_ACKR2_FCIIC0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCIIC0_SHIFT))&CSC0_STOP_ACKR2_FCIIC0_MASK)
#define CSC0_STOP_ACKR2_FCSPI0_MASK 0x100u
#define CSC0_STOP_ACKR2_FCSPI0_SHIFT 8u
#define CSC0_STOP_ACKR2_FCSPI0_WIDTH 1u
#define CSC0_STOP_ACKR2_FCSPI0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_FCSPI0_SHIFT))&CSC0_STOP_ACKR2_FCSPI0_MASK)
#define CSC0_STOP_ACKR2_CMP1_MASK 0x80u
#define CSC0_STOP_ACKR2_CMP1_SHIFT 7u
#define CSC0_STOP_ACKR2_CMP1_WIDTH 1u
#define CSC0_STOP_ACKR2_CMP1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMP1_SHIFT))&CSC0_STOP_ACKR2_CMP1_MASK)
#define CSC0_STOP_ACKR2_CMP0_MASK 0x40u
#define CSC0_STOP_ACKR2_CMP0_SHIFT 6u
#define CSC0_STOP_ACKR2_CMP0_WIDTH 1u
#define CSC0_STOP_ACKR2_CMP0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMP0_SHIFT))&CSC0_STOP_ACKR2_CMP0_MASK)
#define CSC0_STOP_ACKR2_CMU3_MASK 0x20u
#define CSC0_STOP_ACKR2_CMU3_SHIFT 5u
#define CSC0_STOP_ACKR2_CMU3_WIDTH 1u
#define CSC0_STOP_ACKR2_CMU3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU3_SHIFT))&CSC0_STOP_ACKR2_CMU3_MASK)
#define CSC0_STOP_ACKR2_CMU2_MASK 0x10u
#define CSC0_STOP_ACKR2_CMU2_SHIFT 4u
#define CSC0_STOP_ACKR2_CMU2_WIDTH 1u
#define CSC0_STOP_ACKR2_CMU2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU2_SHIFT))&CSC0_STOP_ACKR2_CMU2_MASK)
#define CSC0_STOP_ACKR2_CMU1_MASK 0x8u
#define CSC0_STOP_ACKR2_CMU1_SHIFT 3u
#define CSC0_STOP_ACKR2_CMU1_WIDTH 1u
#define CSC0_STOP_ACKR2_CMU1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU1_SHIFT))&CSC0_STOP_ACKR2_CMU1_MASK)
#define CSC0_STOP_ACKR2_CMU0_MASK 0x4u
#define CSC0_STOP_ACKR2_CMU0_SHIFT 2u
#define CSC0_STOP_ACKR2_CMU0_WIDTH 1u
#define CSC0_STOP_ACKR2_CMU0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_STOP_ACKR2_CMU0_SHIFT))&CSC0_STOP_ACKR2_CMU0_MASK)
/* STOP_ACKR2 Reg Mask */
#define CSC0_STOP_ACKR2_MASK 0x000007FCu
/* CCM0_CFG Bit Fields */
#define CSC0_CCM0_CFG_WPB_LOCK_MASK 0x80000000u
#define CSC0_CCM0_CFG_WPB_LOCK_SHIFT 31u
#define CSC0_CCM0_CFG_WPB_LOCK_WIDTH 1u
#define CSC0_CCM0_CFG_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_WPB_LOCK_SHIFT))&CSC0_CCM0_CFG_WPB_LOCK_MASK)
#define CSC0_CCM0_CFG_WPB_MASK 0x70000000u
#define CSC0_CCM0_CFG_WPB_SHIFT 28u
#define CSC0_CCM0_CFG_WPB_WIDTH 3u
#define CSC0_CCM0_CFG_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_WPB_SHIFT))&CSC0_CCM0_CFG_WPB_MASK)
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK 0x4u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_SHIFT 2u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_WIDTH 1u
#define CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_SHIFT))&CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK)
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK 0x3u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT 0u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_WIDTH 2u
#define CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT))&CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK)
/* CCM0_CFG Reg Mask */
#define CSC0_CCM0_CFG_MASK 0xF0000007u
/* CCM0_STATUS Bit Fields */
#define CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK 0x80u
#define CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_SHIFT 7u
#define CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_WIDTH 1u
#define CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_SHIFT))&CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK)
#define CSC0_CCM0_STATUS_CPU0_STOP_MASTER_MASK 0x40u
#define CSC0_CCM0_STATUS_CPU0_STOP_MASTER_SHIFT 6u
#define CSC0_CCM0_STATUS_CPU0_STOP_MASTER_WIDTH 1u
#define CSC0_CCM0_STATUS_CPU0_STOP_MASTER(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_STATUS_CPU0_STOP_MASTER_SHIFT))&CSC0_CCM0_STATUS_CPU0_STOP_MASTER_MASK)
#define CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK 0x20u
#define CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_SHIFT 5u
#define CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_WIDTH 1u
#define CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_SHIFT))&CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK)
#define CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK 0x10u
#define CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_SHIFT 4u
#define CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_WIDTH 1u
#define CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_SHIFT))&CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK)
/* CCM0_STATUS Reg Mask */
#define CSC0_CCM0_STATUS_MASK 0x000000F0u
/* SCG_MAM_STALL Bit Fields */
#define CSC0_SCG_MAM_STALL_SCG_STALL_MASK 0x2u
#define CSC0_SCG_MAM_STALL_SCG_STALL_SHIFT 1u
#define CSC0_SCG_MAM_STALL_SCG_STALL_WIDTH 1u
#define CSC0_SCG_MAM_STALL_SCG_STALL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SCG_MAM_STALL_SCG_STALL_SHIFT))&CSC0_SCG_MAM_STALL_SCG_STALL_MASK)
#define CSC0_SCG_MAM_STALL_LOCK_MASK 0x1u
#define CSC0_SCG_MAM_STALL_LOCK_SHIFT 0u
#define CSC0_SCG_MAM_STALL_LOCK_WIDTH 1u
#define CSC0_SCG_MAM_STALL_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SCG_MAM_STALL_LOCK_SHIFT))&CSC0_SCG_MAM_STALL_LOCK_MASK)
/* SCG_MAM_STALL Reg Mask */
#define CSC0_SCG_MAM_STALL_MASK 0x00000003u
/* CPU0_INT Bit Fields */
#define CSC0_CPU0_INT_WPB_LOCK_MASK 0x80000000u
#define CSC0_CPU0_INT_WPB_LOCK_SHIFT 31u
#define CSC0_CPU0_INT_WPB_LOCK_WIDTH 1u
#define CSC0_CPU0_INT_WPB_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_WPB_LOCK_SHIFT))&CSC0_CPU0_INT_WPB_LOCK_MASK)
#define CSC0_CPU0_INT_WPB_MASK 0x70000000u
#define CSC0_CPU0_INT_WPB_SHIFT 28u
#define CSC0_CPU0_INT_WPB_WIDTH 3u
#define CSC0_CPU0_INT_WPB(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_WPB_SHIFT))&CSC0_CPU0_INT_WPB_MASK)
#define CSC0_CPU0_INT_SW_INT_MASK 0x1u
#define CSC0_CPU0_INT_SW_INT_SHIFT 0u
#define CSC0_CPU0_INT_SW_INT_WIDTH 1u
#define CSC0_CPU0_INT_SW_INT(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CPU0_INT_SW_INT_SHIFT))&CSC0_CPU0_INT_SW_INT_MASK)
/* CPU0_INT Reg Mask */
#define CSC0_CPU0_INT_MASK 0xF0000001u
/* CLKOUT_CTRL Bit Fields */
#define CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK 0x80000000u
#define CSC0_CLKOUT_CTRL_CLKOUT_EN_SHIFT 31u
#define CSC0_CLKOUT_CTRL_CLKOUT_EN_WIDTH 1u
#define CSC0_CLKOUT_CTRL_CLKOUT_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CLKOUT_CTRL_CLKOUT_EN_SHIFT))&CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK)
#define CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK 0x70000000u
#define CSC0_CLKOUT_CTRL_CLKOUT_DIV_SHIFT 28u
#define CSC0_CLKOUT_CTRL_CLKOUT_DIV_WIDTH 3u
#define CSC0_CLKOUT_CTRL_CLKOUT_DIV(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CLKOUT_CTRL_CLKOUT_DIV_SHIFT))&CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK)
#define CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK 0xF000000u
#define CSC0_CLKOUT_CTRL_CLKOUT_SEL_SHIFT 24u
#define CSC0_CLKOUT_CTRL_CLKOUT_SEL_WIDTH 4u
#define CSC0_CLKOUT_CTRL_CLKOUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CLKOUT_CTRL_CLKOUT_SEL_SHIFT))&CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK)
#define CSC0_CLKOUT_CTRL_LOCK_MASK 0x1u
#define CSC0_CLKOUT_CTRL_LOCK_SHIFT 0u
#define CSC0_CLKOUT_CTRL_LOCK_WIDTH 1u
#define CSC0_CLKOUT_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CLKOUT_CTRL_LOCK_SHIFT))&CSC0_CLKOUT_CTRL_LOCK_MASK)
/* CLKOUT_CTRL Reg Mask */
#define CSC0_CLKOUT_CTRL_MASK 0xFF000001u
/* AONCLKSR Bit Fields */
#define CSC0_AONCLKSR_AON32KCLKSEL_MASK 0xC000u
#define CSC0_AONCLKSR_AON32KCLKSEL_SHIFT 14u
#define CSC0_AONCLKSR_AON32KCLKSEL_WIDTH 2u
#define CSC0_AONCLKSR_AON32KCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_AON32KCLKSEL_SHIFT))&CSC0_AONCLKSR_AON32KCLKSEL_MASK)
#define CSC0_AONCLKSR_RTCCLKSEL_MASK 0x3000u
#define CSC0_AONCLKSR_RTCCLKSEL_SHIFT 12u
#define CSC0_AONCLKSR_RTCCLKSEL_WIDTH 2u
#define CSC0_AONCLKSR_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_RTCCLKSEL_SHIFT))&CSC0_AONCLKSR_RTCCLKSEL_MASK)
#define CSC0_AONCLKSR_AONCLKSEL_MASK 0xC00u
#define CSC0_AONCLKSR_AONCLKSEL_SHIFT 10u
#define CSC0_AONCLKSR_AONCLKSEL_WIDTH 2u
#define CSC0_AONCLKSR_AONCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_AONCLKSEL_SHIFT))&CSC0_AONCLKSR_AONCLKSEL_MASK)
#define CSC0_AONCLKSR_SIRCDIV32KEN_MASK 0x200u
#define CSC0_AONCLKSR_SIRCDIV32KEN_SHIFT 9u
#define CSC0_AONCLKSR_SIRCDIV32KEN_WIDTH 1u
#define CSC0_AONCLKSR_SIRCDIV32KEN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_SIRCDIV32KEN_SHIFT))&CSC0_AONCLKSR_SIRCDIV32KEN_MASK)
#define CSC0_AONCLKSR_AON1KCLKEN_MASK 0x100u
#define CSC0_AONCLKSR_AON1KCLKEN_SHIFT 8u
#define CSC0_AONCLKSR_AON1KCLKEN_WIDTH 1u
#define CSC0_AONCLKSR_AON1KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_AON1KCLKEN_SHIFT))&CSC0_AONCLKSR_AON1KCLKEN_MASK)
#define CSC0_AONCLKSR_LOCK_MASK 0x1u
#define CSC0_AONCLKSR_LOCK_SHIFT 0u
#define CSC0_AONCLKSR_LOCK_WIDTH 1u
#define CSC0_AONCLKSR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_AONCLKSR_LOCK_SHIFT))&CSC0_AONCLKSR_LOCK_MASK)
/* AONCLKSR Reg Mask */
#define CSC0_AONCLKSR_MASK 0x0000FF01u
/* PCU_CTRL Bit Fields */
#define CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK 0xFF000000u
#define CSC0_PCU_CTRL_RPM_EXIT_CNT_SHIFT 24u
#define CSC0_PCU_CTRL_RPM_EXIT_CNT_WIDTH 8u
#define CSC0_PCU_CTRL_RPM_EXIT_CNT(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PCU_CTRL_RPM_EXIT_CNT_SHIFT))&CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_MASK 0x80u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_SHIFT 7u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_WIDTH 1u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PCU_CTRL_PAD_ISO_HOLD_SHIFT))&CSC0_PCU_CTRL_PAD_ISO_HOLD_MASK)
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_MASK 0x40u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_SHIFT 6u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_WIDTH 1u
#define CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_SHIFT))&CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_MASK)
#define CSC0_PCU_CTRL_LOCK_MASK 0x1u
#define CSC0_PCU_CTRL_LOCK_SHIFT 0u
#define CSC0_PCU_CTRL_LOCK_WIDTH 1u
#define CSC0_PCU_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_PCU_CTRL_LOCK_SHIFT))&CSC0_PCU_CTRL_LOCK_MASK)
/* PCU_CTRL Reg Mask */
#define CSC0_PCU_CTRL_MASK 0xFF0000C1u
/* SMU_CTRL0 Bit Fields */
#define CSC0_SMU_CTRL0_CMU4_MASK 0x80000000u
#define CSC0_SMU_CTRL0_CMU4_SHIFT 31u
#define CSC0_SMU_CTRL0_CMU4_WIDTH 1u
#define CSC0_SMU_CTRL0_CMU4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU4_SHIFT))&CSC0_SMU_CTRL0_CMU4_MASK)
#define CSC0_SMU_CTRL0_PMC_MON_MASK 0x40000000u
#define CSC0_SMU_CTRL0_PMC_MON_SHIFT 30u
#define CSC0_SMU_CTRL0_PMC_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_PMC_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_PMC_MON_SHIFT))&CSC0_SMU_CTRL0_PMC_MON_MASK)
#define CSC0_SMU_CTRL0_CMU2_MASK 0x20000000u
#define CSC0_SMU_CTRL0_CMU2_SHIFT 29u
#define CSC0_SMU_CTRL0_CMU2_WIDTH 1u
#define CSC0_SMU_CTRL0_CMU2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU2_SHIFT))&CSC0_SMU_CTRL0_CMU2_MASK)
#define CSC0_SMU_CTRL0_CMU1_MASK 0x10000000u
#define CSC0_SMU_CTRL0_CMU1_SHIFT 28u
#define CSC0_SMU_CTRL0_CMU1_WIDTH 1u
#define CSC0_SMU_CTRL0_CMU1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CMU1_SHIFT))&CSC0_SMU_CTRL0_CMU1_MASK)
#define CSC0_SMU_CTRL0_PMC_LVD_HVD_MASK 0x8000000u
#define CSC0_SMU_CTRL0_PMC_LVD_HVD_SHIFT 27u
#define CSC0_SMU_CTRL0_PMC_LVD_HVD_WIDTH 1u
#define CSC0_SMU_CTRL0_PMC_LVD_HVD(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_PMC_LVD_HVD_SHIFT))&CSC0_SMU_CTRL0_PMC_LVD_HVD_MASK)
#define CSC0_SMU_CTRL0_SRAM1_MON_MASK 0x2000000u
#define CSC0_SMU_CTRL0_SRAM1_MON_SHIFT 25u
#define CSC0_SMU_CTRL0_SRAM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_SRAM1_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_SRAM1_MON_SHIFT))&CSC0_SMU_CTRL0_SRAM1_MON_MASK)
#define CSC0_SMU_CTRL0_SRAM0_MON_MASK 0x1000000u
#define CSC0_SMU_CTRL0_SRAM0_MON_SHIFT 24u
#define CSC0_SMU_CTRL0_SRAM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_SRAM0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_SRAM0_MON_SHIFT))&CSC0_SMU_CTRL0_SRAM0_MON_MASK)
#define CSC0_SMU_CTRL0_CPM_MON_MASK 0x800000u
#define CSC0_SMU_CTRL0_CPM_MON_SHIFT 23u
#define CSC0_SMU_CTRL0_CPM_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_CPM_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CPM_MON_SHIFT))&CSC0_SMU_CTRL0_CPM_MON_MASK)
#define CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_MASK 0x400000u
#define CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_SHIFT 22u
#define CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S5_DS_ECC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_SHIFT))&CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_MASK)
#define CSC0_SMU_CTRL0_MAM0_S8_DS_MASK 0x200000u
#define CSC0_SMU_CTRL0_MAM0_S8_DS_SHIFT 21u
#define CSC0_SMU_CTRL0_MAM0_S8_DS_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S8_DS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S8_DS_SHIFT))&CSC0_SMU_CTRL0_MAM0_S8_DS_MASK)
#define CSC0_SMU_CTRL0_MAM0_S5_DS_MASK 0x100000u
#define CSC0_SMU_CTRL0_MAM0_S5_DS_SHIFT 20u
#define CSC0_SMU_CTRL0_MAM0_S5_DS_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S5_DS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S5_DS_SHIFT))&CSC0_SMU_CTRL0_MAM0_S5_DS_MASK)
#define CSC0_SMU_CTRL0_DMA0_MASK 0x40000u
#define CSC0_SMU_CTRL0_DMA0_SHIFT 18u
#define CSC0_SMU_CTRL0_DMA0_WIDTH 1u
#define CSC0_SMU_CTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_DMA0_SHIFT))&CSC0_SMU_CTRL0_DMA0_MASK)
#define CSC0_SMU_CTRL0_HSM_MASK 0x20000u
#define CSC0_SMU_CTRL0_HSM_SHIFT 17u
#define CSC0_SMU_CTRL0_HSM_WIDTH 1u
#define CSC0_SMU_CTRL0_HSM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_HSM_SHIFT))&CSC0_SMU_CTRL0_HSM_MASK)
#define CSC0_SMU_CTRL0_MAM0_S2F_MON_MASK 0x8000u
#define CSC0_SMU_CTRL0_MAM0_S2F_MON_SHIFT 15u
#define CSC0_SMU_CTRL0_MAM0_S2F_MON_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S2F_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S2F_MON_SHIFT))&CSC0_SMU_CTRL0_MAM0_S2F_MON_MASK)
#define CSC0_SMU_CTRL0_CPU0_AHBS_MASK 0x1000u
#define CSC0_SMU_CTRL0_CPU0_AHBS_SHIFT 12u
#define CSC0_SMU_CTRL0_CPU0_AHBS_WIDTH 1u
#define CSC0_SMU_CTRL0_CPU0_AHBS(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_CPU0_AHBS_SHIFT))&CSC0_SMU_CTRL0_CPU0_AHBS_MASK)
#define CSC0_SMU_CTRL0_MAM0_S8_MASK 0x800u
#define CSC0_SMU_CTRL0_MAM0_S8_SHIFT 11u
#define CSC0_SMU_CTRL0_MAM0_S8_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S8(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S8_SHIFT))&CSC0_SMU_CTRL0_MAM0_S8_MASK)
#define CSC0_SMU_CTRL0_MAM0_S7_MASK 0x400u
#define CSC0_SMU_CTRL0_MAM0_S7_SHIFT 10u
#define CSC0_SMU_CTRL0_MAM0_S7_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S7(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S7_SHIFT))&CSC0_SMU_CTRL0_MAM0_S7_MASK)
#define CSC0_SMU_CTRL0_MAM0_S6_MASK 0x200u
#define CSC0_SMU_CTRL0_MAM0_S6_SHIFT 9u
#define CSC0_SMU_CTRL0_MAM0_S6_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S6(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S6_SHIFT))&CSC0_SMU_CTRL0_MAM0_S6_MASK)
#define CSC0_SMU_CTRL0_MAM0_S5_MASK 0x100u
#define CSC0_SMU_CTRL0_MAM0_S5_SHIFT 8u
#define CSC0_SMU_CTRL0_MAM0_S5_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S5(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S5_SHIFT))&CSC0_SMU_CTRL0_MAM0_S5_MASK)
#define CSC0_SMU_CTRL0_MAM0_S4_MASK 0x40u
#define CSC0_SMU_CTRL0_MAM0_S4_SHIFT 6u
#define CSC0_SMU_CTRL0_MAM0_S4_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S4_SHIFT))&CSC0_SMU_CTRL0_MAM0_S4_MASK)
#define CSC0_SMU_CTRL0_MAM0_S3_MASK 0x20u
#define CSC0_SMU_CTRL0_MAM0_S3_SHIFT 5u
#define CSC0_SMU_CTRL0_MAM0_S3_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S3_SHIFT))&CSC0_SMU_CTRL0_MAM0_S3_MASK)
#define CSC0_SMU_CTRL0_MAM0_S2_MASK 0x8u
#define CSC0_SMU_CTRL0_MAM0_S2_SHIFT 3u
#define CSC0_SMU_CTRL0_MAM0_S2_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S2_SHIFT))&CSC0_SMU_CTRL0_MAM0_S2_MASK)
#define CSC0_SMU_CTRL0_MAM0_S1_MASK 0x4u
#define CSC0_SMU_CTRL0_MAM0_S1_SHIFT 2u
#define CSC0_SMU_CTRL0_MAM0_S1_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S1_SHIFT))&CSC0_SMU_CTRL0_MAM0_S1_MASK)
#define CSC0_SMU_CTRL0_MAM0_S0_MASK 0x2u
#define CSC0_SMU_CTRL0_MAM0_S0_SHIFT 1u
#define CSC0_SMU_CTRL0_MAM0_S0_WIDTH 1u
#define CSC0_SMU_CTRL0_MAM0_S0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_MAM0_S0_SHIFT))&CSC0_SMU_CTRL0_MAM0_S0_MASK)
#define CSC0_SMU_CTRL0_LOCK_MASK 0x1u
#define CSC0_SMU_CTRL0_LOCK_SHIFT 0u
#define CSC0_SMU_CTRL0_LOCK_WIDTH 1u
#define CSC0_SMU_CTRL0_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL0_LOCK_SHIFT))&CSC0_SMU_CTRL0_LOCK_MASK)
/* SMU_CTRL0 Reg Mask */
#define CSC0_SMU_CTRL0_MASK 0xFBF69F6Fu
/* SMU_CTRL1 Bit Fields */
#define CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_MASK 0x40000u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_SHIFT 18u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_MASK 0x20000u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_SHIFT 17u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_MASK)
#define CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_MASK 0x10000u
#define CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_SHIFT 16u
#define CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ITCM_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_SHIFT))&CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_MASK)
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK 0x8000u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_SHIFT 15u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_OVERLAY(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_OVERLAY_SHIFT))&CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK 0x4000u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_SHIFT 14u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM1_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK 0x2000u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_SHIFT 13u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM0_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK 0x1000u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_SHIFT 12u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ITCM_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ITCM_MON_SHIFT))&CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_MASK 0x400u
#define CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_SHIFT 10u
#define CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM1_F2S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_MASK 0x200u
#define CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_SHIFT 9u
#define CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM0_F2S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK 0x100u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_SHIFT 8u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBP_F2S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBP_F2S_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM1_MASK 0x80u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_SHIFT 7u
#define CSC0_SMU_CTRL1_CPU0_DTCM1_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM1_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM1_MASK)
#define CSC0_SMU_CTRL1_CPU0_DTCM0_MASK 0x40u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_SHIFT 6u
#define CSC0_SMU_CTRL1_CPU0_DTCM0_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DTCM0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DTCM0_SHIFT))&CSC0_SMU_CTRL1_CPU0_DTCM0_MASK)
#define CSC0_SMU_CTRL1_CPU0_ITCM_MASK 0x20u
#define CSC0_SMU_CTRL1_CPU0_ITCM_SHIFT 5u
#define CSC0_SMU_CTRL1_CPU0_ITCM_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ITCM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ITCM_SHIFT))&CSC0_SMU_CTRL1_CPU0_ITCM_MASK)
#define CSC0_SMU_CTRL1_CPU0_DCACHE_MASK 0x10u
#define CSC0_SMU_CTRL1_CPU0_DCACHE_SHIFT 4u
#define CSC0_SMU_CTRL1_CPU0_DCACHE_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_DCACHE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_DCACHE_SHIFT))&CSC0_SMU_CTRL1_CPU0_DCACHE_MASK)
#define CSC0_SMU_CTRL1_CPU0_ICACHE_MASK 0x8u
#define CSC0_SMU_CTRL1_CPU0_ICACHE_SHIFT 3u
#define CSC0_SMU_CTRL1_CPU0_ICACHE_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_ICACHE(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_ICACHE_SHIFT))&CSC0_SMU_CTRL1_CPU0_ICACHE_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBP_MASK 0x4u
#define CSC0_SMU_CTRL1_CPU0_AHBP_SHIFT 2u
#define CSC0_SMU_CTRL1_CPU0_AHBP_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBP(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBP_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBP_MASK)
#define CSC0_SMU_CTRL1_CPU0_AHBM_MASK 0x2u
#define CSC0_SMU_CTRL1_CPU0_AHBM_SHIFT 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM_WIDTH 1u
#define CSC0_SMU_CTRL1_CPU0_AHBM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_CPU0_AHBM_SHIFT))&CSC0_SMU_CTRL1_CPU0_AHBM_MASK)
#define CSC0_SMU_CTRL1_LOCK_MASK 0x1u
#define CSC0_SMU_CTRL1_LOCK_SHIFT 0u
#define CSC0_SMU_CTRL1_LOCK_WIDTH 1u
#define CSC0_SMU_CTRL1_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL1_LOCK_SHIFT))&CSC0_SMU_CTRL1_LOCK_MASK)
/* SMU_CTRL1 Reg Mask */
#define CSC0_SMU_CTRL1_MASK 0x0007F7FFu
/* SMU_CTRL4 Bit Fields */
#define CSC0_SMU_CTRL4_HSM_WDOG_MASK 0x80000000u
#define CSC0_SMU_CTRL4_HSM_WDOG_SHIFT 31u
#define CSC0_SMU_CTRL4_HSM_WDOG_WIDTH 1u
#define CSC0_SMU_CTRL4_HSM_WDOG(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_HSM_WDOG_SHIFT))&CSC0_SMU_CTRL4_HSM_WDOG_MASK)
#define CSC0_SMU_CTRL4_FMC_ERR_MASK 0x40000000u
#define CSC0_SMU_CTRL4_FMC_ERR_SHIFT 30u
#define CSC0_SMU_CTRL4_FMC_ERR_WIDTH 1u
#define CSC0_SMU_CTRL4_FMC_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FMC_ERR_SHIFT))&CSC0_SMU_CTRL4_FMC_ERR_MASK)
#define CSC0_SMU_CTRL4_ROM_S_EN_MASK 0x10000000u
#define CSC0_SMU_CTRL4_ROM_S_EN_SHIFT 28u
#define CSC0_SMU_CTRL4_ROM_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_ROM_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_ROM_S_EN_SHIFT))&CSC0_SMU_CTRL4_ROM_S_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK 0x2000000u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_SHIFT 25u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK 0x1000000u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_SHIFT 24u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM1_S_EN_MASK 0x200000u
#define CSC0_SMU_CTRL4_SRAM1_S_EN_SHIFT 21u
#define CSC0_SMU_CTRL4_SRAM1_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_S_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM1_S_EN_MASK)
#define CSC0_SMU_CTRL4_SRAM0_S_EN_MASK 0x100000u
#define CSC0_SMU_CTRL4_SRAM0_S_EN_SHIFT 20u
#define CSC0_SMU_CTRL4_SRAM0_S_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_S_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_S_EN_SHIFT))&CSC0_SMU_CTRL4_SRAM0_S_EN_MASK)
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK 0x20000u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_SHIFT 17u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S_WIDTH 1u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FLASH_ECC_EN_S_SHIFT))&CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK)
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK 0x10000u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_SHIFT 16u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_FLASH_ECC_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_FLASH_ECC_EN_SHIFT))&CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK)
#define CSC0_SMU_CTRL4_AFCB1_MON_MASK 0x8000u
#define CSC0_SMU_CTRL4_AFCB1_MON_SHIFT 15u
#define CSC0_SMU_CTRL4_AFCB1_MON_WIDTH 1u
#define CSC0_SMU_CTRL4_AFCB1_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_AFCB1_MON_SHIFT))&CSC0_SMU_CTRL4_AFCB1_MON_MASK)
#define CSC0_SMU_CTRL4_AFCB0_MON_MASK 0x4000u
#define CSC0_SMU_CTRL4_AFCB0_MON_SHIFT 14u
#define CSC0_SMU_CTRL4_AFCB0_MON_WIDTH 1u
#define CSC0_SMU_CTRL4_AFCB0_MON(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_AFCB0_MON_SHIFT))&CSC0_SMU_CTRL4_AFCB0_MON_MASK)
#define CSC0_SMU_CTRL4_SCF_RST_EN_MASK 0x2000u
#define CSC0_SMU_CTRL4_SCF_RST_EN_SHIFT 13u
#define CSC0_SMU_CTRL4_SCF_RST_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SCF_RST_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCF_RST_EN_SHIFT))&CSC0_SMU_CTRL4_SCF_RST_EN_MASK)
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK 0x1000u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_SHIFT 12u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN_WIDTH 1u
#define CSC0_SMU_CTRL4_SCF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCF_IRQ_EN_SHIFT))&CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK)
#define CSC0_SMU_CTRL4_TMU_MASK 0x400u
#define CSC0_SMU_CTRL4_TMU_SHIFT 10u
#define CSC0_SMU_CTRL4_TMU_WIDTH 1u
#define CSC0_SMU_CTRL4_TMU(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_TMU_SHIFT))&CSC0_SMU_CTRL4_TMU_MASK)
#define CSC0_SMU_CTRL4_SCM_CRC_MASK 0x200u
#define CSC0_SMU_CTRL4_SCM_CRC_SHIFT 9u
#define CSC0_SMU_CTRL4_SCM_CRC_WIDTH 1u
#define CSC0_SMU_CTRL4_SCM_CRC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCM_CRC_SHIFT))&CSC0_SMU_CTRL4_SCM_CRC_MASK)
#define CSC0_SMU_CTRL4_SCG_CRC_MASK 0x100u
#define CSC0_SMU_CTRL4_SCG_CRC_SHIFT 8u
#define CSC0_SMU_CTRL4_SCG_CRC_WIDTH 1u
#define CSC0_SMU_CTRL4_SCG_CRC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SCG_CRC_SHIFT))&CSC0_SMU_CTRL4_SCG_CRC_MASK)
#define CSC0_SMU_CTRL4_SRAM1_ECC_MASK 0x20u
#define CSC0_SMU_CTRL4_SRAM1_ECC_SHIFT 5u
#define CSC0_SMU_CTRL4_SRAM1_ECC_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM1_ECC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM1_ECC_SHIFT))&CSC0_SMU_CTRL4_SRAM1_ECC_MASK)
#define CSC0_SMU_CTRL4_SRAM0_ECC_MASK 0x10u
#define CSC0_SMU_CTRL4_SRAM0_ECC_SHIFT 4u
#define CSC0_SMU_CTRL4_SRAM0_ECC_WIDTH 1u
#define CSC0_SMU_CTRL4_SRAM0_ECC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_SRAM0_ECC_SHIFT))&CSC0_SMU_CTRL4_SRAM0_ECC_MASK)
#define CSC0_SMU_CTRL4_MAM0_ERR_MASK 0x2u
#define CSC0_SMU_CTRL4_MAM0_ERR_SHIFT 1u
#define CSC0_SMU_CTRL4_MAM0_ERR_WIDTH 1u
#define CSC0_SMU_CTRL4_MAM0_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_MAM0_ERR_SHIFT))&CSC0_SMU_CTRL4_MAM0_ERR_MASK)
#define CSC0_SMU_CTRL4_LOCK_MASK 0x1u
#define CSC0_SMU_CTRL4_LOCK_SHIFT 0u
#define CSC0_SMU_CTRL4_LOCK_WIDTH 1u
#define CSC0_SMU_CTRL4_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL4_LOCK_SHIFT))&CSC0_SMU_CTRL4_LOCK_MASK)
/* SMU_CTRL4 Reg Mask */
#define CSC0_SMU_CTRL4_MASK 0xD333F733u
/* CMU_CTRL Bit Fields */
#define CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_MASK 0x10000u
#define CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_SHIFT 16u
#define CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_WIDTH 1u
#define CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_SHIFT))&CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_MASK)
#define CSC0_CMU_CTRL_CMU3_FCSMU_RST_MASK 0x200u
#define CSC0_CMU_CTRL_CMU3_FCSMU_RST_SHIFT 9u
#define CSC0_CMU_CTRL_CMU3_FCSMU_RST_WIDTH 1u
#define CSC0_CMU_CTRL_CMU3_FCSMU_RST(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CMU_CTRL_CMU3_FCSMU_RST_SHIFT))&CSC0_CMU_CTRL_CMU3_FCSMU_RST_MASK)
#define CSC0_CMU_CTRL_CMU3_RST_EN_MASK 0x100u
#define CSC0_CMU_CTRL_CMU3_RST_EN_SHIFT 8u
#define CSC0_CMU_CTRL_CMU3_RST_EN_WIDTH 1u
#define CSC0_CMU_CTRL_CMU3_RST_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CMU_CTRL_CMU3_RST_EN_SHIFT))&CSC0_CMU_CTRL_CMU3_RST_EN_MASK)
#define CSC0_CMU_CTRL_CMU4_LOC_EN_MASK 0x20u
#define CSC0_CMU_CTRL_CMU4_LOC_EN_SHIFT 5u
#define CSC0_CMU_CTRL_CMU4_LOC_EN_WIDTH 1u
#define CSC0_CMU_CTRL_CMU4_LOC_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CMU_CTRL_CMU4_LOC_EN_SHIFT))&CSC0_CMU_CTRL_CMU4_LOC_EN_MASK)
#define CSC0_CMU_CTRL_LOCK_MASK 0x1u
#define CSC0_CMU_CTRL_LOCK_SHIFT 0u
#define CSC0_CMU_CTRL_LOCK_WIDTH 1u
#define CSC0_CMU_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_CMU_CTRL_LOCK_SHIFT))&CSC0_CMU_CTRL_LOCK_MASK)
/* CMU_CTRL Reg Mask */
#define CSC0_CMU_CTRL_MASK 0x00010321u
/* SMU_CTRL5 Bit Fields */
#define CSC0_SMU_CTRL5_SRAM1_EDC_MASK 0x20000000u
#define CSC0_SMU_CTRL5_SRAM1_EDC_SHIFT 29u
#define CSC0_SMU_CTRL5_SRAM1_EDC_WIDTH 1u
#define CSC0_SMU_CTRL5_SRAM1_EDC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_SRAM1_EDC_SHIFT))&CSC0_SMU_CTRL5_SRAM1_EDC_MASK)
#define CSC0_SMU_CTRL5_SRAM0_EDC_MASK 0x10000000u
#define CSC0_SMU_CTRL5_SRAM0_EDC_SHIFT 28u
#define CSC0_SMU_CTRL5_SRAM0_EDC_WIDTH 1u
#define CSC0_SMU_CTRL5_SRAM0_EDC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_SRAM0_EDC_SHIFT))&CSC0_SMU_CTRL5_SRAM0_EDC_MASK)
#define CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_MASK 0x2000000u
#define CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_SHIFT 25u
#define CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_WIDTH 1u
#define CSC0_SMU_CTRL5_FLASH_EDC_P1_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_SHIFT))&CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_MASK)
#define CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_MASK 0x1000000u
#define CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_SHIFT 24u
#define CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_WIDTH 1u
#define CSC0_SMU_CTRL5_FLASH_EDC_P0_EN(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_SHIFT))&CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_MASK)
#define CSC0_SMU_CTRL5_HSM_IRAM_S_MASK 0x800000u
#define CSC0_SMU_CTRL5_HSM_IRAM_S_SHIFT 23u
#define CSC0_SMU_CTRL5_HSM_IRAM_S_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_IRAM_S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_IRAM_S_SHIFT))&CSC0_SMU_CTRL5_HSM_IRAM_S_MASK)
#define CSC0_SMU_CTRL5_HSM_DRAM_S_MASK 0x400000u
#define CSC0_SMU_CTRL5_HSM_DRAM_S_SHIFT 22u
#define CSC0_SMU_CTRL5_HSM_DRAM_S_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_DRAM_S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_DRAM_S_SHIFT))&CSC0_SMU_CTRL5_HSM_DRAM_S_MASK)
#define CSC0_SMU_CTRL5_HSM_IRAM_MASK 0x200000u
#define CSC0_SMU_CTRL5_HSM_IRAM_SHIFT 21u
#define CSC0_SMU_CTRL5_HSM_IRAM_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_IRAM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_IRAM_SHIFT))&CSC0_SMU_CTRL5_HSM_IRAM_MASK)
#define CSC0_SMU_CTRL5_HSM_DRAM_MASK 0x100000u
#define CSC0_SMU_CTRL5_HSM_DRAM_SHIFT 20u
#define CSC0_SMU_CTRL5_HSM_DRAM_WIDTH 1u
#define CSC0_SMU_CTRL5_HSM_DRAM(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_HSM_DRAM_SHIFT))&CSC0_SMU_CTRL5_HSM_DRAM_MASK)
#define CSC0_SMU_CTRL5_DMA0_ECC_S_MASK 0x10000u
#define CSC0_SMU_CTRL5_DMA0_ECC_S_SHIFT 16u
#define CSC0_SMU_CTRL5_DMA0_ECC_S_WIDTH 1u
#define CSC0_SMU_CTRL5_DMA0_ECC_S(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_ECC_S_SHIFT))&CSC0_SMU_CTRL5_DMA0_ECC_S_MASK)
#define CSC0_SMU_CTRL5_DMA0_ECC_MASK 0x4000u
#define CSC0_SMU_CTRL5_DMA0_ECC_SHIFT 14u
#define CSC0_SMU_CTRL5_DMA0_ECC_WIDTH 1u
#define CSC0_SMU_CTRL5_DMA0_ECC(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_ECC_SHIFT))&CSC0_SMU_CTRL5_DMA0_ECC_MASK)
#define CSC0_SMU_CTRL5_DMA0_LOCKSTEP_MASK 0x1000u
#define CSC0_SMU_CTRL5_DMA0_LOCKSTEP_SHIFT 12u
#define CSC0_SMU_CTRL5_DMA0_LOCKSTEP_WIDTH 1u
#define CSC0_SMU_CTRL5_DMA0_LOCKSTEP(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_DMA0_LOCKSTEP_SHIFT))&CSC0_SMU_CTRL5_DMA0_LOCKSTEP_MASK)
#define CSC0_SMU_CTRL5_FOSC_ERR_MASK 0x400u
#define CSC0_SMU_CTRL5_FOSC_ERR_SHIFT 10u
#define CSC0_SMU_CTRL5_FOSC_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_FOSC_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_FOSC_ERR_SHIFT))&CSC0_SMU_CTRL5_FOSC_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL1_ERR_MASK 0x200u
#define CSC0_SMU_CTRL5_PLL1_ERR_SHIFT 9u
#define CSC0_SMU_CTRL5_PLL1_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL1_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL1_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL1_ERR_MASK)
#define CSC0_SMU_CTRL5_PLL0_ERR_MASK 0x100u
#define CSC0_SMU_CTRL5_PLL0_ERR_SHIFT 8u
#define CSC0_SMU_CTRL5_PLL0_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_PLL0_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_PLL0_ERR_SHIFT))&CSC0_SMU_CTRL5_PLL0_ERR_MASK)
#define CSC0_SMU_CTRL5_STCU_ERR_MASK 0x10u
#define CSC0_SMU_CTRL5_STCU_ERR_SHIFT 4u
#define CSC0_SMU_CTRL5_STCU_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_STCU_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_STCU_ERR_SHIFT))&CSC0_SMU_CTRL5_STCU_ERR_MASK)
#define CSC0_SMU_CTRL5_NONUSER_ERR_MASK 0x4u
#define CSC0_SMU_CTRL5_NONUSER_ERR_SHIFT 2u
#define CSC0_SMU_CTRL5_NONUSER_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_NONUSER_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_NONUSER_ERR_SHIFT))&CSC0_SMU_CTRL5_NONUSER_ERR_MASK)
#define CSC0_SMU_CTRL5_NVR_ERR_MASK 0x2u
#define CSC0_SMU_CTRL5_NVR_ERR_SHIFT 1u
#define CSC0_SMU_CTRL5_NVR_ERR_WIDTH 1u
#define CSC0_SMU_CTRL5_NVR_ERR(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_NVR_ERR_SHIFT))&CSC0_SMU_CTRL5_NVR_ERR_MASK)
#define CSC0_SMU_CTRL5_LOCK_MASK 0x1u
#define CSC0_SMU_CTRL5_LOCK_SHIFT 0u
#define CSC0_SMU_CTRL5_LOCK_WIDTH 1u
#define CSC0_SMU_CTRL5_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_SMU_CTRL5_LOCK_SHIFT))&CSC0_SMU_CTRL5_LOCK_MASK)
/* SMU_CTRL5 Reg Mask */
#define CSC0_SMU_CTRL5_MASK 0x33F15717u
/* LP_WAKEUP Bit Fields */
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_MASK 0xF0000000u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_SHIFT 28u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_WIDTH 4u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG0(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_SHIFT))&CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_MASK)
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG1_MASK 0xF000000u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG1_SHIFT 24u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG1_WIDTH 4u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG1(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP_WAKEUP_CFG1_SHIFT))&CSC0_LP_WAKEUP_LP_WAKEUP_CFG1_MASK)
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG2_MASK 0xF00000u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG2_SHIFT 20u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG2_WIDTH 4u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG2(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP_WAKEUP_CFG2_SHIFT))&CSC0_LP_WAKEUP_LP_WAKEUP_CFG2_MASK)
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG3_MASK 0xF0000u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG3_SHIFT 16u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG3_WIDTH 4u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG3(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP_WAKEUP_CFG3_SHIFT))&CSC0_LP_WAKEUP_LP_WAKEUP_CFG3_MASK)
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG4_MASK 0xF000u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG4_SHIFT 12u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG4_WIDTH 4u
#define CSC0_LP_WAKEUP_LP_WAKEUP_CFG4(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP_WAKEUP_CFG4_SHIFT))&CSC0_LP_WAKEUP_LP_WAKEUP_CFG4_MASK)
#define CSC0_LP_WAKEUP_LP0_POL_MASK 0x80u
#define CSC0_LP_WAKEUP_LP0_POL_SHIFT 7u
#define CSC0_LP_WAKEUP_LP0_POL_WIDTH 1u
#define CSC0_LP_WAKEUP_LP0_POL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP0_POL_SHIFT))&CSC0_LP_WAKEUP_LP0_POL_MASK)
#define CSC0_LP_WAKEUP_LP1_POL_MASK 0x40u
#define CSC0_LP_WAKEUP_LP1_POL_SHIFT 6u
#define CSC0_LP_WAKEUP_LP1_POL_WIDTH 1u
#define CSC0_LP_WAKEUP_LP1_POL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP1_POL_SHIFT))&CSC0_LP_WAKEUP_LP1_POL_MASK)
#define CSC0_LP_WAKEUP_LP2_POL_MASK 0x20u
#define CSC0_LP_WAKEUP_LP2_POL_SHIFT 5u
#define CSC0_LP_WAKEUP_LP2_POL_WIDTH 1u
#define CSC0_LP_WAKEUP_LP2_POL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP2_POL_SHIFT))&CSC0_LP_WAKEUP_LP2_POL_MASK)
#define CSC0_LP_WAKEUP_LP3_POL_MASK 0x10u
#define CSC0_LP_WAKEUP_LP3_POL_SHIFT 4u
#define CSC0_LP_WAKEUP_LP3_POL_WIDTH 1u
#define CSC0_LP_WAKEUP_LP3_POL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP3_POL_SHIFT))&CSC0_LP_WAKEUP_LP3_POL_MASK)
#define CSC0_LP_WAKEUP_LP4_POL_MASK 0x8u
#define CSC0_LP_WAKEUP_LP4_POL_SHIFT 3u
#define CSC0_LP_WAKEUP_LP4_POL_WIDTH 1u
#define CSC0_LP_WAKEUP_LP4_POL(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LP4_POL_SHIFT))&CSC0_LP_WAKEUP_LP4_POL_MASK)
#define CSC0_LP_WAKEUP_LOCK_MASK 0x1u
#define CSC0_LP_WAKEUP_LOCK_SHIFT 0u
#define CSC0_LP_WAKEUP_LOCK_WIDTH 1u
#define CSC0_LP_WAKEUP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<CSC0_LP_WAKEUP_LOCK_SHIFT))&CSC0_LP_WAKEUP_LOCK_MASK)
/* LP_WAKEUP Reg Mask */
#define CSC0_LP_WAKEUP_MASK 0xFFFFF0F9u
/*!
* @}
*/ /* end of group CSC0_Register_Masks */
/*!
* @}
*/ /* end of group CSC0_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif
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