140 lines
6.0 KiB
C
140 lines
6.0 KiB
C
#ifndef DRIVER_CRC_H
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#define DRIVER_CRC_H
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/* ----------------------------------------------------------------------------
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-- CRC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
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* @{
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*/
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/** CRC - Size of Registers Arrays */
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/** CRC - Register Layout Typedef */
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typedef struct {
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union {
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__IO uint32_t uDATA; /** CRC Data union */
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struct {
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__IO uint16_t L; /** CRC_DATAL register., offset: 0x0 */
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__IO uint16_t H; /** CRC_DATAH register., offset: 0x2 */
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} tDATA_16;
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struct {
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__IO uint8_t LL; /** CRC_DATALL register., offset: 0x0 */
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__IO uint8_t LU; /** CRC_DATALU register., offset: 0x1 */
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__IO uint8_t HL; /** CRC_DATAHL register., offset: 0x2 */
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__IO uint8_t HU; /** CRC_DATAHU register., offset: 0x3 */
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} tDATA_8;
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} DATA;
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__IO uint32_t POLY ; /* CRC Polynomial Register, offset: 0x4 */
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__IO uint32_t CR ; /* CRC Control Register, offset: 0x8 */
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__IO uint32_t SDAT ; /* CRC Data Bit Swap Register, offset: 0xC */
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} CRC_Type, *CRC_MemMapPtr;
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/** Number of instances of the CRC module. */
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#define CRC_INSTANCE_COUNT (1u)
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/* CRC - Peripheral instance base addresses */
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/** Peripheral CRC base address */
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#define CRC_BASE (0x4002a000u)
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/** Peripheral CRC base pointer */
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#define CRC ((CRC_Type *)CRC_BASE)
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/** Array initializer of CRC peripheral base addresses */
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#define CRC_BASE_ADDRS {CRC_BASE}
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/** Array initializer of CRC peripheral base pointers */
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#define CRC_BASE_PTRS {CRC}
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/* ----------------------------------------------------------------------------
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-- CRC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CRC_Register_Masks CRC Register Masks
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* @{
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*/
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/* DATA Bit Fields */
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#define CRC_DATA_HU_MASK 0xFF000000u
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#define CRC_DATA_HU_SHIFT 24u
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#define CRC_DATA_HU_WIDTH 8u
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#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
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#define CRC_DATA_HL_MASK 0xFF0000u
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#define CRC_DATA_HL_SHIFT 16u
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#define CRC_DATA_HL_WIDTH 8u
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#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
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#define CRC_DATA_LU_MASK 0xFF00u
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#define CRC_DATA_LU_SHIFT 8u
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#define CRC_DATA_LU_WIDTH 8u
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#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
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#define CRC_DATA_LL_MASK 0xFFu
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#define CRC_DATA_LL_SHIFT 0u
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#define CRC_DATA_LL_WIDTH 8u
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#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
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/* DATA Reg Mask */
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#define CRC_DATA_MASK 0xFFFFFFFFu
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/* POLY Bit Fields */
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#define CRC_POLY_HIGH_MASK 0xFFFF0000u
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#define CRC_POLY_HIGH_SHIFT 16u
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#define CRC_POLY_HIGH_WIDTH 16u
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#define CRC_POLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_HIGH_SHIFT))&CRC_POLY_HIGH_MASK)
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#define CRC_POLY_LOW_MASK 0xFFFFu
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#define CRC_POLY_LOW_SHIFT 0u
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#define CRC_POLY_LOW_WIDTH 16u
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#define CRC_POLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_LOW_SHIFT))&CRC_POLY_LOW_MASK)
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/* POLY Reg Mask */
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#define CRC_POLY_MASK 0xFFFFFFFFu
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/* CR Bit Fields */
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#define CRC_CR_DSW_MASK 0xC0000000u
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#define CRC_CR_DSW_SHIFT 30u
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#define CRC_CR_DSW_WIDTH 2u
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#define CRC_CR_DSW(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSW_SHIFT))&CRC_CR_DSW_MASK)
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#define CRC_CR_DSR_MASK 0x30000000u
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#define CRC_CR_DSR_SHIFT 28u
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#define CRC_CR_DSR_WIDTH 2u
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#define CRC_CR_DSR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSR_SHIFT))&CRC_CR_DSR_MASK)
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#define CRC_CR_TCRC8_MASK 0x8000000u
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#define CRC_CR_TCRC8_SHIFT 27u
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#define CRC_CR_TCRC8_WIDTH 1u
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#define CRC_CR_TCRC8(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC8_SHIFT))&CRC_CR_TCRC8_MASK)
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#define CRC_CR_FXOR_MASK 0x4000000u
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#define CRC_CR_FXOR_SHIFT 26u
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#define CRC_CR_FXOR_WIDTH 1u
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#define CRC_CR_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_FXOR_SHIFT))&CRC_CR_FXOR_MASK)
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#define CRC_CR_WAS_MASK 0x2000000u
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#define CRC_CR_WAS_SHIFT 25u
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#define CRC_CR_WAS_WIDTH 1u
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#define CRC_CR_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_WAS_SHIFT))&CRC_CR_WAS_MASK)
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#define CRC_CR_TCRC_MASK 0x1000000u
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#define CRC_CR_TCRC_SHIFT 24u
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#define CRC_CR_TCRC_WIDTH 1u
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#define CRC_CR_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC_SHIFT))&CRC_CR_TCRC_MASK)
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/* CR Reg Mask */
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#define CRC_CR_MASK 0xFF000000u
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/* SDAT Bit Fields */
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#define CRC_SDAT_HIGH_MASK 0xFFFF0000u
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#define CRC_SDAT_HIGH_SHIFT 16u
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#define CRC_SDAT_HIGH_WIDTH 16u
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#define CRC_SDAT_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_HIGH_SHIFT))&CRC_SDAT_HIGH_MASK)
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#define CRC_SDAT_LOW_MASK 0xFFFFu
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#define CRC_SDAT_LOW_SHIFT 0u
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#define CRC_SDAT_LOW_WIDTH 16u
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#define CRC_SDAT_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_LOW_SHIFT))&CRC_SDAT_LOW_MASK)
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/* SDAT Reg Mask */
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#define CRC_SDAT_MASK 0xFFFFFFFFu
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/*!
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* @}
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*/ /* end of group CRC_Register_Masks */
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/*!
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* @}
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*/ /* end of group CRC_Peripheral_Access_Layer */
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#endif
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