355 lines
8.7 KiB
C
355 lines
8.7 KiB
C
#ifndef _FC7240_CPM_NU_Tztufn6_REGS_H_
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#define _FC7240_CPM_NU_Tztufn6_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- CPM Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CPM_Peripheral_Access_Layer CPM Peripheral Access Layer
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* @{
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*/
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/** CPM - Size of Registers Arrays */
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/** CPM - Register Layout Typedef */
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typedef struct {
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__IO uint32_t FISCR ; /* FPU Interrupt Status and Control Register, offset: 0x0 */
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__IO uint32_t MISCR ; /* Miscellaneous Control Register, offset: 0x4 */
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uint8_t RESERVED_0[24];
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__IO uint32_t TCMRCR ; /* TCM Retry Control Register, offset: 0x20 */
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} CPM_Type, *CPM_MemMapPtr;
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/** Number of instances of the CPM module. */
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#define CPM_INSTANCE_COUNT (1u)
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/* CPM - Peripheral instance base addresses */
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/** Peripheral CPM base address */
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#define CPM_BASE (0xE0080000u)
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/** Peripheral CPM base pointer */
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#define CPM ((CPM_Type *)CPM_BASE)
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/** Array initializer of CPM peripheral base addresses */
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#define CPM_BASE_ADDRS {CPM_BASE}
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/** Array initializer of CPM peripheral base pointers */
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#define CPM_BASE_PTRS {CPM}
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// need fill by yourself
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///** Number of interrupt vector arrays for the CPM module. */
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//#define CPM_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the CPM module. */
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//#define CPM_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the CPM peripheral type */
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//#define CPM_IRQS {CPM_IRQn}
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/* ----------------------------------------------------------------------------
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-- CPM Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CPM_Register_Masks CPM Register Masks
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* @{
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*/
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/* FISCR Bit Fields */
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#define CPM_FISCR_FIXCE_MASK 0x200000u
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#define CPM_FISCR_FIXCE_SHIFT 21u
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#define CPM_FISCR_FIXCE_WIDTH 1u
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#define CPM_FISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXCE_SHIFT))&CPM_FISCR_FIXCE_MASK)
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#define CPM_FISCR_FIDCE_MASK 0x100000u
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#define CPM_FISCR_FIDCE_SHIFT 20u
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#define CPM_FISCR_FIDCE_WIDTH 1u
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#define CPM_FISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDCE_SHIFT))&CPM_FISCR_FIDCE_MASK)
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#define CPM_FISCR_FOFCE_MASK 0x80000u
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#define CPM_FISCR_FOFCE_SHIFT 19u
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#define CPM_FISCR_FOFCE_WIDTH 1u
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#define CPM_FISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFCE_SHIFT))&CPM_FISCR_FOFCE_MASK)
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#define CPM_FISCR_FUFCE_MASK 0x40000u
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#define CPM_FISCR_FUFCE_SHIFT 18u
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#define CPM_FISCR_FUFCE_WIDTH 1u
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#define CPM_FISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFCE_SHIFT))&CPM_FISCR_FUFCE_MASK)
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#define CPM_FISCR_FDZCE_MASK 0x20000u
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#define CPM_FISCR_FDZCE_SHIFT 17u
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#define CPM_FISCR_FDZCE_WIDTH 1u
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#define CPM_FISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZCE_SHIFT))&CPM_FISCR_FDZCE_MASK)
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#define CPM_FISCR_FIOCE_MASK 0x10000u
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#define CPM_FISCR_FIOCE_SHIFT 16u
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#define CPM_FISCR_FIOCE_WIDTH 1u
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#define CPM_FISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOCE_SHIFT))&CPM_FISCR_FIOCE_MASK)
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#define CPM_FISCR_FIXC_MASK 0x20u
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#define CPM_FISCR_FIXC_SHIFT 5u
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#define CPM_FISCR_FIXC_WIDTH 1u
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#define CPM_FISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXC_SHIFT))&CPM_FISCR_FIXC_MASK)
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#define CPM_FISCR_FIDC_MASK 0x10u
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#define CPM_FISCR_FIDC_SHIFT 4u
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#define CPM_FISCR_FIDC_WIDTH 1u
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#define CPM_FISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDC_SHIFT))&CPM_FISCR_FIDC_MASK)
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#define CPM_FISCR_FOFC_MASK 0x8u
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#define CPM_FISCR_FOFC_SHIFT 3u
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#define CPM_FISCR_FOFC_WIDTH 1u
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#define CPM_FISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFC_SHIFT))&CPM_FISCR_FOFC_MASK)
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#define CPM_FISCR_FUFC_MASK 0x4u
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#define CPM_FISCR_FUFC_SHIFT 2u
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#define CPM_FISCR_FUFC_WIDTH 1u
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#define CPM_FISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFC_SHIFT))&CPM_FISCR_FUFC_MASK)
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#define CPM_FISCR_FDZC_MASK 0x2u
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#define CPM_FISCR_FDZC_SHIFT 1u
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#define CPM_FISCR_FDZC_WIDTH 1u
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#define CPM_FISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZC_SHIFT))&CPM_FISCR_FDZC_MASK)
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#define CPM_FISCR_FIOC_MASK 0x1u
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#define CPM_FISCR_FIOC_SHIFT 0u
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#define CPM_FISCR_FIOC_WIDTH 1u
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#define CPM_FISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOC_SHIFT))&CPM_FISCR_FIOC_MASK)
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/* FISCR Reg Mask */
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#define CPM_FISCR_MASK 0x003F003Fu
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/* MISCR Bit Fields */
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#define CPM_MISCR_AHBS_PRIORITY_MASK 0x1u
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#define CPM_MISCR_AHBS_PRIORITY_SHIFT 0u
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#define CPM_MISCR_AHBS_PRIORITY_WIDTH 1u
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#define CPM_MISCR_AHBS_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<<CPM_MISCR_AHBS_PRIORITY_SHIFT))&CPM_MISCR_AHBS_PRIORITY_MASK)
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/* MISCR Reg Mask */
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#define CPM_MISCR_MASK 0x00000001u
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/* TCMRCR Bit Fields */
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#define CPM_TCMRCR_D1RBCLR_MASK 0x4000u
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#define CPM_TCMRCR_D1RBCLR_SHIFT 14u
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#define CPM_TCMRCR_D1RBCLR_WIDTH 1u
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#define CPM_TCMRCR_D1RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBCLR_SHIFT))&CPM_TCMRCR_D1RBCLR_MASK)
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#define CPM_TCMRCR_D0RBCLR_MASK 0x2000u
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#define CPM_TCMRCR_D0RBCLR_SHIFT 13u
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#define CPM_TCMRCR_D0RBCLR_WIDTH 1u
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#define CPM_TCMRCR_D0RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBCLR_SHIFT))&CPM_TCMRCR_D0RBCLR_MASK)
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#define CPM_TCMRCR_IRBCLR_MASK 0x1000u
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#define CPM_TCMRCR_IRBCLR_SHIFT 12u
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#define CPM_TCMRCR_IRBCLR_WIDTH 1u
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#define CPM_TCMRCR_IRBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBCLR_SHIFT))&CPM_TCMRCR_IRBCLR_MASK)
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#define CPM_TCMRCR_D1RBVLD_MASK 0x400u
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#define CPM_TCMRCR_D1RBVLD_SHIFT 10u
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#define CPM_TCMRCR_D1RBVLD_WIDTH 1u
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#define CPM_TCMRCR_D1RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBVLD_SHIFT))&CPM_TCMRCR_D1RBVLD_MASK)
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#define CPM_TCMRCR_D0RBVLD_MASK 0x200u
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#define CPM_TCMRCR_D0RBVLD_SHIFT 9u
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#define CPM_TCMRCR_D0RBVLD_WIDTH 1u
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#define CPM_TCMRCR_D0RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBVLD_SHIFT))&CPM_TCMRCR_D0RBVLD_MASK)
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#define CPM_TCMRCR_IRBVLD_MASK 0x100u
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#define CPM_TCMRCR_IRBVLD_SHIFT 8u
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#define CPM_TCMRCR_IRBVLD_WIDTH 1u
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#define CPM_TCMRCR_IRBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBVLD_SHIFT))&CPM_TCMRCR_IRBVLD_MASK)
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#define CPM_TCMRCR_D1RBIE_MASK 0x40u
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#define CPM_TCMRCR_D1RBIE_SHIFT 6u
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#define CPM_TCMRCR_D1RBIE_WIDTH 1u
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#define CPM_TCMRCR_D1RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBIE_SHIFT))&CPM_TCMRCR_D1RBIE_MASK)
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#define CPM_TCMRCR_D0RBIE_MASK 0x20u
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#define CPM_TCMRCR_D0RBIE_SHIFT 5u
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#define CPM_TCMRCR_D0RBIE_WIDTH 1u
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#define CPM_TCMRCR_D0RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBIE_SHIFT))&CPM_TCMRCR_D0RBIE_MASK)
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#define CPM_TCMRCR_IRBIE_MASK 0x10u
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#define CPM_TCMRCR_IRBIE_SHIFT 4u
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#define CPM_TCMRCR_IRBIE_WIDTH 1u
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#define CPM_TCMRCR_IRBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBIE_SHIFT))&CPM_TCMRCR_IRBIE_MASK)
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#define CPM_TCMRCR_D1RBAC_MASK 0x4u
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#define CPM_TCMRCR_D1RBAC_SHIFT 2u
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#define CPM_TCMRCR_D1RBAC_WIDTH 1u
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#define CPM_TCMRCR_D1RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBAC_SHIFT))&CPM_TCMRCR_D1RBAC_MASK)
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#define CPM_TCMRCR_D0RBAC_MASK 0x2u
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#define CPM_TCMRCR_D0RBAC_SHIFT 1u
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#define CPM_TCMRCR_D0RBAC_WIDTH 1u
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#define CPM_TCMRCR_D0RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBAC_SHIFT))&CPM_TCMRCR_D0RBAC_MASK)
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#define CPM_TCMRCR_IRBAC_MASK 0x1u
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#define CPM_TCMRCR_IRBAC_SHIFT 0u
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#define CPM_TCMRCR_IRBAC_WIDTH 1u
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#define CPM_TCMRCR_IRBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBAC_SHIFT))&CPM_TCMRCR_IRBAC_MASK)
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/* TCMRCR Reg Mask */
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#define CPM_TCMRCR_MASK 0x00007777u
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/*!
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* @}
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*/ /* end of group CPM_Register_Masks */
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/*!
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* @}
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*/ /* end of group CPM_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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