352 lines
7.9 KiB
C
352 lines
7.9 KiB
C
#ifndef _FC7240_CMU_NU_Tztufn2_REGS_H_
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#define _FC7240_CMU_NU_Tztufn2_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- CMU Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CMU_Peripheral_Access_Layer CMU Peripheral Access Layer
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* @{
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*/
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/** CMU - Size of Registers Arrays */
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/** CMU - Register Layout Typedef */
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typedef struct {
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uint8_t RESERVED_0[8];
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__IO uint32_t CTRL ; /* Control Register, offset: 0x8 */
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uint8_t RESERVED_1[4];
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__IO uint32_t MIN ; /* Minimum Threshold Register, offset: 0x10 */
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__IO uint32_t MAX ; /* Maximum Threshold Register, offset: 0x14 */
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__IO uint32_t REF_WINDOW ; /* Reference Window Register, offset: 0x18 */
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__I uint32_t MON_CNT ; /* Monitor Counter Register, offset: 0x1C */
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__IO uint32_t ST ; /* Status Register, offset: 0x20 */
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__IO uint32_t PERIOD ; /* Period Monitor Mode Configuration Register, offset: 0x24 */
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} CMU_Type, *CMU_MemMapPtr;
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/** Number of instances of the CMU module. */
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#define CMU_INSTANCE_COUNT (5u)
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/* CMU - Peripheral instance base addresses */
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/** Peripheral CMU0 base address */
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#define CMU0_BASE (0x40031000u)
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/** Peripheral CMU0 base pointer */
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#define CMU0 ((CMU_Type *)CMU0_BASE)
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/** Peripheral CMU1 base address */
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#define CMU1_BASE (0x40032000u)
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/** Peripheral CMU1 base pointer */
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#define CMU1 ((CMU_Type *)CMU1_BASE)
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/** Peripheral CMU2 base address */
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#define CMU2_BASE (0x40033000u)
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/** Peripheral CMU2 base pointer */
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#define CMU2 ((CMU_Type *)CMU2_BASE)
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/** Peripheral CMU3 base address */
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#define CMU3_BASE (0x40034000u)
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/** Peripheral CMU3 base pointer */
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#define CMU3 ((CMU_Type *)CMU3_BASE)
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/** Peripheral CMU4 base address */
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#define CMU4_BASE (0x40035000u)
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/** Peripheral CMU4 base pointer */
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#define CMU4 ((CMU_Type *)CMU4_BASE)
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/** Array initializer of CMU peripheral base addresses */
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#define CMU_BASE_ADDRS {CMU0_BASE, CMU1_BASE, CMU2_BASE, CMU3_BASE, CMU4_BASE}
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/** Array initializer of CMU peripheral base pointers */
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#define CMU_BASE_PTRS {CMU0, CMU1, CMU2, CMU3, CMU4}
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// need fill by yourself
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///** Number of interrupt vector arrays for the CMU module. */
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//#define CMU_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the CMU module. */
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//#define CMU_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the CMU peripheral type */
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//#define CMU_IRQS {CMU0_IRQn, CMU1_IRQn, CMU2_IRQn, CMU3_IRQn, CMU4_IRQn}
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/* ----------------------------------------------------------------------------
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-- CMU Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CMU_Register_Masks CMU Register Masks
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* @{
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*/
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/* CTRL Bit Fields */
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#define CMU_CTRL_REF_DIV_MASK 0x70000u
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#define CMU_CTRL_REF_DIV_SHIFT 16u
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#define CMU_CTRL_REF_DIV_WIDTH 3u
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#define CMU_CTRL_REF_DIV(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_REF_DIV_SHIFT))&CMU_CTRL_REF_DIV_MASK)
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#define CMU_CTRL_IRQ_EN_MASK 0x40u
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#define CMU_CTRL_IRQ_EN_SHIFT 6u
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#define CMU_CTRL_IRQ_EN_WIDTH 1u
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#define CMU_CTRL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_IRQ_EN_SHIFT))&CMU_CTRL_IRQ_EN_MASK)
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#define CMU_CTRL_RESTART_EN_MASK 0x20u
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#define CMU_CTRL_RESTART_EN_SHIFT 5u
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#define CMU_CTRL_RESTART_EN_WIDTH 1u
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#define CMU_CTRL_RESTART_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_RESTART_EN_SHIFT))&CMU_CTRL_RESTART_EN_MASK)
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#define CMU_CTRL_LP_EN_MASK 0x10u
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#define CMU_CTRL_LP_EN_SHIFT 4u
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#define CMU_CTRL_LP_EN_WIDTH 1u
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#define CMU_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_LP_EN_SHIFT))&CMU_CTRL_LP_EN_MASK)
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#define CMU_CTRL_STOP_EN_MASK 0x8u
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#define CMU_CTRL_STOP_EN_SHIFT 3u
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#define CMU_CTRL_STOP_EN_WIDTH 1u
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#define CMU_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_STOP_EN_SHIFT))&CMU_CTRL_STOP_EN_MASK)
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#define CMU_CTRL_SW_RST_MASK 0x2u
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#define CMU_CTRL_SW_RST_SHIFT 1u
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#define CMU_CTRL_SW_RST_WIDTH 1u
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#define CMU_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_SW_RST_SHIFT))&CMU_CTRL_SW_RST_MASK)
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#define CMU_CTRL_ENABLE_MASK 0x1u
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#define CMU_CTRL_ENABLE_SHIFT 0u
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#define CMU_CTRL_ENABLE_WIDTH 1u
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#define CMU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_ENABLE_SHIFT))&CMU_CTRL_ENABLE_MASK)
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/* CTRL Reg Mask */
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#define CMU_CTRL_MASK 0x0007007Bu
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/* MIN Bit Fields */
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#define CMU_MIN_MIN_MASK 0xFFFFFFu
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#define CMU_MIN_MIN_SHIFT 0u
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#define CMU_MIN_MIN_WIDTH 24u
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#define CMU_MIN_MIN(x) (((uint32_t)(((uint32_t)(x))<<CMU_MIN_MIN_SHIFT))&CMU_MIN_MIN_MASK)
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/* MIN Reg Mask */
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#define CMU_MIN_MASK 0x00FFFFFFu
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/* MAX Bit Fields */
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#define CMU_MAX_MAX_MASK 0xFFFFFFu
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#define CMU_MAX_MAX_SHIFT 0u
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#define CMU_MAX_MAX_WIDTH 24u
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#define CMU_MAX_MAX(x) (((uint32_t)(((uint32_t)(x))<<CMU_MAX_MAX_SHIFT))&CMU_MAX_MAX_MASK)
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/* MAX Reg Mask */
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#define CMU_MAX_MASK 0x00FFFFFFu
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/* REF_WINDOW Bit Fields */
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#define CMU_REF_WINDOW_REF_WINDOW_MASK 0xFFFFFFu
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#define CMU_REF_WINDOW_REF_WINDOW_SHIFT 0u
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#define CMU_REF_WINDOW_REF_WINDOW_WIDTH 24u
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#define CMU_REF_WINDOW_REF_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_REF_WINDOW_REF_WINDOW_SHIFT))&CMU_REF_WINDOW_REF_WINDOW_MASK)
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/* REF_WINDOW Reg Mask */
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#define CMU_REF_WINDOW_MASK 0x00FFFFFFu
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/* MON_CNT Bit Fields */
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#define CMU_MON_CNT_MON_CNT_MASK 0xFFFFFFu
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#define CMU_MON_CNT_MON_CNT_SHIFT 0u
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#define CMU_MON_CNT_MON_CNT_WIDTH 24u
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#define CMU_MON_CNT_MON_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMU_MON_CNT_MON_CNT_SHIFT))&CMU_MON_CNT_MON_CNT_MASK)
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/* MON_CNT Reg Mask */
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#define CMU_MON_CNT_MASK 0x00FFFFFFu
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/* ST Bit Fields */
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#define CMU_ST_LOC_MASK 0x8000u
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#define CMU_ST_LOC_SHIFT 15u
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#define CMU_ST_LOC_WIDTH 1u
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#define CMU_ST_LOC(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_LOC_SHIFT))&CMU_ST_LOC_MASK)
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#define CMU_ST_MIS_MASK 0x100u
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#define CMU_ST_MIS_SHIFT 8u
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#define CMU_ST_MIS_WIDTH 1u
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#define CMU_ST_MIS(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_MIS_SHIFT))&CMU_ST_MIS_MASK)
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/* ST Reg Mask */
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#define CMU_ST_MASK 0x00008100u
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/* PERIOD Bit Fields */
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#define CMU_PERIOD_WINDOW_MASK 0xF0000u
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#define CMU_PERIOD_WINDOW_SHIFT 16u
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#define CMU_PERIOD_WINDOW_WIDTH 4u
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#define CMU_PERIOD_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_WINDOW_SHIFT))&CMU_PERIOD_WINDOW_MASK)
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#define CMU_PERIOD_EN_MASK 0x1u
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#define CMU_PERIOD_EN_SHIFT 0u
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#define CMU_PERIOD_EN_WIDTH 1u
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#define CMU_PERIOD_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_EN_SHIFT))&CMU_PERIOD_EN_MASK)
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/* PERIOD Reg Mask */
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#define CMU_PERIOD_MASK 0x000F0001u
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/*!
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* @}
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*/ /* end of group CMU_Register_Masks */
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/*!
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* @}
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*/ /* end of group CMU_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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