130 lines
4.2 KiB
C
130 lines
4.2 KiB
C
//
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// Created by cfif on 07.09.22.
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//
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#include <SystemDelayInterface.h>
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#include "AdcFlagchip.h"
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#define VREF 5.0F
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static const uint8_t DUMMY_BYTE = 0xFF;
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void Get_ADC_Result(tAdcFlagchip *env) {
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osMessageQueuePut(env->txAccessQueue, &DUMMY_BYTE, 0, 0);
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}
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tAdcFlagchip ADC_Initial(
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ADC_InstanceType ADCx, // ADC_INSTANCE_0, ADC_INSTANCE_1
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PCC_ClkSrcType adcClock, // PCC_CLK_ADC0, PCC_CLK_ADC1
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DMA_ChannelType ADC_DMA_CHANNEL, // DMA_CHANNEL_0 .. DMA_CHANNEL_15
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IRQn_Type IRQ_DMA,
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uint8_t IRQ_DMA_PRIORITY,
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uint8_t IRQ_DMA_CHANNEL_PRIORITY,
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const uint32_t *DMA_BUF,
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uint8_t num_aChannels,
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ADC_ChannelCfgType *s_aChannels,
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int32_t offset,
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double mux,
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double div,
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ADC_ConvCompleteCallbackType Bsp_ADC_HandleResult
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) {
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PCC_CtrlType bSP_PCC_Config;
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bSP_PCC_Config.eClockName = adcClock;
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bSP_PCC_Config.bEn = TRUE;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1;
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PCC_SetPcc(&bSP_PCC_Config);
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tAdcFlagchip adc = {
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.ADCx = ADCx,
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.DMA_BUF = DMA_BUF,
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.offset = offset,
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.div = div,
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.mux = mux,
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.num_aChannels = num_aChannels,
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.txAccessQueue = osMessageQueueNew(1, 1, NULL),
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.s_tAdcInitCfg = {
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.eResolution = ADC_RESOLUTION_12_BIT, //!< 12 bit resolution
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.eAlign = ADC_ALIGN_RIGHT, //!< Align right
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.eTriggerMode = ADC_TRIGMODE_SW, //!< Software trigger
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.bWaitEnable = false, //!< Disable wait conversion mode
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.bCalEnable = false,
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.s32CalOffset = 0U,
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.s32CalGain = 0U,
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.bSequenceGroupModeEnable = false, //!< Disable sequence group mode
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.eTrgLatchUnitPri = TRG_LATCH_UNIT_PRI_ROUND_ROBIN, //!< Round robin priority
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.eClockDivider = ADC_CLOCK_DIV_1, //!< Adc clock divided by 1
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.eSequenceMode = ADC_SEQMODE_SINGLE, //!< Single sequence mode
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.eOverrunMode = ADC_OVERRUN_MODE_PRESERVE, //!< When overrun occurred, the old conversion data are preserved
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.eVoltageRef = ADC_REF_INTERNAL, //!< Use internal reference
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.bHwAvgEnable = false, //!< Disable averaging functionality
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.eHwAverage = ADC_AVERAGE_4, //!< Selection for number of samples used for averaging
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.aSampleTimes = {4U, 10U, 40U, 80U}, //!< ADC channel sample time options
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},
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.s_tAdcDmaCfg = {
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.bDmaEnable = true,
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.eSeqGroupIndex = ADC_SEQUENCE_GROUP_0,
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.eDmaInstance = DMA_INSTANCE_0,
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.eDmaChannel = ADC_DMA_CHANNEL,
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.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY,
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.pResultBuffer = (void *) ((uint32_t) DMA_BUF),
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.pConvCompleteNotify = Bsp_ADC_HandleResult,
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}
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};
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ADC_Init(ADCx, &adc.s_tAdcInitCfg);
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ADC_InitChannel(ADCx, s_aChannels, num_aChannels);
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ADC_InitDmaChannel(ADCx, &adc.s_tAdcDmaCfg);
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ADC_Enable(ADC_INSTANCE_0);
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NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_4);
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NVIC_EnableIRQ(IRQ_DMA);
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NVIC_SetPriority(DMA_Error_IRQn, IRQ_DMA_PRIORITY);
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NVIC_SetPriority(IRQ_DMA, IRQ_DMA_PRIORITY);
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return adc;
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}
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static float *vAdcGet(tAdcFlagchip *env, uint32_t timeout) {
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ADC_Start(env->ADCx);
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uint8_t res;
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uint16_t sent = osMessageQueueGet(env->txAccessQueue, &res, 0, timeout);
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if (sent == osOK) {
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for (uint8_t i = 0; i < env->num_aChannels; ++i) {
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env->pVoltageBuffer[i] = (float) env->DMA_BUF[i] / ((1U << 12U) - 1U) * VREF;
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}
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}
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return env->pVoltageBuffer;
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}
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tAdcIO vAdcGetIo(tAdcFlagchip *env) {
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tAdcIO io = {
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.env = env,
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.get = (AdcIOTransaction) vAdcGet,
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};
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return io;
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} |