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doc/DS_AT32F435_437_V2.02-EN-4.pdf Normal file
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/**
**************************************************************************
* @file at32f435_437.h
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __AT32F435_437_H
#define __AT32F435_437_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F435_437
* @{
*/
/** @addtogroup Library_configuration_section
* @{
*/
/**
* tip: to avoid modifying this file each time you need to switch between these
* devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (AT32F435CCU7) && !defined (AT32F435CGU7) && !defined (AT32F435CMU7) && \
!defined (AT32F435CCT7) && !defined (AT32F435CGT7) && !defined (AT32F435CMT7) && \
!defined (AT32F435RCT7) && !defined (AT32F435RGT7) && !defined (AT32F435RMT7) && \
!defined (AT32F435VCT7) && !defined (AT32F435VGT7) && !defined (AT32F435VMT7) && \
!defined (AT32F435ZCT7) && !defined (AT32F435ZGT7) && !defined (AT32F435ZMT7) && \
!defined (AT32F437RCT7) && !defined (AT32F437RGT7) && !defined (AT32F437RMT7) && \
!defined (AT32F437VCT7) && !defined (AT32F437VGT7) && !defined (AT32F437VMT7) && \
!defined (AT32F437ZCT7) && !defined (AT32F437ZGT7) && !defined (AT32F437ZMT7)
#error "Please select first the target device used in your application (in at32f435_437.h file)"
#endif
#if defined (AT32F435CCU7) || defined (AT32F435CGU7) || defined (AT32F435CMU7) || \
defined (AT32F435CCT7) || defined (AT32F435CGT7) || defined (AT32F435CMT7) || \
defined (AT32F435RCT7) || defined (AT32F435RGT7) || defined (AT32F435RMT7) || \
defined (AT32F435VCT7) || defined (AT32F435VGT7) || defined (AT32F435VMT7) || \
defined (AT32F435ZCT7) || defined (AT32F435ZGT7) || defined (AT32F435ZMT7)
#define AT32F435xx
#endif
#if defined (AT32F437RCT7) || defined (AT32F437RGT7) || defined (AT32F437RMT7) || \
defined (AT32F437VCT7) || defined (AT32F437VGT7) || defined (AT32F437VMT7) || \
defined (AT32F437ZCT7) || defined (AT32F437ZGT7) || defined (AT32F437ZMT7)
#define AT32F437xx
#endif
#ifndef USE_STDPERIPH_DRIVER
/**
* @brief comment the line below if you will not use the peripherals drivers.
* in this case, these drivers will not be included and the application code will
* be based on direct access to peripherals registers
*/
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
#define USE_STDPERIPH_DRIVER
#endif
#endif
#endif
/**
* @brief at32f435_437 standard peripheral library version number
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
(__AT32F435_437_LIBRARY_VERSION_MINOR << 8) | \
(__AT32F435_437_LIBRARY_VERSION_RC))
/**
* @}
*/
/** @addtogroup configuration_section_for_cmsis
* @{
*/
/**
* @brief configuration of the cortex-m4 processor and core peripherals
*/
#define __CM4_REV 0x0001U /*!< core revision r0p1 */
#define __MPU_PRESENT 1 /*!< mpu present */
#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
#define __FPU_PRESENT 1U /*!< fpu present */
/**
* @brief at32f435_437 interrupt number definition, according to the selected device
* in @ref library_configuration_section
*/
typedef enum IRQn
{
/****** cortex-m4 processor exceptions numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
/****** at32 specific interrupt numbers *********************************************************/
WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */
ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */
FLASH_IRQn = 4, /*!< flash global interrupt */
CRM_IRQn = 5, /*!< crm global interrupt */
EXINT0_IRQn = 6, /*!< exint line0 interrupt */
EXINT1_IRQn = 7, /*!< exint line1 interrupt */
EXINT2_IRQn = 8, /*!< exint line2 interrupt */
EXINT3_IRQn = 9, /*!< exint line3 interrupt */
EXINT4_IRQn = 10, /*!< exint line4 interrupt */
EDMA_Stream1_IRQn = 11, /*!< edma stream 1 global interrupt */
EDMA_Stream2_IRQn = 12, /*!< edma stream 2 global interrupt */
EDMA_Stream3_IRQn = 13, /*!< edma stream 3 global interrupt */
EDMA_Stream4_IRQn = 14, /*!< edma stream 4 global interrupt */
EDMA_Stream5_IRQn = 15, /*!< edma stream 5 global interrupt */
EDMA_Stream6_IRQn = 16, /*!< edma stream 6 global interrupt */
EDMA_Stream7_IRQn = 17, /*!< edma stream 7 global interrupt */
#if defined (AT32F435xx)
ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
SPI1_IRQn = 35, /*!< spi1 global interrupt */
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
USART1_IRQn = 37, /*!< usart1 global interrupt */
USART2_IRQn = 38, /*!< usart2 global interrupt */
USART3_IRQn = 39, /*!< usart3 global interrupt */
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
EDMA_Stream8_IRQn = 47, /*!< edma stream 8 global interrupt */
XMC_IRQn = 48, /*!< xmc global interrupt */
SDIO1_IRQn = 49, /*!< sdio global interrupt */
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
UART4_IRQn = 52, /*!< uart4 global interrupt */
UART5_IRQn = 53, /*!< uart5 global interrupt */
TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
USART6_IRQn = 71, /*!< usart6 interrupt */
I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
DVP_IRQn = 78, /*!< dvp interrupt */
FPU_IRQn = 81, /*!< fpu interrupt */
UART7_IRQn = 82, /*!< uart7 interrupt */
UART8_IRQn = 83, /*!< uart8 interrupt */
SPI4_IRQn = 84, /*!< spi4 global interrupt */
QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
ACC_IRQn = 103, /*!< acc interrupt */
TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
#endif
#if defined (AT32F437xx)
ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
SPI1_IRQn = 35, /*!< spi1 global interrupt */
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
USART1_IRQn = 37, /*!< usart1 global interrupt */
USART2_IRQn = 38, /*!< usart2 global interrupt */
USART3_IRQn = 39, /*!< usart3 global interrupt */
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
EDMA_Stream8_IRQn = 47, /*!< dma1 stream 8 global interrupt */
XMC_IRQn = 48, /*!< xmc global interrupt */
SDIO1_IRQn = 49, /*!< sdio global interrupt */
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
UART4_IRQn = 52, /*!< uart4 global interrupt */
UART5_IRQn = 53, /*!< uart5 global interrupt */
TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
EMAC_IRQn = 61, /*!< emac interrupt */
EMAC_WKUP_IRQn = 62, /*!< emac wakeup interrupt */
CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
USART6_IRQn = 71, /*!< usart6 interrupt */
I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
DVP_IRQn = 78, /*!< dvp interrupt */
FPU_IRQn = 81, /*!< fpu interrupt */
UART7_IRQn = 82, /*!< uart7 interrupt */
UART8_IRQn = 83, /*!< uart8 interrupt */
SPI4_IRQn = 84, /*!< spi4 global interrupt */
QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
ACC_IRQn = 103, /*!< acc interrupt */
TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
#endif
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h"
#include "system_at32f435_437.h"
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
typedef int32_t INT32;
typedef int16_t INT16;
typedef int8_t INT8;
typedef uint32_t UINT32;
typedef uint16_t UINT16;
typedef uint8_t UINT8;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< read only */
typedef const int16_t sc16; /*!< read only */
typedef const int8_t sc8; /*!< read only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< read only */
typedef __I int16_t vsc16; /*!< read only */
typedef __I int8_t vsc8; /*!< read only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< read only */
typedef const uint16_t uc16; /*!< read only */
typedef const uint8_t uc8; /*!< read only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< read only */
typedef __I uint16_t vuc16; /*!< read only */
typedef __I uint8_t vuc8; /*!< read only */
typedef enum {RESET = 0, SET = !RESET} flag_status;
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define REG8(addr) *(volatile uint8_t *)(addr)
#define REG16(addr) *(volatile uint16_t *)(addr)
#define REG32(addr) *(volatile uint32_t *)(addr)
#define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f))
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
#define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f))
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define XMC_SDRAM_MEM_BASE ((uint32_t)0xC0000000)
#define QSPI2_MEM_BASE ((uint32_t)0xB0000000)
#define XMC_CARD_MEM_BASE ((uint32_t)0xA8000000)
#define QSPI2_REG_BASE ((uint32_t)0xA0002000)
#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
#define XMC_REG_BASE ((uint32_t)0xA0000000)
#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
#define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
#define QSPI1_MEM_BASE ((uint32_t)0x90000000)
#define XMC_MEM_BASE ((uint32_t)0x60000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define SRAM_BB_BASE ((uint32_t)0x22000000)
#define PERIPH_BB_BASE ((uint32_t)0x42000000)
#define SRAM_BASE ((uint32_t)0x20000000)
#define USD_BASE ((uint32_t)0x1FFFC000)
#define FLASH_BASE ((uint32_t)0x08000000)
#define DEBUG_BASE ((uint32_t)0xE0042000)
#define APB1PERIPH_BASE (PERIPH_BASE)
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
#define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000)
#if defined (AT32F435xx)
/* apb1 bus base address */
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
/* apb2 bus base address */
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
/* ahb bus base address */
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
#endif
#if defined (AT32F437xx)
/* apb1 bus base address */
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
/* apb2 bus base address */
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
/* ahb bus base address */
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
#define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
#define EMAC_MAC_BASE (EMAC_BASE)
#define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
#define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
#define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#include "at32f435_437_def.h"
#include "at32f435_437_conf.h"
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file system_at32f435_437.h
* @version v2.0.4
* @date 2021-12-31
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __SYSTEM_AT32F435_437_H
#define __SYSTEM_AT32F435_437_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F435_437_system
* @{
*/
/** @defgroup AT32F435_437_system_exported_variables
* @{
*/
extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
/**
* @}
*/
/** @defgroup AT32F435_437_system_exported_functions
* @{
*/
extern void SystemInit(void);
extern void system_core_clock_update(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/*
*****************************************************************************
**
** File : AT32F437xM_FLASH.ld
**
** Abstract : Linker script for AT32F437xM Device with
** 4096KByte FLASH, 384KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : Artery Tek AT32
**
** Environment : Arm gcc toolchain
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20017FFF; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
_FullFirmwareSize = 300K ;
_MetadataSize = 256 ;
_FirmwareSize = _FullFirmwareSize - _MetadataSize ;
_FirmwareBegin = 0x08000000;
_StorageSize = 16K;
_StorageABegin = 0x0804B000;
_StorageBBegin = 0x0804F000;
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = _FirmwareBegin, LENGTH = _FirmwareSize
META (rx) : ORIGIN = _FirmwareBegin + _FirmwareSize, LENGTH = _MetadataSize
STORAGE_A (rx) : ORIGIN = _StorageABegin, LENGTH = _StorageSize
STORAGE_B (rx) : ORIGIN = _StorageBBegin, LENGTH = _StorageSize
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
.metaaaa : SUBALIGN(1)
{
KEEP(*(.meta_fw_crc))
LONG(_FirmwareSize) ; /* word with firmware_size */
KEEP(*(.meta_fw_name_size))
KEEP(*(.meta_fw_name))
KEEP(*(.meta_hw_name_size))
KEEP(*(.meta_hw_name))
. = ALIGN(256);
} >META
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

154
ld/AT32F437xM_FLASH.ld Normal file
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/*
*****************************************************************************
**
** File : AT32F437xM_FLASH.ld
**
** Abstract : Linker script for AT32F437xM Device with
** 4096KByte FLASH, 384KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : Artery Tek AT32
**
** Environment : Arm gcc toolchain
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20017FFF; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

17
modular.json Normal file
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{
"dep": [
{
"type": "git",
"provider": "HVAC_DEV",
"repo": "PeripheralDriver_ARTERY_AT32F435_437"
}
],
"cmake": {
"inc_dirs": [
"inc"
],
"srcs": [
"src/**.c"
]
}
}

178
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/**
**************************************************************************
* @file system_at32f435_437.c
* @version v2.0.4
* @date 2021-12-31
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup AT32F435_437_system
* @{
*/
#include "at32f435_437.h"
/** @addtogroup AT32F435_437_system_private_defines
* @{
*/
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
#endif
/**
* @}
*/
/** @addtogroup AT32F435_437_system_private_variables
* @{
*/
unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
/**
* @}
*/
/** @addtogroup AT32F435_437_system_private_functions
* @{
*/
/**
* @brief setup the microcontroller system
* initialize the flash interface.
* @note this function should be used only after reset.
* @param none
* @retval none
*/
void SystemInit(void) {
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
(3U << 11U * 2U)); /* set cp11 full access */
#endif
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = TRUE;
/* wait hick stable */
while (CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while (CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
CRM->cfg = 0;
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset pllms pllns pllfr pllrcs bits */
CRM->pllcfg = 0x00033002U;
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000U;
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
#endif
}
/**
* @brief update system_core_clock variable according to clock register values.
* the system_core_clock variable contains the core clock (hclk), it can
* be used by the user application to setup the systick timer or configure
* other parameters.
* @param none
* @retval none
*/
void system_core_clock_update(void) {
uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
uint32_t temp = 0, div_value = 0;
crm_sclk_type sclk_source;
static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch (sclk_source) {
case CRM_SCLK_HICK:
if (((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
system_core_clock = HICK_VALUE * 6;
else
system_core_clock = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
system_core_clock = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
/* get pll clock source */
pll_clock_source = CRM->pllcfg_bit.pllrcs;
/* get multiplication factor */
pll_ns = CRM->pllcfg_bit.pllns;
pll_ms = CRM->pllcfg_bit.pllms;
pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
if (pll_clock_source == CRM_PLL_SOURCE_HICK) {
/* hick selected as pll clock entry */
pllrcsfreq = HICK_VALUE;
} else {
/* hext selected as pll clock entry */
pllrcsfreq = HEXT_VALUE;
}
system_core_clock = (pllrcsfreq * pll_ns) / (pll_ms * pll_fr);
break;
default:
system_core_clock = HICK_VALUE;
break;
}
/* compute sclk, ahbclk frequency */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sys_ahb_div_table[temp];
/* ahbclk frequency */
system_core_clock = system_core_clock >> div_value;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CONF_H
#define __AT32F435_437_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup AT32F435_periph_template
* @{
*/
/** @addtogroup 435_Library_configuration Library_configuration
* @{
*/
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)
* used in your application
*
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)25000000) /*!< value of the high speed exernal crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define DAC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define EDMA_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define SDIO_MODULE_ENABLED
#define XMC_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define ACC_MODULE_ENABLED
#define MISC_MODULE_ENABLED
#define QSPI_MODULE_ENABLED
#define DVP_MODULE_ENABLED
#define SCFG_MODULE_ENABLED
#define EMAC_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f435_437_crm.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f435_437_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f435_437_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f435_437_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f435_437_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f435_437_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f435_437_pwc.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f435_437_can.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f435_437_adc.h"
#endif
#ifdef DAC_MODULE_ENABLED
#include "at32f435_437_dac.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f435_437_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f435_437_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f435_437_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f435_437_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f435_437_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f435_437_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f435_437_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f435_437_exint.h"
#endif
#ifdef SDIO_MODULE_ENABLED
#include "at32f435_437_sdio.h"
#endif
#ifdef XMC_MODULE_ENABLED
#include "at32f435_437_xmc.h"
#endif
#ifdef ACC_MODULE_ENABLED
#include "at32f435_437_acc.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f435_437_misc.h"
#endif
#ifdef EDMA_MODULE_ENABLED
#include "at32f435_437_edma.h"
#endif
#ifdef QSPI_MODULE_ENABLED
#include "at32f435_437_qspi.h"
#endif
#ifdef SCFG_MODULE_ENABLED
#include "at32f435_437_scfg.h"
#endif
#ifdef EMAC_MODULE_ENABLED
#include "at32f435_437_emac.h"
#endif
#ifdef DVP_MODULE_ENABLED
#include "at32f435_437_dvp.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f435_437_usb.h"
#endif
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_conf.h
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CONF_H
#define __AT32F435_437_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed exernal crystal (hext)
* used in your application
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define CAN_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define DAC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define EDMA_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define SDIO_MODULE_ENABLED
#define XMC_MODULE_ENABLED
#define USB_MODULE_ENABLED
#define ACC_MODULE_ENABLED
#define MISC_MODULE_ENABLED
#define QSPI_MODULE_ENABLED
#define DVP_MODULE_ENABLED
#define SCFG_MODULE_ENABLED
#define EMAC_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f435_437_crm.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f435_437_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f435_437_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f435_437_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f435_437_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f435_437_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f435_437_pwc.h"
#endif
#ifdef CAN_MODULE_ENABLED
#include "at32f435_437_can.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f435_437_adc.h"
#endif
#ifdef DAC_MODULE_ENABLED
#include "at32f435_437_dac.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f435_437_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f435_437_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f435_437_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f435_437_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f435_437_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f435_437_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f435_437_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f435_437_exint.h"
#endif
#ifdef SDIO_MODULE_ENABLED
#include "at32f435_437_sdio.h"
#endif
#ifdef XMC_MODULE_ENABLED
#include "at32f435_437_xmc.h"
#endif
#ifdef ACC_MODULE_ENABLED
#include "at32f435_437_acc.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f435_437_misc.h"
#endif
#ifdef EDMA_MODULE_ENABLED
#include "at32f435_437_edma.h"
#endif
#ifdef QSPI_MODULE_ENABLED
#include "at32f435_437_qspi.h"
#endif
#ifdef SCFG_MODULE_ENABLED
#include "at32f435_437_scfg.h"
#endif
#ifdef EMAC_MODULE_ENABLED
#include "at32f435_437_emac.h"
#endif
#ifdef DVP_MODULE_ENABLED
#include "at32f435_437_dvp.h"
#endif
#ifdef USB_MODULE_ENABLED
#include "at32f435_437_usb.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* __AT32F435_437_CONF_H */

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/**
**************************************************************************
* @file at32f435_437_clock.c
* @version v2.0.4
* @date 2021-12-31
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f435_437_clock.h"
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* - system clock = (hext * pll_ns)/(pll_ms * pll_fr)
* - system clock source = pll (hext)
* - hext = 8000000
* - sclk = 250000000
* - ahbdiv = 1
* - ahbclk = 250000000
* - apb2div = 2
* - apb2clk = 125000000
* - apb1div = 2
* - apb1clk = 125000000
* - pll_ns = 125
* - pll_ms = 1
* - pll_fr = 4
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
/* config ldo voltage */
pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
#if defined PLL_NS
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT, PLL_NS, 1, CRM_PLL_FR_4);
#endif
#if !defined PLL_NS
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT, 40, 1, CRM_PLL_FR_4);
#endif
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk */
crm_apb1_div_set(CRM_APB1_DIV_2);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}

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/**
**************************************************************************
* @file at32f435_437_clock.h
* @version v2.0.4
* @date 2021-12-31
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_CLOCK_H
#define __AT32F435_437_CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/* exported functions ------------------------------------------------------- */
void system_clock_config(void);
#ifdef __cplusplus
}
#endif
#endif

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/**
**************************************************************************
* @file at32f435_437_int.c
* @version v2.0.4
* @date 2021-12-31
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f435_437_int.h"
/** @addtogroup AT32F437_periph_examples
* @{
*/
/** @addtogroup 437_EMAC_tcp_server
* @{
*/
/**
* @brief this function handles nmi exception.
* @param none
* @retval none
*/
//void NMI_Handler(void)
//{
//}
/**
* @brief this function handles hard fault exception.
* @param none
* @retval none
*/
//void HardFault_Handler(void)
//{
/* go to infinite loop when hard fault exception occurs */
// while(1)
// {
// }
//}
/**
* @brief this function handles memory manage exception.
* @param none
* @retval none
*/
//void MemManage_Handler(void)
//{
/* go to infinite loop when memory manage exception occurs */
// while(1)
// {
// }
//}
/**
* @brief this function handles bus fault exception.
* @param none
* @retval none
*/
//void BusFault_Handler(void)
//{
/* go to infinite loop when bus fault exception occurs */
// while(1)
// {
// }
//}
/**
* @brief this function handles usage fault exception.
* @param none
* @retval none
*/
//void UsageFault_Handler(void)
//{
/* go to infinite loop when usage fault exception occurs */
// while(1)
// {
// }
//}
/**
* @brief this function handles svcall exception.
* @param none
* @retval none
*/
//void SVC_Handler(void)
//{
//}
/**
* @brief this function handles debug monitor exception.
* @param none
* @retval none
*/
//void DebugMon_Handler(void)
//{
//}
/**
* @brief this function handles pendsv_handler exception.
* @param none
* @retval none
*/
//void PendSV_Handler(void)
//{
//}
/**
* @brief this function handles systick handler.
* @param none
* @retval none
*/
//void SysTick_Handler(void)
//{
//}
/**
* @brief this function handles emac handler.
* @param none
* @retval none
*/
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f435_437_int.h
* @version v2.0.4
* @date 2021-12-31
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F435_437_INT_H
#define __AT32F435_437_INT_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f435_437.h"
/* exported types ------------------------------------------------------------*/
/* exported constants --------------------------------------------------------*/
/* exported macro ------------------------------------------------------------*/
/* exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif

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//
// Created by xemon on 06.02.24.
//
_Noreturn void stop_it() {
while (1) {
asm("nop");
}
}
#define STOP_IT stop_it();
void WWDT_IRQHandler() {
STOP_IT
}
void PVM_IRQHandler() {
STOP_IT
}
void TAMP_STAMP_IRQHandler() {
STOP_IT
}
void ERTC_WKUP_IRQHandler() {
STOP_IT
}
void FLASH_IRQHandler() {
STOP_IT
}
void CRM_IRQHandler() {
STOP_IT
}
void EXINT0_IRQHandler() {
STOP_IT
}
void EXINT1_IRQHandler() {
STOP_IT
}
void EXINT2_IRQHandler() {
STOP_IT
}
void EXINT3_IRQHandler() {
STOP_IT
}
void EXINT4_IRQHandler() {
STOP_IT
}
void EDMA_Stream1_IRQHandler() {
STOP_IT
}
void EDMA_Stream2_IRQHandler() {
STOP_IT
}
void EDMA_Stream3_IRQHandler() {
STOP_IT
}
void EDMA_Stream4_IRQHandler() {
STOP_IT
}
void EDMA_Stream5_IRQHandler() {
STOP_IT
}
void EDMA_Stream6_IRQHandler() {
STOP_IT
}
void EDMA_Stream7_IRQHandler() {
STOP_IT
}
void ADC1_2_3_IRQHandler() {
STOP_IT
}
void CAN1_TX_IRQHandler() {
STOP_IT
}
void CAN1_RX0_IRQHandler() {
STOP_IT
}
void CAN1_RX1_IRQHandler() {
STOP_IT
}
void CAN1_SE_IRQHandler() {
STOP_IT
}
void EXINT9_5_IRQHandler() {
STOP_IT
}
void TMR1_BRK_TMR9_IRQHandler() {
STOP_IT
}
void TMR1_OVF_TMR10_IRQHandler() {
STOP_IT
}
void TMR1_TRG_HALL_TMR11_IRQHandler() {
STOP_IT
}
void TMR1_CH_IRQHandler() {
STOP_IT
}
void TMR2_GLOBAL_IRQHandler() {
STOP_IT
}
void TMR3_GLOBAL_IRQHandler() {
STOP_IT
}
void TMR4_GLOBAL_IRQHandler() {
STOP_IT
}
void I2C1_EVT_IRQHandler() {
STOP_IT
}
void I2C1_ERR_IRQHandler() {
STOP_IT
}
void I2C2_EVT_IRQHandler() {
STOP_IT
}
void I2C2_ERR_IRQHandler() {
STOP_IT
}
void SPI1_IRQHandler() {
STOP_IT
}
void SPI2_I2S2EXT_IRQHandler() {
STOP_IT
}
//void USART1_IRQHandler() {
// STOP_IT
//}
void USART2_IRQHandler() {
STOP_IT
}
//void USART3_IRQHandler() {
// STOP_IT
//}
void EXINT15_10_IRQHandler() {
STOP_IT
}
void ERTCAlarm_IRQHandler() {
STOP_IT
}
void OTGFS1_WKUP_IRQHandler() {
STOP_IT
}
void TMR8_BRK_TMR12_IRQHandler() {
STOP_IT
}
void TMR8_OVF_TMR13_IRQHandler() {
STOP_IT
}
void TMR8_TRG_HALL_TMR14_IRQHandler() {
STOP_IT
}
void TMR8_CH_IRQHandler() {
STOP_IT
}
void EDMA_Stream8_IRQHandler() {
STOP_IT
}
void XMC_IRQHandler() {
STOP_IT
}
void SDIO1_IRQHandler() {
STOP_IT
}
void TMR5_GLOBAL_IRQHandler() {
STOP_IT
}
void SPI3_I2S3EXT_IRQHandler() {
STOP_IT
}
void UART4_IRQHandler() {
STOP_IT
}
void UART5_IRQHandler() {
STOP_IT
}
void TMR6_DAC_GLOBAL_IRQHandler() {
STOP_IT
}
void TMR7_GLOBAL_IRQHandler() {
STOP_IT
}
//void DMA1_Channel1_IRQHandler() {
// STOP_IT
//}
//void DMA1_Channel2_IRQHandler() {
// STOP_IT
//}
//void DMA1_Channel3_IRQHandler() {
// STOP_IT
//}
//
//void DMA1_Channel4_IRQHandler() {
// STOP_IT
//}
//void DMA1_Channel5_IRQHandler() {
// STOP_IT
//}
void EMAC_IRQHandler() {
STOP_IT
}
void EMAC_WKUP_IRQHandler() {
STOP_IT
}
void CAN2_TX_IRQHandler() {
STOP_IT
}
void CAN2_RX0_IRQHandler() {
STOP_IT
}
void CAN2_RX1_IRQHandler() {
STOP_IT
}
void CAN2_SE_IRQHandler() {
STOP_IT
}
void OTGFS1_IRQHandler() {
STOP_IT
}
//void DMA1_Channel6_IRQHandler() {
// STOP_IT
//}
void DMA1_Channel7_IRQHandler() {
STOP_IT
}
void USART6_IRQHandler() {
STOP_IT
}
void I2C3_EVT_IRQHandler() {
STOP_IT
}
void I2C3_ERR_IRQHandler() {
STOP_IT
}
void OTGFS2_WKUP_IRQHandler() {
STOP_IT
}
void OTGFS2_IRQHandler() {
STOP_IT
}
void DVP_IRQHandler() {
STOP_IT
}
void FPU_IRQHandler() {
STOP_IT
}
void UART7_IRQHandler() {
STOP_IT
}
//void UART8_IRQHandler() {
// STOP_IT
//}
void SPI4_IRQHandler() {
STOP_IT
}
void QSPI2_IRQHandler() {
STOP_IT
}
void QSPI1_IRQHandler() {
STOP_IT
}
void DMAMUX_IRQHandler() {
STOP_IT
}
void SDIO2_IRQHandler() {
STOP_IT
}
void ACC_IRQHandler() {
STOP_IT
}
void TMR20_BRK_IRQHandler() {
STOP_IT
}
void TMR20_OVF_IRQHandler() {
STOP_IT
}
void TMR20_TRG_HALL_IRQHandler() {
STOP_IT
}
void TMR20_CH_IRQHandler() {
STOP_IT
}
void DMA2_Channel1_IRQHandler() {
STOP_IT
}
void DMA2_Channel2_IRQHandler() {
STOP_IT
}
void DMA2_Channel3_IRQHandler() {
STOP_IT
}
void DMA2_Channel4_IRQHandler() {
STOP_IT
}
void DMA2_Channel5_IRQHandler() {
STOP_IT
}
void DMA2_Channel6_IRQHandler() {
STOP_IT
}
void DMA2_Channel7_IRQHandler() {
STOP_IT
}
//void _estack() {
// STOP_IT
//}
//void Reset_Handler() {
// STOP_IT
//}
void NMI_Handler() {
STOP_IT
}
void HardFault_Handler() {
STOP_IT
}
void MemManage_Handler() {
STOP_IT
}
void BusFault_Handler() {
STOP_IT
}
void UsageFault_Handler() {
STOP_IT
}
//void SVC_Handler() {
// STOP_IT
//}
void DebugMon_Handler() {
STOP_IT
}
//void PendSV_Handler() {
// STOP_IT
//}
//
//void SysTick_Handler() {
// STOP_IT
//}

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/**
******************************************************************************
* @file startup_at32f435_437.s
* @version v2.0.4
* @date 2021-12-31
* @brief at32f435_437 devices vector table for gcc toolchain.
* this module performs:
* - set the initial sp
* - set the initial pc == reset_handler,
* - set the vector table entries with the exceptions isr address
* - configure the clock system and the external sram to
* be used as data memory (optional, to be enabled by user)
* - branches to main in the c library (which eventually
* calls main()).
* after reset the cortex-m4 processor is in thread mode,
* priority is privileged, and the stack is set to main.
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDT_IRQHandler /* Window Watchdog Timer */
.word PVM_IRQHandler /* PVM through EXINT Line detect */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */
.word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */
.word FLASH_IRQHandler /* Flash */
.word CRM_IRQHandler /* CRM */
.word EXINT0_IRQHandler /* EXINT Line 0 */
.word EXINT1_IRQHandler /* EXINT Line 1 */
.word EXINT2_IRQHandler /* EXINT Line 2 */
.word EXINT3_IRQHandler /* EXINT Line 3 */
.word EXINT4_IRQHandler /* EXINT Line 4 */
.word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */
.word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */
.word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */
.word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */
.word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */
.word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */
.word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */
.word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SE_IRQHandler /* CAN1 SE */
.word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
.word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
.word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */
.word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
.word TMR1_CH_IRQHandler /* TMR1 Channel */
.word TMR2_GLOBAL_IRQHandler /* TMR2 */
.word TMR3_GLOBAL_IRQHandler /* TMR3 */
.word TMR4_GLOBAL_IRQHandler /* TMR4 */
.word I2C1_EVT_IRQHandler /* I2C1 Event */
.word I2C1_ERR_IRQHandler /* I2C1 Error */
.word I2C2_EVT_IRQHandler /* I2C2 Event */
.word I2C2_ERR_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_I2S2EXT_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
.word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */
.word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */
.word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */
.word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */
.word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */
.word TMR8_CH_IRQHandler /* TMR8 Channel */
.word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */
.word XMC_IRQHandler /* XMC */
.word SDIO1_IRQHandler /* SDIO1 */
.word TMR5_GLOBAL_IRQHandler /* TMR5 */
.word SPI3_I2S3EXT_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */
.word TMR7_GLOBAL_IRQHandler /* TMR7 */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.word EMAC_IRQHandler /* EMAC */
.word EMAC_WKUP_IRQHandler /* EMAC Wakeup */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SE_IRQHandler /* CAN2 SE */
.word OTGFS1_IRQHandler /* OTGFS1 */
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.word 0 /* Reserved */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EVT_IRQHandler /* I2C3 Event */
.word I2C3_ERR_IRQHandler /* I2C3 Error */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */
.word OTGFS2_IRQHandler /* OTGFS2 */
.word DVP_IRQHandler /* DVP */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word QSPI2_IRQHandler /* QSPI2 */
.word QSPI1_IRQHandler /* QSPI1 */
.word 0 /* Reserved */
.word DMAMUX_IRQHandler /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SDIO2_IRQHandler /* SDIO2 */
.word ACC_IRQHandler /* ACC */
.word TMR20_BRK_IRQHandler /* TMR20 Brake */
.word TMR20_OVF_IRQHandler /* TMR20 Overflow */
.word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */
.word TMR20_CH_IRQHandler /* TMR20 Channel */
.word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
.word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
.word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
.word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
.word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
.word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
.word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler,Default_Handler
.weak PVM_IRQHandler
.thumb_set PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak ERTC_WKUP_IRQHandler
.thumb_set ERTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak CRM_IRQHandler
.thumb_set CRM_IRQHandler,Default_Handler
.weak EXINT0_IRQHandler
.thumb_set EXINT0_IRQHandler,Default_Handler
.weak EXINT1_IRQHandler
.thumb_set EXINT1_IRQHandler,Default_Handler
.weak EXINT2_IRQHandler
.thumb_set EXINT2_IRQHandler,Default_Handler
.weak EXINT3_IRQHandler
.thumb_set EXINT3_IRQHandler,Default_Handler
.weak EXINT4_IRQHandler
.thumb_set EXINT4_IRQHandler,Default_Handler
.weak EDMA_Stream1_IRQHandler
.thumb_set EDMA_Stream1_IRQHandler,Default_Handler
.weak EDMA_Stream2_IRQHandler
.thumb_set EDMA_Stream2_IRQHandler,Default_Handler
.weak EDMA_Stream3_IRQHandler
.thumb_set EDMA_Stream3_IRQHandler,Default_Handler
.weak EDMA_Stream4_IRQHandler
.thumb_set EDMA_Stream4_IRQHandler,Default_Handler
.weak EDMA_Stream5_IRQHandler
.thumb_set EDMA_Stream5_IRQHandler,Default_Handler
.weak EDMA_Stream6_IRQHandler
.thumb_set EDMA_Stream6_IRQHandler,Default_Handler
.weak EDMA_Stream7_IRQHandler
.thumb_set EDMA_Stream7_IRQHandler,Default_Handler
.weak ADC1_2_3_IRQHandler
.thumb_set ADC1_2_3_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SE_IRQHandler
.thumb_set CAN1_SE_IRQHandler,Default_Handler
.weak EXINT9_5_IRQHandler
.thumb_set EXINT9_5_IRQHandler,Default_Handler
.weak TMR1_BRK_TMR9_IRQHandler
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
.weak TMR1_OVF_TMR10_IRQHandler
.thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
.weak TMR1_TRG_HALL_TMR11_IRQHandler
.thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
.weak TMR1_CH_IRQHandler
.thumb_set TMR1_CH_IRQHandler,Default_Handler
.weak TMR2_GLOBAL_IRQHandler
.thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
.weak TMR3_GLOBAL_IRQHandler
.thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
.weak TMR4_GLOBAL_IRQHandler
.thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
.weak I2C1_EVT_IRQHandler
.thumb_set I2C1_EVT_IRQHandler,Default_Handler
.weak I2C1_ERR_IRQHandler
.thumb_set I2C1_ERR_IRQHandler,Default_Handler
.weak I2C2_EVT_IRQHandler
.thumb_set I2C2_EVT_IRQHandler,Default_Handler
.weak I2C2_ERR_IRQHandler
.thumb_set I2C2_ERR_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_I2S2EXT_IRQHandler
.thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXINT15_10_IRQHandler
.thumb_set EXINT15_10_IRQHandler,Default_Handler
.weak ERTCAlarm_IRQHandler
.thumb_set ERTCAlarm_IRQHandler,Default_Handler
.weak OTGFS1_WKUP_IRQHandler
.thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler
.weak TMR8_BRK_TMR12_IRQHandler
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
.weak TMR8_OVF_TMR13_IRQHandler
.thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler
.weak TMR8_TRG_HALL_TMR14_IRQHandler
.thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
.weak TMR8_CH_IRQHandler
.thumb_set TMR8_CH_IRQHandler,Default_Handler
.weak EDMA_Stream8_IRQHandler
.thumb_set EDMA_Stream8_IRQHandler,Default_Handler
.weak XMC_IRQHandler
.thumb_set XMC_IRQHandler,Default_Handler
.weak SDIO1_IRQHandler
.thumb_set SDIO1_IRQHandler,Default_Handler
.weak TMR5_GLOBAL_IRQHandler
.thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
.weak SPI3_I2S3EXT_IRQHandler
.thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TMR6_DAC_GLOBAL_IRQHandler
.thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler
.weak TMR7_GLOBAL_IRQHandler
.thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak EMAC_IRQHandler
.thumb_set EMAC_IRQHandler,Default_Handler
.weak EMAC_WKUP_IRQHandler
.thumb_set EMAC_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler ,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler ,Default_Handler
.weak CAN2_SE_IRQHandler
.thumb_set CAN2_SE_IRQHandler,Default_Handler
.weak OTGFS1_IRQHandler
.thumb_set OTGFS1_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EVT_IRQHandler
.thumb_set I2C3_EVT_IRQHandler,Default_Handler
.weak I2C3_ERR_IRQHandler
.thumb_set I2C3_ERR_IRQHandler,Default_Handler
.weak OTGFS2_WKUP_IRQHandler
.thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler
.weak OTGFS2_IRQHandler
.thumb_set OTGFS2_IRQHandler,Default_Handler
.weak DVP_IRQHandler
.thumb_set DVP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak QSPI2_IRQHandler
.thumb_set QSPI2_IRQHandler,Default_Handler
.weak QSPI1_IRQHandler
.thumb_set QSPI1_IRQHandler,Default_Handler
.weak DMAMUX_IRQHandler
.thumb_set DMAMUX_IRQHandler ,Default_Handler
.weak SDIO2_IRQHandler
.thumb_set SDIO2_IRQHandler ,Default_Handler
.weak ACC_IRQHandler
.thumb_set ACC_IRQHandler,Default_Handler
.weak TMR20_BRK_IRQHandler
.thumb_set TMR20_BRK_IRQHandler,Default_Handler
.weak TMR20_OVF_IRQHandler
.thumb_set TMR20_OVF_IRQHandler,Default_Handler
.weak TMR20_TRG_HALL_IRQHandler
.thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler
.weak TMR20_CH_IRQHandler
.thumb_set TMR20_CH_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler