643 lines
20 KiB
C
643 lines
20 KiB
C
/* Copyright Statement:
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*
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* This software/firmware and related documentation ("AutoChips Software") are
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* protected under relevant copyright laws. The information contained herein is
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* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
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* the prior written permission of AutoChips inc. and/or its licensors, any
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* reproduction, modification, use or disclosure of AutoChips Software, and
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* information contained herein, in whole or in part, shall be strictly
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* prohibited.
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*
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* AutoChips Inc. (C) 2021. All rights reserved.
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*
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* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
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* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
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* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
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* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
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* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
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* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
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* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
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* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
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* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
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* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
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* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
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* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
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* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
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* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
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* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
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* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
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*/
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/*!
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* @file spi_hw.h
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*
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* @brief This file provides spi hardware integration functions.
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*
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*/
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/* PRQA S 4304,4394,4340 EOF */ /* Type conversion. */
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#ifndef SPI_HW_H
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#define SPI_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* =========================================== Includes =========================================== */
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#include "spi_shared_function.h"
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/* ============================================ Define ============================================ */
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/* =========================================== Typedef ============================================ */
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/*!
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* @brief SPI status flags.
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*/
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typedef enum
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{
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SPI_TX_DATA_FLAG = SPI_STATUS_TXEF_Pos, /*!< TX data not full flag */
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SPI_RX_DATA_FLAG = SPI_STATUS_RXFF_Pos, /*!< RX data not empty flag */
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SPI_TRANSMIT_ERROR = SPI_STATUS_TXUF_Pos, /*!< Transmit Error flag (TX underrun) */
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SPI_RECEIVE_ERROR = SPI_STATUS_RXOF_Pos, /*!< Receive Error flag (RX overrun) */
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SPI_MODE_FAULT_ERROR = SPI_STATUS_MODEF_Pos, /*!< Master mode fault error flag */
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SPI_DATA_MATCH = SPI_STATUS_RDMF_Pos, /*!< Data match flag */
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SPI_MASTER_BUSY = SPI_STATUS_MEBY_Pos, /*!< SPI engine busy flag */
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SPI_MODULE_IDLE = SPI_STATUS_IDLEF_Pos, /*!< Module idle flag */
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SPI_ALL_STATUS = 0x0000002CU /*!< Used for clearing all w1c status flags */
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} spi_status_flag_t;
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/*!
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* @brief SPI interrupt source.
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*/
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typedef enum
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{
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SPI_INT_TX_DATA = SPI_CFG1_TXEIE_Pos, /*!< TX data not full interrupt */
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SPI_INT_RX_DATA = SPI_CFG1_RXFIE_Pos, /*!< RX data not empty interrupt */
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SPI_INT_TRANSMIT_ERROR = SPI_CFG1_TXUIE_Pos, /*!< Transmit Error interrupt (TX underrun) */
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SPI_INT_RECEIVE_ERROR = SPI_CFG1_RXOIE_Pos, /*!< Receive Error interrupt (RX overrun) */
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SPI_INT_MODE_FAULT_ERROR = SPI_CFG1_MODFIE_Pos, /*!< Master mode fault error interrupt */
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SPI_INT_DATA_MATCH = SPI_CFG1_DMIE_Pos, /*!< Data match interrupt */
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} spi_interrupt_t;
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/*!
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* @brief SPI master or slave configuration.
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*/
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typedef enum
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{
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SPI_SLAVE = 0U, /*!< SPI peripheral operates in slave mode. */
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SPI_MASTER = 1U /*!< SPI peripheral operates in master mode. */
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} spi_master_slave_mode_t;
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/*!
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* @brief SPI pin (SOUT and SIN) configuration.
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*/
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typedef enum
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{
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SPI_SOUT_MOSI_SIN_MISO = 0U, /*!< SPI SOUT pin set as MOSI, SIN pin set as MISO */
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SPI_SOUT_MISO_SIN_MOSI /*!< SPI SOUT pin set as MISO, SIN pin set as MOSI */
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} spi_pin_config_t;
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/*!
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* @brief SPI delay type selection.
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*/
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typedef enum
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{
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SPI_SCK_TO_PCS = 0U, /*!< CS_SETUP: from the last SCK edge to the CS negation */
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SPI_PCS_TO_SCK = 1U, /*!< CS_HOLD: from the CS assertion to the first SCK edge */
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SPI_BETWEEN_TRANSFER = 2U /*!< CS_IDLE: from the CS assertion to the next CS negation */
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} spi_delay_type_t;
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/*!
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* @brief SPI hreq polarity type selection.
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*/
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typedef enum
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{
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SPI_HREQ_POLARITY_HIGH = 0U, /*!< SPI host request active polarity is high */
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SPI_HREQ_POLARITY_LOW /*!< SPI host request active polarity is low */
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} SPI_hreq_polarity_t;
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/* ========================================== Variables =========================================== */
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/* ==================================== Functions declaration ===================================== */
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/*!
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* @brief Clears the SPI status flag, which can write "1" to clear.
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*
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* @param[in] base: SPI base pointer
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* @param[in] statusFlag: Select which status will be cleared
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* @return STATUS_SUCCESS or STATUS_ERROR
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*/
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status_t SPI_ClearStatusFlag(SPI_Type *base, spi_status_flag_t statusFlag);
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/*!
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* @brief SPI Module softreset. And it only reset master engine/buffer/flag logic,
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* slave buffer/flag logic, the configuration of control registers(CFG0/
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* CFG1/CFG2/CMD) will not be reset.
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*
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* @param[in] base: SPI base pointer
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* @return none
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*/
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void SPI_SoftwareReset(SPI_Type *base);
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/*!
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* @brief Set CS_HOLD, CS_SETUP or CS_IDLE time.
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*
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* @param[in] base: SPI base pointer.
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* @param[in] whichDelay: Select which CS time
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* @param[in] delay: The 8-bit delay value 0x00 to 0xFF (255).
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* @return none
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*/
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void SPI_SetDelay(SPI_Type *base, spi_delay_type_t whichDelay, uint8_t delay);
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/*!
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* @brief Configures the SPI PCS polarity.
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*
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* @param[in] base: SPI base pointer
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* @param[in] whichPcs: Select which PCS to configured
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* -SPI_PCS0
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* -SPI_PCS1
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* -SPI_PCS2
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* -SPI_PCS3
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* @param[in] pcsPolarity: Set PCS as active high or low
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* -SPI_ACTIVE_LOW
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* -SPI_ACTIVE_HIGH
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* @return none
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*/
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void SPI_SetPcsPolarityMode(SPI_Type *base, spi_which_pcs_t whichPcs, spi_signal_polarity_t pcsPolarity);
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/*!
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* @brief Configure the SPI baud rate in bits per second.
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*
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* @param[in] base: SPI base pointer
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* @param[in] bitsPerSec: The desired baud rate in bits per second
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* @param[in] sourceClockInHz: SPI functional source input clock in Hertz
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* @return The actual calculated baud rate. This function may also return a "0" if the
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* bitPerSec is greater than sourceClockInHz/2
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*/
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uint32_t SPI_SetBaudRate(SPI_Type *base, uint32_t bitsPerSec, uint32_t sourceClockInHz);
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/*!
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* @brief Set SPI frame size(4~32 bits per frame).
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*
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* @param[in] base: SPI base pointer
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* @param[in] frameSize: SPI frame size, support 4~32 bits
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* -4: 4 bits
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* -5: 5 bits
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* -...
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* -32: 32 bits
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* @return none
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*/
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void SPI_SetFrameSize(SPI_Type *base, uint32_t frameSize);
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/* ===================================== Functions definition ===================================== */
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/*!
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* @brief Enable/Disable SPI module.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable/disable SPI module
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* @return none
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*/
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static inline void SPI_SetEnable(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CMD, SPI_CMD_SPIEN_Msk, SPI_CMD_SPIEN_Pos, enable);
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}
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/*!
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* @brief Check if SPI module is enabled.
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*
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* @param[in] base: SPI base pointer
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* @return SPI module is enabled or not
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* -true: SPI module is enabled
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* -false: SPI module is disabled
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*/
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static inline bool SPI_IsModuleEnabled(const SPI_Type *base)
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{
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return (bool)(((base->CMD) & SPI_CMD_SPIEN_Msk) >> SPI_CMD_SPIEN_Pos);
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}
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/*!
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* @brief Set SPI master or slave mode.
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*
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* @param[in] base: SPI base pointer
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* @param[in] mode: set SPI master mode
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* -SPI_MASTER: SPI master mode
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* -SPI_SLAVE: SPI slave mode
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* @return none
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*/
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static inline void SPI_SetMasterSlaveMode(SPI_Type *base, spi_master_slave_mode_t mode)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_MSTR_Msk, SPI_CFG1_MSTR_Pos, mode);
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}
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/*!
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* @brief Returns whether the SPI module is in master mode.
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*
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* @param[in] base: SPI base pointer
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* @return Returns the status of SPI master or slave mode
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* -true: SPI work in master mode
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* -false: SPI work in salve mode
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*/
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static inline bool SPI_IsMaster(const SPI_Type *base)
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{
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return (bool)(((base->CFG1) & SPI_CFG1_MSTR_Msk) >> SPI_CFG1_MSTR_Pos);
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}
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/*!
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* @brief Returns whether the SPI module is in Cs Continuous mode.
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*
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* @param[in] base：SPI base pointer
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* @return Returns the status of SPI Continuous or DisContinuous mode
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* -true: SPI work in Continuous mode
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* -false: SPI work in DisContinuous mode
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*/
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static inline bool SPI_IsCsContinuousMode(const SPI_Type *base)
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{
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return ((0U != ((base)->CFG1 & SPI_CFG1_CSOE_Msk)) && (0U != ((base)->CFG1 & SPI_CFG1_CONT_CS_Msk)));
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}
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/*!
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* @brief Gets the SPI status flag enable.
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*
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* @param[in] base: SPI base pointer
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* @param[in] statusFlag: Select which status will be return status
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* @return State of the status flag
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* -true: the status flag is "1"
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* -false: the status flag is "0"
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*/
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static inline bool SPI_GetStatusFlag(const SPI_Type *base, spi_status_flag_t statusFlag)
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{
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return (bool)(((base->STATUS) >> (uint8_t)statusFlag) & 1U);
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}
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/*!
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* @brief Configures the SPI interrupts.
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*
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* @param[in] base: SPI base pointer
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* @param[in] interruptSrc: The interrupt source, which will be enabled
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* @param[in] enable Enable or disable the interrupt source
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* @return none
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*/
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static inline void SPI_SetIntMode(SPI_Type *base, spi_interrupt_t interruptSrc, bool enable)
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{
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if (enable)
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{
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base->CFG1 |= (uint32_t)1U << (uint8_t)interruptSrc;
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}
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else
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{
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base->CFG1 &= ~((uint32_t)1U << (uint8_t)interruptSrc);
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}
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}
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/*!
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* @brief Returns if the SPI interrupt request is enabled or disabled.
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*
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* @param[in] base: SPI base pointer
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* @param[in] interruptSrc: The interrupt source, which will be enabled
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* @return Return the interrupt source enable status
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* -true: the interrupt source is enabled
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* -false: the interrupt source is disabled
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*/
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static inline bool SPI_GetIntMode(const SPI_Type *base, spi_interrupt_t interruptSrc)
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{
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return (bool)(((base->CFG1) >> (uint8_t)interruptSrc) & 1U);
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}
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/*!
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* @brief Enable/disable the SPI Transmit Data DMA request.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or disable the TX DMA request
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* @return none
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*/
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static inline void SPI_SetTxDmaCmd(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_DMATXEN_Msk, SPI_CFG1_DMATXEN_Pos, enable);
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}
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/*!
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* @brief Enable/disable the SPI Receive Data DMA request.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or disable the RX DMA request
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* @return none
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*/
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static inline void SPI_SetRxDmaCmd(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_DMARXEN_Msk, SPI_CFG1_DMARXEN_Pos, enable);
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}
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/*!
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* @brief Configures the SPI SOUT/SIN pin configuration mode.
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*
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* @param[in] base: SPI base pointer
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* @param[in] pinCfg: Select configuration for the SOUT/SIN pins (see spi_pin_config_t)
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* @return none
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*/
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static inline void SPI_SetPinConfigMode(SPI_Type *base, spi_pin_config_t pinCfg)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_PINCFG_Msk, SPI_CFG1_PINCFG_Pos, pinCfg);
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}
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/*!
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* @brief Set SPI CPHA.
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*
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* @param[in] base: SPI base pointer
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* @param[in] clkPhase: SPI clock CPHA
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* -SPI_CLOCK_PHASE_1ST_EDGE
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* -SPI_CLOCK_PHASE_2ND_EDGE
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* @return none
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*/
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static inline void SPI_SetCPHA(SPI_Type *base, spi_clock_phase_t clkPhase)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_CPHA_Msk, SPI_CFG1_CPHA_Pos, clkPhase);
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}
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/*!
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* @brief Set SPI CPOL.
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*
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* @param[in] base: SPI base pointer
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* @param[in] clkPolarity: SPI cpol select
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* - SPI_SCK_ACTIVE_HIGH
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* - SPI_SCK_ACTIVE_LOW
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* @return none
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*/
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static inline void SPI_SetCPOL(SPI_Type *base, spi_sck_polarity_t clkPolarity)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_CPOL_Msk, SPI_CFG1_CPOL_Pos, clkPolarity);
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}
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/*!
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* @brief Set SPI RX MSB first.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or isable SPI RX MSB first
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* -true: RX MSB
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* -false: RX LSB
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* @return none
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*/
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static inline void SPI_SetRxMSB(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_RMSBF_Msk, SPI_CFG1_RMSBF_Pos, enable);
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}
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/*!
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* @brief Set SPI TX MSB first.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or disable SPI TX MSB first
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* -true: TX MSB
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* -false: TX LSB
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* @return none
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*/
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static inline void SPI_SetTxMSB(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_MSBF_Msk, SPI_CFG1_MSBF_Pos, enable);
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}
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/*!
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* @brief Get SPI frame size.
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*
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* @param[in] base: SPI base pointer
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* @return The frame size, the value will be 4~32, corresponding to 4~32 bits
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*/
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static inline uint32_t SPI_GetFrameSize(SPI_Type *base)
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{
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return (((base->CFG1 & SPI_CFG1_FRMSIZE_Msk) >> SPI_CFG1_FRMSIZE_Pos) + 1U);
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}
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/*!
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* @brief Set SPI CS continuous or disContinuous mode.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or diaable SPI CS output continuous mode
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* -true: CS continuous mode
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* -false: CS disContinuous mode
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* @return none
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*/
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static inline void SPI_SetContinuousCS(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_CONT_CS_Msk, SPI_CFG1_CONT_CS_Pos, enable);
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}
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/*!
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* @brief Set SPI CS output enable
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or diaable SPI CS hardware output
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* -true: enable the CS hardware output(CS control by hardware)
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* -false: disable the CS hardware output(CS control by software)
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* @return none
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*/
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static inline void SPI_SetCSOE(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_CSOE_Msk, SPI_CFG1_CSOE_Pos, enable);
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}
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/*!
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* @brief Enable/Disable SPI CS mode fault detect function.
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*
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* @param[in] base: SPI base pointer
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* @param[in] enable: Enable or disable SPI CS mode fault detect function
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* -true: enable the master mode fault detect function
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* -false: disable the master mode fault detect function
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* @return none
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*/
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static inline void SPI_SetModeFault(SPI_Type *base, bool enable)
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{
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MODIFY_REG32(base->CFG1, SPI_CFG1_MODFEN_Msk, SPI_CFG1_MODFEN_Pos, enable);
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}
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/*!
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* @brief Release SPI CS, which will be changed to inactive enable.
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*
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* @param[in] base: SPI base pointer
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* @return none
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*/
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static inline void SPI_ReleaseCS(SPI_Type *base)
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{
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SET_BIT32(base->CMD, SPI_CMD_CSRLS_Msk);
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}
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/*!
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* @brief Set SPI match data.
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*
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* @param[in] base: SPI base pointer
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* @return none
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*/
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static inline void SPI_SetMatchData(SPI_Type *base, uint32_t data)
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{
|
||
WRITE_REG32(base->DMV, data);
|
||
}
|
||
|
||
/*!
|
||
* @brief Sets the PCS flag to the value of the whichPcs parameter.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] whichPcs: Select which CS is assert
|
||
* -SPI_PCS0
|
||
* -SPI_PCS1
|
||
* -SPI_PCS2
|
||
* -SPI_PCS3
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetPcs(SPI_Type *base, spi_which_pcs_t whichPcs)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_PCSCFG_Msk, SPI_CFG2_PCSCFG_Pos, whichPcs);
|
||
}
|
||
|
||
/*!
|
||
* @brief Set SPI transfer data width.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] dataWidth: transfer data width
|
||
* - SPI_DATA_WIDTH_1BIT
|
||
* - SPI_DATA_WIDTH_2BIT
|
||
* - SPI_DATA_WIDTH_4BIT
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetDataWidth(SPI_Type *base, spi_transfer_width_t dataWidth)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_WIDTH_Msk, SPI_CFG2_WIDTH_Pos, dataWidth);
|
||
}
|
||
|
||
/*!
|
||
* @brief Writes data into the TX data register.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] data: The data word to be sent
|
||
* @return none
|
||
*/
|
||
static inline void SPI_WriteData(SPI_Type *base, uint32_t data)
|
||
{
|
||
base->DATA = data;
|
||
}
|
||
|
||
/*!
|
||
* @brief Reads data from the data register.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @return The RX data read from the data register
|
||
*/
|
||
static inline uint32_t SPI_ReadData(const SPI_Type *base)
|
||
{
|
||
return (uint32_t)base->DATA;
|
||
}
|
||
|
||
/*!
|
||
* @brief Config Master no overflow mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] enable: Enable or disable SPI no over flow mode
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetMasterNoOverflowMode(SPI_Type *base, bool enable)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_MNOV_Msk, SPI_CFG2_MNOV_Pos, enable);
|
||
}
|
||
|
||
/*!
|
||
* @brief Enable/Disable TX Only mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] enable: enable/disable SPI TX only mode
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetTxOnly(SPI_Type *base, bool enable)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_TOEN_Msk, SPI_CFG2_TOEN_Pos, enable);
|
||
}
|
||
|
||
/*!
|
||
* @brief Get TX Only mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @return SPI TX only mode is enabled/disabled
|
||
*/
|
||
static inline bool SPI_GetTxOnly(SPI_Type *base)
|
||
{
|
||
return (bool)(((base->CFG2) >> (uint8_t)SPI_CFG2_TOEN_Pos) & 1U);
|
||
}
|
||
|
||
/*!
|
||
* @brief Enable/Disable RX Only mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] enable: enable/disable SPI RX only mode
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetRxOnly(SPI_Type *base, bool enable)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_ROEN_Msk, SPI_CFG2_ROEN_Pos, enable);
|
||
}
|
||
|
||
/*!
|
||
* @brief Get RX Only mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @return SPI RX only mode is enabled/disabled
|
||
*/
|
||
static inline bool SPI_GetRxOnly(SPI_Type *base)
|
||
{
|
||
return (bool)(((base->CFG2) >> (uint8_t)SPI_CFG2_ROEN_Pos) & 1U);
|
||
}
|
||
|
||
/*!
|
||
* @brief Start Master Receive With RX Only Mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @return none
|
||
*/
|
||
static inline void SPI_RxOnlyModeTrig(SPI_Type *base)
|
||
{
|
||
SET_BIT32(base->CMD, SPI_CMD_ROTRIG_Msk);
|
||
}
|
||
|
||
/*!
|
||
* @brief Set SPI host request polarity.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] hreqPolarity: host request polarity
|
||
* -SPI_HREQ_POLARITY_LOW
|
||
* -SPI_HREQ_POLARITY_HIGH
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetHreqPolarity(SPI_Type *base, SPI_hreq_polarity_t hreqPolarity)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_HRPOL_Msk, SPI_CFG2_HRPOL_Pos, hreqPolarity);
|
||
}
|
||
|
||
/*!
|
||
* @brief Enable or disable SPI host request.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] enable: Enable or disable SPI host request
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetHreq(SPI_Type *base, bool enable)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_HREN_Msk, SPI_CFG2_HREN_Pos, enable);
|
||
}
|
||
|
||
/*!
|
||
* @brief Enable or disable SPI in debug mode.
|
||
*
|
||
* @param[in] base: SPI base pointer
|
||
* @param[in] enable: Enable or disable SPI in debug mode
|
||
* @return none
|
||
*/
|
||
static inline void SPI_SetDebug(SPI_Type *base, bool enable)
|
||
{
|
||
MODIFY_REG32(base->CFG2, SPI_CFG2_DBGEN_Msk, SPI_CFG2_DBGEN_Pos, enable);
|
||
}
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif /* __cplusplus */
|
||
|
||
#endif /* SPI_HW_H */
|
||
|
||
/* ============================================= EOF ============================================== */
|