531 lines
17 KiB
C
531 lines
17 KiB
C
/* Copyright Statement:
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*
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* This software/firmware and related documentation ("AutoChips Software") are
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* protected under relevant copyright laws. The information contained herein is
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* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
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* the prior written permission of AutoChips inc. and/or its licensors, any
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* reproduction, modification, use or disclosure of AutoChips Software, and
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* information contained herein, in whole or in part, shall be strictly
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* prohibited.
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*
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* AutoChips Inc. (C) 2021. All rights reserved.
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*
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* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
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* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
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* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
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* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
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* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
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* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
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* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
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* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
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* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
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* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
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* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
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* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
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* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
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* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
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* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
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* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
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*/
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/*!
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* @file dma_hw.h
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*
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* @brief This file provides dma hardware integration interface.
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*
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*/
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/* PRQA S 4304 EOF */ /* Type conversion. */
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#ifndef DMA_HW_H
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#define DMA_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/* =========================================== Includes =========================================== */
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#include "dma_drv.h"
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/* ============================================ Define ============================================ */
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/* =========================================== Typedef ============================================ */
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/* ========================================== Variables =========================================== */
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/* ==================================== Functions declaration ===================================== */
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/*!
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* @brief Clear DMA channel interrupt status.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return The interrupt status flags in register before cleared by software
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*/
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uint32_t DMA_ClearIntStatus(DMA_ChannelType *base);
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/* ===================================== Functions definition ===================================== */
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/*!
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* @brief Enable/Disable DMA channel
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: Enable/Disable DMA channel
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* @return none
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*/
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static inline void DMA_SetChannel(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->CHAN_ENABLE, DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Msk, \
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DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Pos, enable);
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}
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/*!
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* @brief DMA Top warm reset
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*
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* @param[in] none
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* @return none
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*/
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static inline void DMA_TopWarmRst(void)
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{
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DMA0_TOP_RST->TOP_RST |= DMA_TOP_RST_WARM_RST_Msk;
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}
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/*!
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* @brief DMA_Top Hard reset
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*
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* @param[in] none
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* @return none
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*/
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static inline void DMA_TopHardRst(void)
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{
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DMA0_TOP_RST->TOP_RST |= DMA_TOP_RST_HARD_RST_Msk;
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DMA0_TOP_RST->TOP_RST &= ~DMA_TOP_RST_HARD_RST_Msk;
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}
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/*!
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* @brief DMA channel warm reset.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return none
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*/
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static inline void DMA_ChannelWarmRst(DMA_ChannelType *base)
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{
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base->RST |= DMA_CHANNEL_RST_WARM_RST_Msk;
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}
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/*!
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* @brief DMA channel hard reset.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return none
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*/
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static inline void DMA_ChannelHardRst(DMA_ChannelType *base)
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{
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base->RST |= DMA_CHANNEL_RST_HARD_RST_Msk;
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base->RST &= ~DMA_CHANNEL_RST_HARD_RST_Msk;
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}
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/*!
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* @brief Set DMA channel source start address.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] startAddr: DMA source start address, 32bit
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* @return none
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*/
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static inline void DMA_SetSrcStartAddr(DMA_ChannelType *base, uint32_t startAddr)
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{
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WRITE_REG32(base->SSTART_ADDR, startAddr);
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}
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/*!
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* @brief Set DMA channel source end address.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] srcEndAddr:DMA source end address, 32bit
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* @return none
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*/
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static inline void DMA_SetSrcEndAddr(DMA_ChannelType *base, uint32_t srcEndAddr)
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{
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WRITE_REG32(base->SEND_ADDR, srcEndAddr);
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}
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/*!
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* @brief Set DMA channel destination start address.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] destStartAddr:DMA destination start address, 32bit
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* @return none
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*/
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static inline void DMA_SetDestStartAddr(DMA_ChannelType *base, uint32_t destStartAddr)
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{
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WRITE_REG32(base->DSTART_ADDR, destStartAddr);
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}
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/*!
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* @brief Set DMA channel destination end address.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] destEndAddr: DMA destination end address, 32bit
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* @return none
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*/
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static inline void DMA_SetDestEndAddr(DMA_ChannelType *base, uint32_t destEndAddr)
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{
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WRITE_REG32(base->DEND_ADDR, destEndAddr);
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}
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/*!
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* @brief Set DMA channel source transfer size.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] srcTransferSize: DMA channel source transfer size
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* -DMA_TRANSFER_SIZE_1B
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* -DMA_TRANSFER_SIZE_2B
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* -DMA_TRANSFER_SIZE_4B
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* @return none
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*/
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static inline void DMA_SetSrcTransferSize(DMA_ChannelType *base, dma_transfer_size_t srcTransferSize)
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{
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MODIFY_REG32(base->CONFIG, DMA_CHANNEL_CONFIG_SSIZE_Msk, \
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DMA_CHANNEL_CONFIG_SSIZE_Pos, srcTransferSize);
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}
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/*!
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* @brief Set DMA channel destination transfer size.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] destTransferSize: DMA channel destination transfer size
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* -DMA_TRANSFER_SIZE_1B
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* -DMA_TRANSFER_SIZE_2B
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* -DMA_TRANSFER_SIZE_4B
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* @return none
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*/
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static inline void DMA_SetDestTransferSize(DMA_ChannelType *base, dma_transfer_size_t destTransferSize)
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{
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MODIFY_REG32(base->CONFIG, DMA_CHANNEL_CONFIG_DSIZE_Msk, \
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DMA_CHANNEL_CONFIG_DSIZE_Pos, destTransferSize);
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}
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/*!
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* @brief Set DMA channel source address offset.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] srcOffset: source address offset
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* @return none
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*/
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static inline void DMA_SetSrcAddrOffSet(DMA_ChannelType *base, uint16_t srcOffset)
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{
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MODIFY_REG32(base->ADDR_OFFSET, DMA_CHANNEL_ADDR_OFFSET_SOFFSET_Msk, \
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DMA_CHANNEL_ADDR_OFFSET_SOFFSET_Pos, srcOffset);
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}
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/*!
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* @brief Set DMA destination address offset.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] destOffset: destination address offset
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* @return none
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*/
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static inline void DMA_SetDestAddrOffSet(DMA_ChannelType *base, uint16_t destOffset)
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{
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MODIFY_REG32(base->ADDR_OFFSET, DMA_CHANNEL_ADDR_OFFSET_DOFFSET_Msk, \
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DMA_CHANNEL_ADDR_OFFSET_DOFFSET_Pos, destOffset);
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}
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/*!
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* @brief Set DMA channel transfer length by bytes.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] bytesLength: DMA channel transfer length(0~32767 byte, bit 15 should be 0)
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* @return none
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*/
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static inline void DMA_SetTranferLength(DMA_ChannelType *base, uint16_t bytesLength)
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{
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MODIFY_REG32(base->CHAN_LENGTH, DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Msk, \
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DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Pos, bytesLength);
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}
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/*!
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* @brief Get DMA channel total transfer length by bytes.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return DMA channel transfer length
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*/
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static inline uint32_t DMA_GetTranferLength(DMA_ChannelType *base)
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{
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return (base->CHAN_LENGTH & DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Msk);
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}
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/*!
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* @brief Get number of bytes transfered by DMA channel
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return DMA channel transfered bytes number
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*/
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static inline uint32_t DMA_GetTransferedBytes(DMA_ChannelType *base)
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{
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return (base->DATA_TRANS_NUM & DMA_CHANNEL_DATA_TRANS_NUM_DATA_TRANS_NUM_Msk);
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}
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/*!
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* @brief Set DMA channel priority.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] channelPriority: DMA chanenl priority
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* -DMA_CHN_PRIORITY_LOW
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* -DMA_CHN_PRIORITY_MEDIUM
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* -DMA_CHN_PRIORITY_HIGH
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* -DMA_CHN_PRIORITY_VERY_HIGH
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* @return none
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*/
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static inline void DMA_SetChannelPriority(DMA_ChannelType *base, dma_channel_priority_t channelPriority)
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{
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MODIFY_REG32(base->CONFIG, DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Msk, \
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DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Pos, channelPriority);
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}
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/*!
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* @brief Set DMA channel circular mode
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: enable/disable DMA channel circular mode
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* @return none
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*/
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static inline void DMA_SetCircularMode(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->CONFIG, DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Msk, \
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DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Pos, enable);
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}
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/*!
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* @brief Set DMA channel FIFO move fast function.
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* When DMA read from peripheral, it must be disable FIFO fast function.
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* When DMA read from memory, it must be enable FIFO fast function.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: Enable or disable move data to FIFO early
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* -true: move data to DMA FIFO early, ignored DMA request
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* -false: move data to DMA FIFO by DMA request
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* @return none
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*/
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static inline void DMA_SetFIFOFastFunction(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->CONFIG, DMA_CHANNEL_CONFIG_CHAN_DIR_Msk, \
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DMA_CHANNEL_CONFIG_CHAN_DIR_Pos, enable);
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}
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/*!
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* @brief Get the number of the data left in the DMA channel's internal FIFO
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return DMA Channel FIFO left data bytes number
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*/
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static inline uint32_t DMA_GetInterFIFODataLeftBytes(DMA_ChannelType *base)
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{
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return (base->FIFO_LEFT_NUM & DMA_CHANNEL_FIFO_LEFT_NUM_FIFO_LEFT_NUM_Msk);
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}
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/*!
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* @brief Flush DMA channel data
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @return none
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*/
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static inline void DMA_FlushChannelFIFO(DMA_ChannelType *base)
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{
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SET_BIT32(base->RST, DMA_CHANNEL_RST_FLUSH_Msk);
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}
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/*!
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* @brief Enable/Disable DMA channel transfer finish interrupt
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: enable/disable DMA channel finish interrupt
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* @return none
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*/
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static inline void DMA_SetFinishInterrupt(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->INTEN, DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Msk, \
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DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Pos, enable);
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}
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/*!
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* @brief Enable DMA channel Error interrupt
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: enable/disable DMA transfer Error interrupt
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* - ENABLE
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* - DISABLE
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* @return none
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*/
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static inline void DMA_SetErrorInterrupt(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->INTEN, DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Msk, \
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DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Pos, enable);
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}
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/*!
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* @brief Configure DMA channel trigger from CTU module.
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* Only DMA channel 0~3 support trigger function.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: Enable or disable DMA channel trigger
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*/
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static inline void DMA_SetChannelTrigger(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->DMAMUX_CFG, DMA_CHANNEL_DMAMUX_CFG_TRIG_EN_Msk, \
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DMA_CHANNEL_DMAMUX_CFG_TRIG_EN_Pos, enable);
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}
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/*!
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* @brief Configures the DMA request for the DMA channel.
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] source: DMA request source.The DMA request sources(dma_request_source_t)
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* are defined in the file dma_drv.h
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*/
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static inline void DMA_SetChannelSource(DMA_ChannelType *base, uint8_t source)
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{
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MODIFY_REG32(base->DMAMUX_CFG, DMA_CHANNEL_DMAMUX_CFG_REQ_ID_Msk, \
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DMA_CHANNEL_DMAMUX_CFG_REQ_ID_Pos, source);
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}
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/*!
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* @brief Set DMA debug function
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*
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* @param[in] base: Base address for DMA channel
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* -DMA0_CHANNEL0
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* -DMA0_CHANNEL1
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* -...
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* -DMA0_CHANNEL15
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* @param[in] enable: enable or disable debug fucntion
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* -true: In debug mode, DMA continues to operate
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* -false: In debug mode, DMA will be disabled when CPU is halted
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* @return none
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*/
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static inline void DMA_SetChannelDebug(DMA_ChannelType *base, bool enable)
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{
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MODIFY_REG32(base->CHAN_ENABLE, DMA_CHANNEL_CHAN_ENABLE_EDBG_Msk, DMA_CHANNEL_CHAN_ENABLE_EDBG_Pos, enable);
|
|
}
|
|
|
|
/*!
|
|
* @brief DMA channel transfer pause/resume
|
|
*
|
|
* @param[in] base: Base address for DMA channel
|
|
* -DMA0_CHANNEL0
|
|
* -DMA0_CHANNEL1
|
|
* -...
|
|
* -DMA0_CHANNEL15
|
|
* @param[in] enable: enable/disable DMA paulse
|
|
* - true: DMA channel transfer pause
|
|
* - false: DMA channel transfer resume
|
|
* @return none
|
|
*/
|
|
static inline void DMA_SetChannelPause(DMA_ChannelType *base, bool enable)
|
|
{
|
|
MODIFY_REG32(base->STOP, DMA_CHANNEL_STOP_STOP_Msk, DMA_CHANNEL_STOP_STOP_Pos, enable);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif /* __cplusplus */
|
|
|
|
#endif /* DMA_HW_H*/
|
|
|
|
/* ============================================= EOF ============================================== */
|