Общие изменения
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cfif
commit
1b98f03828
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//
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// Created by cfif on 17.11.22.
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//
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#ifndef ADC_ARTERY_H
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#define ADC_ARTERY_H
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#include "AdcIO.h"
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#include "cmsis_os2.h"
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#include CMSIS_device_header
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#include "gpio_drv.h"
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#include "adc_drv.h"
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#include "dma_drv.h"
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typedef struct {
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uint8_t ADC0_CHANNEL_NUM;
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uint8_t ADC1_CHANNEL_NUM;
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adc_converter_config_t adc0Config;
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adc_converter_config_t adc1Config;
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dma_state_t g_dma_state;
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dma_chn_state_t g_dma_adc0_state;
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dma_chn_state_t g_dma_adc1_state;
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uint16_t g_adc0_array[32];
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uint16_t g_adc1_array[32];
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} tAdcGlobalAC7840x;
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typedef struct {
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int32_t offset;
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double mux;
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double div;
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uint8_t index;
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uint16_t *g_adc_array;
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#ifdef ACCESS_ADC
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osMutexId_t access;
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#endif
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} tAdcAC7840x;
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tAdcAC7840x ADC_Initial(
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tAdcAC7840x *env,
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PORT_Type *port,
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uint32_t pinMask,
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adc_inputchannel_t channel,
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int32_t offset,
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double mux,
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double div
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);
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tAdcIO vAdcGetIo(tAdcAC7840x *env);
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#endif //ADC_ARTERY_H
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//
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// Created by cfif on 07.09.22.
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//
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#include <SystemDelayInterface.h>
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#include "Adc_AC7840x.h"
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#define ADC0_INDEX (0U)
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#define ADC1_INDEX (1U)
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#define ADC0_DMA_CHANNEL (0U)
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#define ADC1_DMA_CHANNEL (1U)
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tAdcGlobalAC7840x adcGlobalAC7840x;
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void DmaInit() {
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dma_channel_config_t dma_adc0_config;
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dma_channel_config_t dma_adc1_config;
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DMA_DRV_Init(&adcGlobalAC7840x.g_dma_state, NULL, NULL, 0);
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dma_adc0_config.channelPriority = DMA_CHN_PRIORITY_LOW;
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dma_adc0_config.virtChnConfig = ADC0_DMA_CHANNEL;
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dma_adc0_config.source = DMA_REQ_ADC0;
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dma_adc0_config.callback = NULL;
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dma_adc0_config.enableTrigger = false;
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DMA_DRV_ChannelInit(&adcGlobalAC7840x.g_dma_adc0_state, &dma_adc0_config);
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dma_adc1_config.channelPriority = DMA_CHN_PRIORITY_LOW;
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dma_adc1_config.virtChnConfig = ADC1_DMA_CHANNEL;
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dma_adc1_config.source = DMA_REQ_ADC1;
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dma_adc1_config.callback = NULL;
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dma_adc1_config.enableTrigger = false;
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DMA_DRV_ChannelInit(&adcGlobalAC7840x.g_dma_adc1_state, &dma_adc1_config);
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}
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void ADC0_DmaStart() {
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DMA_DRV_ConfigTransfer(ADC0_DMA_CHANNEL, DMA_TRANSFER_PERIPH2MEM, (uint32_t) (ADC0->RDR),
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(uint32_t) adcGlobalAC7840x.g_adc0_array, DMA_TRANSFER_SIZE_2B,
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adcGlobalAC7840x.ADC0_CHANNEL_NUM * 2);
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DMA_DRV_SetSrcAddr(ADC0_DMA_CHANNEL, (uint32_t) (&(ADC0->RDR[0])),
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(uint32_t) (&(ADC0->RDR[adcGlobalAC7840x.ADC0_CHANNEL_NUM])));
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DMA_DRV_SetSrcOffset(ADC0_DMA_CHANNEL, 4);
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DMA_DRV_SetCircularMode(ADC0_DMA_CHANNEL, true);
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DMA_DRV_StartChannel(ADC0_DMA_CHANNEL);
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ADC_DRV_SoftwareStartRegularConvert(ADC0_INDEX);
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}
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void ADC1_DmaStart() {
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DMA_DRV_ConfigTransfer(ADC1_DMA_CHANNEL, DMA_TRANSFER_PERIPH2MEM, (uint32_t) (ADC1->RDR),
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(uint32_t) adcGlobalAC7840x.g_adc1_array, DMA_TRANSFER_SIZE_2B,
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adcGlobalAC7840x.ADC1_CHANNEL_NUM * 2);
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DMA_DRV_SetSrcAddr(ADC1_DMA_CHANNEL, (uint32_t) (&(ADC1->RDR[0])),
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(uint32_t) (&(ADC1->RDR[adcGlobalAC7840x.ADC1_CHANNEL_NUM])));
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DMA_DRV_SetSrcOffset(ADC1_DMA_CHANNEL, 4);
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DMA_DRV_SetCircularMode(ADC1_DMA_CHANNEL, true);
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DMA_DRV_StartChannel(ADC1_DMA_CHANNEL);
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ADC_DRV_SoftwareStartRegularConvert(ADC1_INDEX);
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}
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void ADC_ConfigChannel(const uint32_t instance, const adc_sequence_t seq, adc_inputchannel_t channel) {
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// ADCCLK = FCLK/clockDivide = 60/6 = 10MHz
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// = (SPT+ resolution12/10/8) ADCCLK + 5 FCLK = (5+12)/10+5/60 - 1.78us
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// 12bit - 1Msps 10bit - 1.2Msps 8bit - 1.4Msps
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adc_chan_config_t adcChConfig;
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ADC_DRV_InitChanStruct(&adcChConfig);
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adcChConfig.channel = channel;
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adcChConfig.spt = ADC_SPT_CLK_5;
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adcChConfig.interruptEn = false;
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ADC_DRV_ConfigChan(instance, seq, &adcChConfig);
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}
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tAdcAC7840x ADC0_Add(PORT_Type *port, uint32_t pinMask, adc_sequence_t sequence, adc_inputchannel_t channel,
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int32_t offset, double mux, double div) {
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GPIO_DRV_SetMuxModeSel(port, pinMask, PORT_PIN_DISABLED);
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++adcGlobalAC7840x.ADC0_CHANNEL_NUM;
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adcGlobalAC7840x.adc0Config.regularSequenceLength = adcGlobalAC7840x.ADC0_CHANNEL_NUM;
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ADC_ConfigChannel(ADC0_INDEX, sequence, channel);
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#ifdef ACCESS_ADC
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tAdcAC7840x adc = {
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.offset = offset,
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.div = div,
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.mux = mux,
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.index = adcGlobalAC7840x.ADC0_CHANNEL_NUM,
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.g_adc_array = adcGlobalAC7840x.g_adc0_array,
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.access = osMutexNew(NULL)
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};
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#else
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tAdcAC7840x adc = {
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.offset = offset,
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.div = div,
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.mux = mux,
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.index = adcGlobalAC7840x.ADC1_CHANNEL_NUM,
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.g_adc_array = adcGlobalAC7840x.g_adc0_array,
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};
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#endif
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return adc;
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}
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tAdcAC7840x ADC1_Add(PORT_Type *port, uint32_t pinMask, adc_sequence_t sequence, adc_inputchannel_t channel,
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int32_t offset, double mux, double div) {
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GPIO_DRV_SetMuxModeSel(port, pinMask, PORT_PIN_DISABLED);
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++adcGlobalAC7840x.ADC1_CHANNEL_NUM;
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adcGlobalAC7840x.adc0Config.regularSequenceLength = adcGlobalAC7840x.ADC1_CHANNEL_NUM;
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ADC_ConfigChannel(ADC1_INDEX, sequence, channel);
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#ifdef ACCESS_ADC
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tAdcAC7840x adc = {
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.offset = offset,
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.div = div,
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.mux = mux,
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.index = adcGlobalAC7840x.ADC1_CHANNEL_NUM,
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.g_adc_array = adcGlobalAC7840x.g_adc1_array,
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.access = osMutexNew(NULL)
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};
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#else
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tAdcAC7840x adc = {
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.ADCx = ADCx,
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.ADC_Channel = ADC_Channel,
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.offset = offset,
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.div = div,
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.mux = mux,
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.index = adcGlobalAC7840x.ADC1_CHANNEL_NUM,
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.g_adc_array = adcGlobalAC7840x.g_adc1_array,
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};
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#endif
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return adc;
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}
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void ADC_StartInit(tAdcAC7840x *env) {
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adcGlobalAC7840x.ADC0_CHANNEL_NUM = 0;
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ADC_DRV_Init(ADC0_INDEX);
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ADC_DRV_InitConverterStruct(&adcGlobalAC7840x.adc0Config);
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adcGlobalAC7840x.adc0Config.clockDivide = ADC_CLK_DIVIDE_6;
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adcGlobalAC7840x.adc0Config.resolution = ADC_RESOLUTION_12BIT;
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adcGlobalAC7840x.adc0Config.regularTrigger = ADC_TRIGGER_INTERNAL;
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adcGlobalAC7840x.adc0Config.injectTrigger = ADC_TRIGGER_INTERNAL;
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adcGlobalAC7840x.adc0Config.dmaEnable = true;
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adcGlobalAC7840x.adc0Config.voltageRef = ADC_VOLTAGEREF_VREF;
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adcGlobalAC7840x.adc0Config.scanModeEn = true;
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adcGlobalAC7840x.adc0Config.continuousModeEn = true;
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adcGlobalAC7840x.adc0Config.regularDiscontinuousModeEn = false;
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adcGlobalAC7840x.adc0Config.injectDiscontinuousModeEn = false;
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adcGlobalAC7840x.adc0Config.injectAutoModeEn = false;
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adcGlobalAC7840x.adc0Config.intervalModeEn = false;
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adcGlobalAC7840x.adc0Config.regularDiscontinuousNum = 0;
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adcGlobalAC7840x.adc0Config.regularSequenceLength = adcGlobalAC7840x.ADC0_CHANNEL_NUM;
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adcGlobalAC7840x.adc0Config.injectSequenceLength = 0;
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adcGlobalAC7840x.adc0Config.powerEn = true;
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adcGlobalAC7840x.ADC1_CHANNEL_NUM = 0;
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ADC_DRV_Init(ADC1_INDEX);
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ADC_DRV_InitConverterStruct(&adcGlobalAC7840x.adc1Config);
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adcGlobalAC7840x.adc1Config.clockDivide = ADC_CLK_DIVIDE_6;
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adcGlobalAC7840x.adc1Config.resolution = ADC_RESOLUTION_12BIT;
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adcGlobalAC7840x.adc1Config.regularTrigger = ADC_TRIGGER_INTERNAL;
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adcGlobalAC7840x.adc1Config.injectTrigger = ADC_TRIGGER_INTERNAL;
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adcGlobalAC7840x.adc1Config.dmaEnable = true;
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adcGlobalAC7840x.adc1Config.voltageRef = ADC_VOLTAGEREF_VREF;
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adcGlobalAC7840x.adc1Config.scanModeEn = true;
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adcGlobalAC7840x.adc1Config.continuousModeEn = true;
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adcGlobalAC7840x.adc1Config.regularDiscontinuousModeEn = false;
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adcGlobalAC7840x.adc1Config.injectDiscontinuousModeEn = false;
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adcGlobalAC7840x.adc1Config.injectAutoModeEn = false;
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adcGlobalAC7840x.adc1Config.intervalModeEn = false;
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adcGlobalAC7840x.adc1Config.regularDiscontinuousNum = 0;
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adcGlobalAC7840x.adc1Config.regularSequenceLength = adcGlobalAC7840x.ADC1_CHANNEL_NUM;
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adcGlobalAC7840x.adc1Config.injectSequenceLength = 0;
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adcGlobalAC7840x.adc1Config.powerEn = true;
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}
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void ADC_EndInit() {
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ADC_DRV_ConfigConverter(ADC0_INDEX, &adcGlobalAC7840x.adc0Config);
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ADC_DRV_ConfigConverter(ADC1_INDEX, &adcGlobalAC7840x.adc1Config);
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}
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static uint32_t vAdcGet(tAdcAC7840x *env) {
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#ifdef ACCESS_ADC
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if (osMutexAcquire(env->access, 100) == osOK) {
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volatile uint16_t data = env->g_adc_array[env->index];
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int32_t projected = (int32_t) ((double) (data + env->offset) * env->mux / env->div);
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osMutexRelease(env->access);
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return projected;
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} else {
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return 0;
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}
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#else
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volatile uint16_t data = env->g_adc_array[env->index];
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int32_t projected = ((data + env->offset) * env->mux / env->div);
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return projected;
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#endif
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}
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tAdcIO vAdcGetIo(tAdcAC7840x *env) {
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tAdcIO io = {
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.env = env,
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.get = (AdcIOTransaction) vAdcGet,
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};
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return io;
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}
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@ -0,0 +1,17 @@
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{
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"dep": [
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{
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"type": "git",
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"provider": "Smart_Components",
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"repo": "Adc"
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}
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],
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"cmake": {
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"inc_dirs": [
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"Inc"
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],
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"srcs": [
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"Src/**.c"
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]
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}
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}
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