From 5f978bb112e7e9c0819a21ae0390f8af37e7db23 Mon Sep 17 00:00:00 2001 From: cfif Date: Thu, 29 May 2025 13:52:39 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9F=D0=B5=D1=80=D0=B5=D0=BD=D0=BE=D1=81=20?= =?UTF-8?q?=D0=BD=D0=B0=20=D0=BD=D0=BE=D0=B2=D1=83=D1=8E=20=D0=BF=D0=BB?= =?UTF-8?q?=D0=B0=D1=82=D1=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- APP/AT32F437xM_FLASH.ld | 175 +++++++++++ APP/FreeRTOSConfig.h | 176 ++++++++++++ APP/at32f435_437_clock.c | 113 ++++++++ APP/at32f435_437_clock.h | 46 +++ APP/at32f435_437_conf.h | 191 +++++++++++++ APP/at32f435_437_int.c | 148 ++++++++++ APP/at32f435_437_int.h | 58 ++++ APP/delay_sec.c | 92 ++++++ APP/delay_sec.h | 14 + APP/lwipopts.h | 103 +++++++ APP/main.c | 300 +++++++++++++++++++ APP/main.h | 61 ++++ APP/modular.json | 11 + APP/startup_at32f435_437.s | 573 +++++++++++++++++++++++++++++++++++++ CMakeLists.txt | 79 +++++ modular.json | 149 ++++++++++ stm32f427.cfg | 27 ++ 17 files changed, 2316 insertions(+) create mode 100755 APP/AT32F437xM_FLASH.ld create mode 100644 APP/FreeRTOSConfig.h create mode 100644 APP/at32f435_437_clock.c create mode 100644 APP/at32f435_437_clock.h create mode 100644 APP/at32f435_437_conf.h create mode 100644 APP/at32f435_437_int.c create mode 100644 APP/at32f435_437_int.h create mode 100644 APP/delay_sec.c create mode 100644 APP/delay_sec.h create mode 100644 APP/lwipopts.h create mode 100755 APP/main.c create mode 100755 APP/main.h create mode 100755 APP/modular.json create mode 100644 APP/startup_at32f435_437.s create mode 100755 CMakeLists.txt create mode 100755 modular.json create mode 100755 stm32f427.cfg diff --git a/APP/AT32F437xM_FLASH.ld b/APP/AT32F437xM_FLASH.ld new file mode 100755 index 0000000..9b6f618 --- /dev/null +++ b/APP/AT32F437xM_FLASH.ld @@ -0,0 +1,175 @@ +/* +***************************************************************************** +** +** File : AT32F437xM_FLASH.ld +** +** Abstract : Linker script for AT32F437xM Device with +** 4096KByte FLASH, 384KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : Artery Tek AT32 +** +** Environment : Arm gcc toolchain +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20080000; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +_FullBootloaderSize = 896K ; +_MetadataSize = 256 ; +_BootloaderSize = _FullBootloaderSize - _MetadataSize ; +_BootloaderBegin = 0x08000000; + + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = _BootloaderBegin, LENGTH = _BootloaderSize + META (rx) : ORIGIN = _BootloaderBegin + _BootloaderSize, LENGTH = _MetadataSize + MAIN_FIRMWARE (rx) : ORIGIN = 0x08100000, LENGTH = 1024K + UPDATE_FIRMWARE (rx) : ORIGIN = 0x08260000, LENGTH = 1024K + SETTINGS_STORAGE (rx) : ORIGIN = 0x083C0000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + .metaaaa : SUBALIGN(1) + { + KEEP(*(.meta_fw_crc)) + LONG(_BootloaderSize) ; /* word with firmware_size */ + KEEP(*(.meta_fw_name_size)) + KEEP(*(.meta_fw_name)) + KEEP(*(.meta_hw_name_size)) + KEEP(*(.meta_hw_name)) + . = ALIGN(256); + } >META + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/APP/FreeRTOSConfig.h b/APP/FreeRTOSConfig.h new file mode 100644 index 0000000..d0b27e7 --- /dev/null +++ b/APP/FreeRTOSConfig.h @@ -0,0 +1,176 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + +#include + +extern uint32_t SystemCoreClock; +#endif + +#ifndef CMSIS_device_header +//#define CMSIS_device_header "niietcm4.h" +#define CMSIS_device_header "at32f435_437.h" +#endif /* CMSIS_device_header */ + +//#include "niietcm4.h" +#include "at32f435_437.h" + +#define configCHECK_FOR_STACK_OVERFLOW 1 + +#define configENABLE_FPU 1 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( system_core_clock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)64) +#define configTOTAL_HEAP_SIZE ((size_t)104000) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 128 + +/* CMSIS-RTOS V2 flags */ +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#define configUSE_OS2_THREAD_ENUMERATE 1 +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#define configUSE_OS2_THREAD_FLAGS 1 +#define configUSE_OS2_TIMER 1 +#define configUSE_OS2_MUTEX 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/APP/at32f435_437_clock.c b/APP/at32f435_437_clock.c new file mode 100644 index 0000000..09b6475 --- /dev/null +++ b/APP/at32f435_437_clock.c @@ -0,0 +1,113 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.c + * @version v2.0.4 + * @date 2021-12-31 + * @brief system clock config program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_clock.h" + +/** + * @brief system clock config program + * @note the system clock is configured as follow: + * - system clock = (hext * pll_ns)/(pll_ms * pll_fr) + * - system clock source = pll (hext) + * - hext = 8000000 + * - sclk = 250000000 + * - ahbdiv = 1 + * - ahbclk = 250000000 + * - apb2div = 2 + * - apb2clk = 125000000 + * - apb1div = 2 + * - apb1clk = 125000000 + * - pll_ns = 125 + * - pll_ms = 1 + * - pll_fr = 4 + * @param none + * @retval none + */ +void system_clock_config(void) +{ + /* enable pwc periph clock */ + crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); + + /* config ldo voltage */ + pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); + + /* set the flash clock divider */ + flash_clock_divider_set(FLASH_CLOCK_DIV_3); + + /* reset crm */ + crm_reset(); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); + + /* wait till hext is ready */ + while(crm_hext_stable_wait() == ERROR) + { + } + +#if defined PLL_NS + /* config pll clock resource */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, PLL_NS, 1, CRM_PLL_FR_4); +#endif + +#if !defined PLL_NS + /* config pll clock resource */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, 40, 1, CRM_PLL_FR_4); +#endif + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk */ + crm_apb2_div_set(CRM_APB2_DIV_2); + + /* config apb1clk */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} diff --git a/APP/at32f435_437_clock.h b/APP/at32f435_437_clock.h new file mode 100644 index 0000000..39da81e --- /dev/null +++ b/APP/at32f435_437_clock.h @@ -0,0 +1,46 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.h + * @version v2.0.4 + * @date 2021-12-31 + * @brief header file of clock program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CLOCK_H +#define __AT32F435_437_CLOCK_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported functions ------------------------------------------------------- */ +void system_clock_config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/APP/at32f435_437_conf.h b/APP/at32f435_437_conf.h new file mode 100644 index 0000000..4f9bd30 --- /dev/null +++ b/APP/at32f435_437_conf.h @@ -0,0 +1,191 @@ +/** + ************************************************************************** + * @file at32f435_437_conf.h + * @version v2.0.4 + * @date 2021-12-31 + * @brief at32f435_437 config header file + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CONF_H +#define __AT32F435_437_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup AT32F435_periph_template + * @{ + */ + +/** @addtogroup 435_Library_configuration Library_configuration + * @{ + */ + +/** + * @brief in the following line adjust the value of high speed exernal crystal (hext) + * used in your application + * + * tip: to avoid modifying this file each time you need to use different hext, you + * can define the hext value in your toolchain compiler preprocessor. + * + */ +#if !defined HEXT_VALUE +#define HEXT_VALUE ((uint32_t)25000000) /*!< value of the high speed exernal crystal in hz */ +#endif + +/** + * @brief in the following line adjust the high speed exernal crystal (hext) startup + * timeout value + */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ + +/* module define -------------------------------------------------------------*/ +#define CRM_MODULE_ENABLED +#define TMR_MODULE_ENABLED +#define ERTC_MODULE_ENABLED +#define GPIO_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define USART_MODULE_ENABLED +#define PWC_MODULE_ENABLED +#define CAN_MODULE_ENABLED +#define ADC_MODULE_ENABLED +#define DAC_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define EDMA_MODULE_ENABLED +#define DMA_MODULE_ENABLED +#define DEBUG_MODULE_ENABLED +#define FLASH_MODULE_ENABLED +#define CRC_MODULE_ENABLED +#define WWDT_MODULE_ENABLED +#define WDT_MODULE_ENABLED +#define EXINT_MODULE_ENABLED +#define SDIO_MODULE_ENABLED +#define XMC_MODULE_ENABLED +#define USB_MODULE_ENABLED +#define ACC_MODULE_ENABLED +#define MISC_MODULE_ENABLED +#define QSPI_MODULE_ENABLED +#define DVP_MODULE_ENABLED +#define SCFG_MODULE_ENABLED +#define EMAC_MODULE_ENABLED + +/* includes ------------------------------------------------------------------*/ +#ifdef CRM_MODULE_ENABLED +#include "at32f435_437_crm.h" +#endif +#ifdef TMR_MODULE_ENABLED +#include "at32f435_437_tmr.h" +#endif +#ifdef ERTC_MODULE_ENABLED +#include "at32f435_437_ertc.h" +#endif +#ifdef GPIO_MODULE_ENABLED +#include "at32f435_437_gpio.h" +#endif +#ifdef I2C_MODULE_ENABLED +#include "at32f435_437_i2c.h" +#endif +#ifdef USART_MODULE_ENABLED +#include "at32f435_437_usart.h" +#endif +#ifdef PWC_MODULE_ENABLED +#include "at32f435_437_pwc.h" +#endif +#ifdef CAN_MODULE_ENABLED +#include "at32f435_437_can.h" +#endif +#ifdef ADC_MODULE_ENABLED +#include "at32f435_437_adc.h" +#endif +#ifdef DAC_MODULE_ENABLED +#include "at32f435_437_dac.h" +#endif +#ifdef SPI_MODULE_ENABLED +#include "at32f435_437_spi.h" +#endif +#ifdef DMA_MODULE_ENABLED +#include "at32f435_437_dma.h" +#endif +#ifdef DEBUG_MODULE_ENABLED +#include "at32f435_437_debug.h" +#endif +#ifdef FLASH_MODULE_ENABLED +#include "at32f435_437_flash.h" +#endif +#ifdef CRC_MODULE_ENABLED +#include "at32f435_437_crc.h" +#endif +#ifdef WWDT_MODULE_ENABLED +#include "at32f435_437_wwdt.h" +#endif +#ifdef WDT_MODULE_ENABLED +#include "at32f435_437_wdt.h" +#endif +#ifdef EXINT_MODULE_ENABLED +#include "at32f435_437_exint.h" +#endif +#ifdef SDIO_MODULE_ENABLED +#include "at32f435_437_sdio.h" +#endif +#ifdef XMC_MODULE_ENABLED +#include "at32f435_437_xmc.h" +#endif +#ifdef ACC_MODULE_ENABLED +#include "at32f435_437_acc.h" +#endif +#ifdef MISC_MODULE_ENABLED +#include "at32f435_437_misc.h" +#endif +#ifdef EDMA_MODULE_ENABLED +#include "at32f435_437_edma.h" +#endif +#ifdef QSPI_MODULE_ENABLED +#include "at32f435_437_qspi.h" +#endif +#ifdef SCFG_MODULE_ENABLED +#include "at32f435_437_scfg.h" +#endif +#ifdef EMAC_MODULE_ENABLED +#include "at32f435_437_emac.h" +#endif +#ifdef DVP_MODULE_ENABLED +#include "at32f435_437_dvp.h" +#endif +#ifdef USB_MODULE_ENABLED +#include "at32f435_437_usb.h" +#endif + +/** + * @} + */ + + /** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/APP/at32f435_437_int.c b/APP/at32f435_437_int.c new file mode 100644 index 0000000..54f0f20 --- /dev/null +++ b/APP/at32f435_437_int.c @@ -0,0 +1,148 @@ +/** + ************************************************************************** + * @file at32f435_437_int.c + * @version v2.0.4 + * @date 2021-12-31 + * @brief main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_int.h" + + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup 437_EMAC_tcp_server + * @{ + */ + +/** + * @brief this function handles nmi exception. + * @param none + * @retval none + */ +//void NMI_Handler(void) +//{ +//} + +/** + * @brief this function handles hard fault exception. + * @param none + * @retval none + */ +//void HardFault_Handler(void) +//{ + /* go to infinite loop when hard fault exception occurs */ +// while(1) +// { +// } +//} + +/** + * @brief this function handles memory manage exception. + * @param none + * @retval none + */ +//void MemManage_Handler(void) +//{ + /* go to infinite loop when memory manage exception occurs */ +// while(1) +// { +// } +//} + +/** + * @brief this function handles bus fault exception. + * @param none + * @retval none + */ +//void BusFault_Handler(void) +//{ + /* go to infinite loop when bus fault exception occurs */ +// while(1) +// { +// } +//} + +/** + * @brief this function handles usage fault exception. + * @param none + * @retval none + */ +//void UsageFault_Handler(void) +//{ + /* go to infinite loop when usage fault exception occurs */ +// while(1) +// { +// } +//} + +/** + * @brief this function handles svcall exception. + * @param none + * @retval none + */ +//void SVC_Handler(void) +//{ +//} + +/** + * @brief this function handles debug monitor exception. + * @param none + * @retval none + */ +//void DebugMon_Handler(void) +//{ +//} + +/** + * @brief this function handles pendsv_handler exception. + * @param none + * @retval none + */ +//void PendSV_Handler(void) +//{ +//} + +/** + * @brief this function handles systick handler. + * @param none + * @retval none + */ +//void SysTick_Handler(void) +//{ +//} + +/** + * @brief this function handles emac handler. + * @param none + * @retval none + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/APP/at32f435_437_int.h b/APP/at32f435_437_int.h new file mode 100644 index 0000000..6671148 --- /dev/null +++ b/APP/at32f435_437_int.h @@ -0,0 +1,58 @@ +/** + ************************************************************************** + * @file at32f435_437_int.h + * @version v2.0.4 + * @date 2021-12-31 + * @brief header file of main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_INT_H +#define __AT32F435_437_INT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported types ------------------------------------------------------------*/ +/* exported constants --------------------------------------------------------*/ +/* exported macro ------------------------------------------------------------*/ +/* exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/APP/delay_sec.c b/APP/delay_sec.c new file mode 100644 index 0000000..0557b30 --- /dev/null +++ b/APP/delay_sec.c @@ -0,0 +1,92 @@ +// +// Created by cfif on 09.02.23. +// +#include "at32f435_437_clock.h" +#include "at32f435_437.h" + +/* delay macros */ +#define STEP_DELAY_MS 50 + +/* delay variable */ +static __IO uint32_t fac_us; +static __IO uint32_t fac_ms; +/** + * @brief initialize delay function + * @param none + * @retval none + */ +void delay_init() +{ + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + fac_us = system_core_clock / (1000000U); + fac_ms = fac_us * (1000U); +} + +/** + * @brief inserts a delay time. + * @param nus: specifies the delay time length, in microsecond. + * @retval none + */ +void delay_us(uint32_t nus) +{ + uint32_t temp = 0; + SysTick->LOAD = (uint32_t)(nus * fac_us); + SysTick->VAL = 0x00; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ; + do + { + temp = SysTick->CTRL; + }while((temp & 0x01) && !(temp & (1 << 16))); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0x00; +} + +/** + * @brief inserts a delay time. + * @param nms: specifies the delay time length, in milliseconds. + * @retval none + */ +void delay_ms(uint16_t nms) +{ + uint32_t temp = 0; + while(nms) + { + if(nms > STEP_DELAY_MS) + { + SysTick->LOAD = (uint32_t)(STEP_DELAY_MS * fac_ms); + nms -= STEP_DELAY_MS; + } + else + { + SysTick->LOAD = (uint32_t)(nms * fac_ms); + nms = 0; + } + SysTick->VAL = 0x00; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + do + { + temp = SysTick->CTRL; + }while((temp & 0x01) && !(temp & (1 << 16))); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0x00; + } +} + +/** + * @brief inserts a delay time. + * @param sec: specifies the delay time, in seconds. + * @retval none + */ +void delay_sec(uint16_t sec) +{ + uint16_t index; + for(index = 0; index < sec; index++) + { + delay_ms(500); + delay_ms(500); + } +} + diff --git a/APP/delay_sec.h b/APP/delay_sec.h new file mode 100644 index 0000000..197ca1c --- /dev/null +++ b/APP/delay_sec.h @@ -0,0 +1,14 @@ +// +// Created by cfif on 18.02.23. +// + +#ifndef GONEC_GSM_DELAY_SEC_H +#define GONEC_GSM_DELAY_SEC_H + +#include "inttypes.h" + +void delay_init(); +void delay_ms(uint16_t nms); +void delay_us(uint32_t nus); + +#endif //GONEC_GSM_DELAY_SEC_H diff --git a/APP/lwipopts.h b/APP/lwipopts.h new file mode 100644 index 0000000..dbe2d80 --- /dev/null +++ b/APP/lwipopts.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_LWIPOPTS_H +#define LWIP_HDR_LWIPOPTS_H + +//#define LWIP_TESTMODE 0 + +#define LWIP_IPV4 1 +//#define LWIP_TIMERS 0 + + +//#define LWIP_CHECKSUM_ON_COPY 1 +//#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK 1 +//#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL(printfmsg) LWIP_ASSERT("TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL", 0) + + + +/* We link to special sys_arch.c (for basic non-waiting API layers unit tests) */ +#define NO_SYS 1 +#define SYS_LIGHTWEIGHT_PROT 0 +#define LWIP_NETCONN !NO_SYS +#define LWIP_SOCKET !NO_SYS +#define LWIP_NETCONN_FULLDUPLEX LWIP_SOCKET +#define LWIP_NETBUF_RECVINFO 0 +#define LWIP_HAVE_LOOPIF 0 +//#define TCPIP_THREAD_TEST + +/* Enable DHCP to test it, disable UDP checksum to easier inject packets */ +#define LWIP_DHCP 0 + +/* Minimal changes to opt.h required for tcp unit tests: */ +/* TCP Maximum segment size. */ + +#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 +#define MEM_SIZE (40*1024) +#define TCP_SND_QUEUELEN (6 * TCP_SND_BUF)/TCP_MSS +#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN +#define TCP_SND_BUF (2 * TCP_MSS) +#define TCP_WND (2 * TCP_MSS)//(2* TCP_MSS) +#define LWIP_WND_SCALE 0 +#define TCP_RCV_SCALE 0 +#define PBUF_POOL_SIZE 16 //4 /* 10 - pbuf tests need ~200KByte */ +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1500//1536//1500 +#define TCP_QUEUE_OOSEQ 0 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Enable IGMP and MDNS for MDNS tests */ +#define LWIP_IGMP 1 +#define LWIP_MDNS_RESPONDER 1 +#define LWIP_NUM_NETIF_CLIENT_DATA (LWIP_MDNS_RESPONDER) + +/* Minimal changes to opt.h required for etharp unit tests: */ +#define ETHARP_SUPPORT_STATIC_ENTRIES 1 + +#define MEMP_NUM_SYS_TIMEOUT (LWIP_NUM_SYS_TIMEOUT_INTERNAL + 8) + +/* MIB2 stats are required to check IPv4 reassembly results */ +#define MIB2_STATS 1 + +/* netif tests want to test this, so enable: */ +//#define LWIP_NETIF_EXT_STATUS_CALLBACK 1 + +/* Check lwip_stats.mem.illegal instead of asserting */ +#define LWIP_MEM_ILLEGAL_FREE(msg) /* to nothing */ + +#endif /* LWIP_HDR_LWIPOPTS_H */ diff --git a/APP/main.c b/APP/main.c new file mode 100755 index 0000000..49399b5 --- /dev/null +++ b/APP/main.c @@ -0,0 +1,300 @@ +// +// Created by xemon on 15.09.22. +// +#include "main.h" +#include "at32f435_437_clock.h" +#include "at32f435_437.h" +#include +//#include +//#include +#include +#include "CmsisRtosThreadUtils.h" +#include "at32_emac.h" +#include "netconf.h" +#include "fs_interface.h" +#include "time.h" +#include "Rtcs.h" +#include "string.h" +#include "SerialPorts.h" +#include "AtCmdCommonProtected.h" +#include "Adcs.h" +#include "Gpios.h" + + +void extend_sram(void); + +void extend_sram(void) { + // check if ram has been set to expectant size, if not, change eopb0 + if (((USD->eopb0) & 0x07) != FLASH_EOPB0_SRAM_512K) { + flash_unlock(); + // erase user system data bytes + flash_user_system_data_erase(); + + // change sram size + flash_eopb0_config(FLASH_EOPB0_SRAM_512K); + + flash_lock(); + + // system reset + nvic_system_reset(); + } +} + +#define FIRMWARE_AREA_LENGTH (1024 * 1024) +#define FIRMWARE_UPDATE_ADDR (0x08260000) +#define FIRMWARE_MAIN_ADDR (0x08100000) + +tAtCmd At0; +uint8_t At0Rx[255]; +uint8_t At0Tx[255]; + +AtCommandResult +AtModem_Get_Version(tAtCmd *env, char *versionModem, uint8_t *sizeModem, char *versionCrypto, uint8_t *sizeCrypto) { + AtCmdPrepare(env); + AtCmdTxClear(env); + AtCmdTxAddStatic(env, "AT+VERSION"); + AtCmdTxSendLn(env); + + *sizeModem = 0; + *sizeCrypto = 0; + + uint32_t timeout = env->stdRxTimeout; + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs = timeout; + + while (AtCmdReceiveNextLine(env, leftMs) == AT_OK) { + leftMs = endMs - SystemGetMs(); + + if (AtCmdRxBeginWithStatic(env, "OK")) { + AtCmdRxClear(env); + + return AT_OK; + + } else if (AtCmdRxBeginWithStatic(env, "ERROR")) { + AtCmdRxClear(env); + return AT_ERROR; + + } else if (AtCmdRxBeginWithStatic(env, "#VERSION: MODEM_")) { + + char *start = env->rxBuffer.data + sizeof("#VERSION:"); + *sizeModem = env->rxBuffer.len - sizeof("#VERSION: "); + memcpy(versionModem, start, *sizeModem); + + AtCmdRxClear(env); + + } else if (AtCmdRxBeginWithStatic(env, "#VERSION: CRYPTO_")) { + + char *start = env->rxBuffer.data + sizeof("#VERSION:"); + *sizeCrypto = env->rxBuffer.len - sizeof("#VERSION: "); + memcpy(versionCrypto, start, *sizeCrypto); + + AtCmdRxClear(env); + + } else { + AtCmdProcessUnresolvedLine(env); + AtCmdRxClear(env); + continue; + } + } + + return AT_ERROR; +} + + +void delay_sec(uint16_t sec); + +void httpd_init(); + +void delay_init(); + +static struct { + uint32_t bootloader[2048]; +} threadsBuffers; + +static struct { + tThreadData bootloader; +} threads; + +THREAD_ATTR_CREATE(osPriorityNormal, bootloader); + +//tComInt COMINT; +tFirmwareLoader FIRMWARE_LOADER; +tFs fs; +tFirmwareInfo firmwareInfo; + +uint32_t get_fattime(void) { + struct tm stm; + RTCS.rtcI0.getTM(&RTCS, &stm); + + return (DWORD)(stm.tm_year - 80) << 25 | + (DWORD)(stm.tm_mon + 1) << 21 | + (DWORD)stm.tm_mday << 16 | + (DWORD)stm.tm_hour << 11 | + (DWORD)stm.tm_min << 5 | + (DWORD)stm.tm_sec >> 1; +} + + +void EMAC_IRQHandler(void) { + while (emac_received_packet_size_get() != 0) { + lwip_pkt_handle(); + } + + emac_dma_flag_clear(EMAC_DMA_RI_FLAG); + emac_dma_flag_clear(EMAC_DMA_NIS_FLAG); +} + +FRESULT FS_Init(tFs *env); +void sys_check_timeouts(void); + + +__NO_RETURN void BootloaderThread() { + + SerialPortClearRxBuffer(&SERIAL_PORTS.GONEC1IO); + + AtCmdInit( + &At0, &SERIAL_PORTS.GONEC1IO, + At0Rx, sizeof(At0Rx), + At0Tx, sizeof(At0Tx), + 2000, 2000 + ); + + + + Adcs_Init(); + + adc_ordinary_software_trigger_enable(ADCS.vcc.ADCx, TRUE); + while (adc_flag_get(ADCS.vcc.ADCx, ADC_OCCE_FLAG) == RESET) { + } + uint16_t data = adc_ordinary_conversion_data_get(ADCS.vcc.ADCx); + adc_flag_clear(ADCS.vcc.ADCx, ADC_OCCO_FLAG); + + + error_status status = emac_system_init_eth(); +// while (status == ERROR); + tcpip_stack_init(data); + httpd_init(); + + //InitSerialPorts(); + + //GpioPinEnable(&GPIO_PINS.rs485Power); + + //tSerialPortIO *serial = &SERIAL_PORTS.ComIntHalfDuplexIo; + +// uint8_t byte; + +// if (checkFirmware()) { + +// } + +// ComIntInit(&COMINT, serial, &FIRMWARE_LOADER); + +// ComIntRun(&COMINT); + +// + while (1) { + + lwip_periodic_handle(SystemGetMs()); + sys_check_timeouts(); + + while (emac_received_packet_size_get() != 0) { + lwip_pkt_handle(); + } + + SystemDelayMs(1); + +// SerialPortReceive(serial, &byte, 1, SystemWaitForever); +// SerialPortTransmit(serial, &byte, 1, SystemWaitForever); + +// GpioPinEnable(&PINS.green); +// SystemDelayMs(500); +// +// GpioPinDisable(&PINS.green); +// lwip_periodic_handle(SystemGetMs()); + +// if (emac_received_packet_size_get() != 0) +// lwip_pkt_handle(); + +// lwip_periodic_handle(SystemGetMs()); + +// SystemDelayMs(1); + + } +} + +__NO_RETURN int main() { + system_clock_config(); + + delay_init(); + + memset(&firmwareInfo, 0, sizeof(tFirmwareInfo)); + + FirmwareLoader_Init(&FIRMWARE_LOADER, FIRMWARE_AREA_LENGTH, FIRMWARE_MAIN_ADDR, FIRMWARE_UPDATE_ADDR); + +// FirmwareLoader_RunFirmware(&FIRMWARE_LOADER); + + Gpios_Init(); + Rtcs_Init(); + + FRESULT res; + + res = FS_Init(&fs); + + if (res == FR_OK) { + + res = f_mkdir(dir_temp); + res = f_mkdir(dir_web); + + char dirUpdateFileName[64]; + dirUpdateFileName[0] = '\0'; + strcat(dirUpdateFileName, dir_web); + strcat(dirUpdateFileName, "load"); + + // Информация о файле обновления + FILINFO fno; + FRESULT fr; + fr = f_stat(dirUpdateFileName, &fno); + // Если файл не найден (прошивки нет) + if (fr) { + firmwareInfo.isErrorFirmwareWEB = 1; + } else { + if (FirmwareLoader_CheckAndUpdate(&FIRMWARE_LOADER)) { + FirmwareLoader_RunFirmware(&FIRMWARE_LOADER); + } else { + firmwareInfo.isErrorFirmwareDEV = 1; + } + } + + } else { + + if (FirmwareLoader_CheckAndUpdate(&FIRMWARE_LOADER) == false) { + firmwareInfo.isErrorFirmwareDEV = 1; + } + + firmwareInfo.isErrorCardSD = 1; + firmwareInfo.isErrorFirmwareWEB = 1; + } + + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOH_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE); + + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + SerialPorts_Init(); + + osKernelInitialize(); + + THREAD_ADD(bootloader, NULL, BootloaderThread); + + osKernelStart(); + + while (1) { + + } +} diff --git a/APP/main.h b/APP/main.h new file mode 100755 index 0000000..129db8c --- /dev/null +++ b/APP/main.h @@ -0,0 +1,61 @@ +// +// Created by xemon on 01.11.22. +// + +#ifndef UVEOS_ON_ARTERY_MAIN_H +#define UVEOS_ON_ARTERY_MAIN_H +#include "stdio.h" +#include "AtCmdCommonProtected.h" + +extern tAtCmd At0; +AtCommandResult +AtModem_Get_Version(tAtCmd *env, char *versionModem, uint8_t *sizeModem, char *versionCrypto, uint8_t *sizeCrypto); + +typedef struct { + uint32_t isErrorCardSD; + uint32_t isErrorFirmwareWEB; + uint32_t isErrorFirmwareDEV; +} tFirmwareInfo; + +extern tFirmwareInfo firmwareInfo; + +/* +#include +#include +#include + +typedef struct { + tGpioPin red; + tGpioPin green; + tGpioPin blue; + + tGpioPin bipRed; + tGpioPin bipGreen; + + tGpioPin bipPower; + tGpioPin addButton; + + tGpioPin rs485Power; + tGpioPin rs485Receive; + tGpioPin rs485Transmit; +} tGpioPins; + +typedef struct { + tSerialPortNation ComIntPort; + tSerialPortIO ComIntIO; + + tSerialPortNation DebugPort; + tSerialPortIO DebugIO; + + tSerialPortHalfDuplex ComIntHalfDuplex; + tSerialPortIO ComIntHalfDuplexIo; +} tSerialPorts; + +extern tGpioPins GPIO_PINS; +extern tSerialPorts SERIAL_PORTS; + +void InitGpioPins(); + +void InitSerialPorts(); +*/ +#endif //UVEOS_ON_ARTERY_MAIN_H diff --git a/APP/modular.json b/APP/modular.json new file mode 100755 index 0000000..2683847 --- /dev/null +++ b/APP/modular.json @@ -0,0 +1,11 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "*.c", + "**.s" + ] + } +} \ No newline at end of file diff --git a/APP/startup_at32f435_437.s b/APP/startup_at32f435_437.s new file mode 100644 index 0000000..9566c54 --- /dev/null +++ b/APP/startup_at32f435_437.s @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file startup_at32f435_437.s + * @version v2.0.4 + * @date 2021-12-31 + * @brief at32f435_437 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + + +Reset_Handler: + bl extend_sram + + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */ + .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */ + .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */ + .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */ + .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */ + .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */ + .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */ + .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */ + .word OTGFS2_IRQHandler /* OTGFS2 */ + .word DVP_IRQHandler /* DVP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI2_IRQHandler /* QSPI2 */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word ACC_IRQHandler /* ACC */ + .word TMR20_BRK_IRQHandler /* TMR20 Brake */ + .word TMR20_OVF_IRQHandler /* TMR20 Overflow */ + .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */ + .word TMR20_CH_IRQHandler /* TMR20 Channel */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak EDMA_Stream1_IRQHandler + .thumb_set EDMA_Stream1_IRQHandler,Default_Handler + + .weak EDMA_Stream2_IRQHandler + .thumb_set EDMA_Stream2_IRQHandler,Default_Handler + + .weak EDMA_Stream3_IRQHandler + .thumb_set EDMA_Stream3_IRQHandler,Default_Handler + + .weak EDMA_Stream4_IRQHandler + .thumb_set EDMA_Stream4_IRQHandler,Default_Handler + + .weak EDMA_Stream5_IRQHandler + .thumb_set EDMA_Stream5_IRQHandler,Default_Handler + + .weak EDMA_Stream6_IRQHandler + .thumb_set EDMA_Stream6_IRQHandler,Default_Handler + + .weak EDMA_Stream7_IRQHandler + .thumb_set EDMA_Stream7_IRQHandler,Default_Handler + + .weak ADC1_2_3_IRQHandler + .thumb_set ADC1_2_3_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak EDMA_Stream8_IRQHandler + .thumb_set EDMA_Stream8_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGFS2_WKUP_IRQHandler + .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler + + .weak OTGFS2_IRQHandler + .thumb_set OTGFS2_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak QSPI2_IRQHandler + .thumb_set QSPI2_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak TMR20_BRK_IRQHandler + .thumb_set TMR20_BRK_IRQHandler,Default_Handler + + .weak TMR20_OVF_IRQHandler + .thumb_set TMR20_OVF_IRQHandler,Default_Handler + + .weak TMR20_TRG_HALL_IRQHandler + .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR20_CH_IRQHandler + .thumb_set TMR20_CH_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100755 index 0000000..46581de --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,79 @@ +#-- Service -------------------------------------------------------------------- +SET(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_GCC_CortexM4/gcc_cm4f.cmake) +ENABLE_LANGUAGE(ASM) +CMAKE_MINIMUM_REQUIRED(VERSION 3.8.0) + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fno-math-errno -ffast-math -funswitch-loops -fpredictive-commoning -finline-functions") + +set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0") +set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0") + +IF (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_BINARY_DIR}) + MESSAGE( + FATAL_ERROR + "In-source builds not allowed. + Please make a new directory (called a build directory) and run CMake from there. + You may need to remove CMakeCache.txt." + ) +ENDIF () + +SET(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +#-- Project config ------------------------------------------------------------- +PROJECT(GONEC_NEW_ARTERY_BOOTLOADER) # Project name +SET(HARDWARE_REVISION MAIN_BOOT) # +SET(VERSION \"1.4.4\") # +SET(HARDWARE_USER_NAME "Гонец N1") +SET(VECT_TAB_OFFSET "0x00000") +SET(HEXT_VALUE "25000000") +SET(PLL_NS "40") +#SET(HEXT_VALUE "8000000") +#SET(PLL_NS "72") + + +#-- Defines -------------------------------------------------------------------- +ADD_DEFINITIONS(-DDEBUG -DAT32F437ZMT7 -DAT32F437Vx) +ADD_DEFINITIONS(-DFIRMWARE_VERSION=${VERSION}) +ADD_DEFINITIONS(-DHARDWARE_REVISION=\"${HARDWARE_REVISION}\") +ADD_DEFINITIONS(-DVECT_TAB_OFFSET=${VECT_TAB_OFFSET}) +ADD_DEFINITIONS(-DHEXT_VALUE=${HEXT_VALUE}) +ADD_DEFINITIONS(-DPLL_NS=${PLL_NS}) +ADD_DEFINITIONS(-DCMSIS_device_header="at32f435_437.h"}) +ADD_DEFINITIONS(-DFLASH_PAGE_SIZE=4096) + +#-- Project paths, Include dirs, Sources list --------------------------------- +#ADD_FILES(SOURCES "MODULES/DeviceStartup_ARTERY_AT32F437ZMT7/ld/startup_at32f435_437.s") +include(modular.cmake) + + +#-- Options -------------------------------------------------------------------- +IF (PRINTF_FLOAT STREQUAL "1") + SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_printf_float") +ENDIF () +IF (SCANF_FLOAT STREQUAL "1") + SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_scanf_float") +ENDIF () + +#-- Linker script -------------------------------------------------------------- +SET(LDSCRIPT ${CMAKE_SOURCE_DIR}/APP/AT32F437xM_FLASH.ld) +SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${LDSCRIPT} -Wl,-Map=${CMAKE_BINARY_DIR}/${PROJECT_NAME}.map -Wl,--print-memory-usage") + + +#-- Random BuildId Generation ------------------------------------------------------------ +SET(RANDOM_BUILD_ID_GEN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake) +add_custom_target(GEN_RANDOM_BUILD_ID) +ADD_CUSTOM_COMMAND(TARGET GEN_RANDOM_BUILD_ID POST_BUILD + COMMAND ${CMAKE_COMMAND} -P ${RANDOM_BUILD_ID_GEN_FILE}) + + +#-- Project linking ------------------------------------------------------------ +ADD_EXECUTABLE(${PROJECT_NAME}.elf ${SOURCES}) +TARGET_LINK_LIBRARIES(${PROJECT_NAME}.elf) +add_dependencies(${PROJECT_NAME}.elf GEN_RANDOM_BUILD_ID) + +#-- Custom commands ------------------------------------------------------------ +ADD_CUSTOM_COMMAND(TARGET ${PROJECT_NAME}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} "-Oihex" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.hex + COMMAND ${CMAKE_OBJCOPY} "-Obinary" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin +# COMMAND ${CMAKE_OBJDUMP} "-DS" ${PROJECT_NAME}.elf > ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.dasm + COMMAND ${CMAKE_SIZE} ${PROJECT_NAME}.elf) diff --git a/modular.json b/modular.json new file mode 100755 index 0000000..096ed24 --- /dev/null +++ b/modular.json @@ -0,0 +1,149 @@ +{ + "dep": [ + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "CmakeConfig_GCC_CortexM4" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "DeviceStartup_ARTERY_AT32F435_437_old" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "PeripheralDriver_ARTERY_AT32F435_437_old" + }, + + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "CmsisCore5" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "SystemDelay_CMSIS_RTOS" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "FreeRTOSHeap4_CM4_CMSIS" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "CmsisRtosThreadUtils" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "FirmwareMetadataSection" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "BootJump_ARTERY_AT32" + }, + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "FirmwareLoader_ARTERY_AT32" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_NetConf_GSM_BOOT" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "Adc_ARTERY_AT32" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_ADCS" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "BOOT_GONEC_ARTERY_HttpServer" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "StreamBuf" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "JSON" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "BOOT_GONEC_ARTERY_FF" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_Rtcs" + }, + + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "Rtc_ARTERY_AT32" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_SerialPorts_BOOT" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "SerialPort_ARTERY_AT32" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "AtGsmCommon" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_GpioPins" + }, + + { + "type": "git", + "provider": "GONEC_NEW", + "repo": "GONEC_ARTERY_PowerManagement" + }, + + + { + "type": "local", + "dir": "APP" + } + ] +} diff --git a/stm32f427.cfg b/stm32f427.cfg new file mode 100755 index 0000000..c0ae719 --- /dev/null +++ b/stm32f427.cfg @@ -0,0 +1,27 @@ +# +# This is an STM32F429 discovery board with a single STM32F429ZI chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 +# + +source [find interface/atlink.cfg] + +#transport select hla_swd + +source [find target/at32f437xM.cfg] + +#reset_config trst_only +#reset_config srst_only +#reset_config trst_and_srst +#reset_config srst_pulls_trst +#reset_config combined +#reset_config srst_gates_jtag +#reset_config trst_push_pull +#reset_config trst_push_pull + +reset_config none + +#reset_config [none|trst_only|srst_only|trst_and_srst] +#[srst_pulls_trst|trst_pulls_srst|combined|separate] +#[srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain] +#[srst_push_pull|srst_open_drain] +#[connect_deassert_srst|connect_assert_srst] \ No newline at end of file