295 lines
9.0 KiB
C
295 lines
9.0 KiB
C
//
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// Created by cfif on 14.12.22.
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//
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/**
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**************************************************************************
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* @file qspi_cmd_esmt32m.c
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* @version v2.0.4
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* @date 2021-12-31
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* @brief qspi_cmd_esmt32m program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "cmsis_os.h"
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/** @addtogroup AT32F435_periph_examples
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* @{
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*/
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/** @addtogroup 435_QSPI_command_port_using_polling
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* @{
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*/
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#define QSPI_FIFO_DEPTH (32*4)
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#define FLASH_PAGE_PROGRAM_SIZE 256
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qspi_cmd_type esmt32m_cmd_config;
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void qspi_busy_check(void);
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void qspi_write_enable(void);
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/**
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* @brief esmt32m cmd read config
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* @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter
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* @param addr: read start address
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* @param counter: read data counter
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* @retval none
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*/
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void esmt32m_cmd_read_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter)
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{
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qspi_cmd_struct->pe_mode_enable = FALSE;
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qspi_cmd_struct->pe_mode_operate_code = 0;
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qspi_cmd_struct->instruction_code = 0xEB;
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qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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qspi_cmd_struct->address_code = addr;
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qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE;
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qspi_cmd_struct->data_counter = counter;
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qspi_cmd_struct->second_dummy_cycle_num = 6;
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qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_144;
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qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
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qspi_cmd_struct->read_status_enable = FALSE;
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qspi_cmd_struct->write_data_enable = FALSE;
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}
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/**
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* @brief esmt32m cmd write config
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* @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter
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* @param addr: write start address
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* @param counter: write data counter
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* @retval none
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*/
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void esmt32m_cmd_write_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr, uint32_t counter)
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{
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qspi_cmd_struct->pe_mode_enable = FALSE;
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qspi_cmd_struct->pe_mode_operate_code = 0;
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qspi_cmd_struct->instruction_code = 0x32;
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qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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qspi_cmd_struct->address_code = addr;
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qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE;
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qspi_cmd_struct->data_counter = counter;
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qspi_cmd_struct->second_dummy_cycle_num = 0;
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qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_114;
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qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
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qspi_cmd_struct->read_status_enable = FALSE;
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qspi_cmd_struct->write_data_enable = TRUE;
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}
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/**
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* @brief esmt32m cmd erase config
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* @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter
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* @param addr: erase address
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* @retval none
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*/
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void esmt32m_cmd_erase_config(qspi_cmd_type *qspi_cmd_struct, uint32_t addr)
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{
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qspi_cmd_struct->pe_mode_enable = FALSE;
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qspi_cmd_struct->pe_mode_operate_code = 0;
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qspi_cmd_struct->instruction_code = 0x20;
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qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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qspi_cmd_struct->address_code = addr;
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qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_3_BYTE;
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qspi_cmd_struct->data_counter = 0;
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qspi_cmd_struct->second_dummy_cycle_num = 0;
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qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_111;
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qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
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qspi_cmd_struct->read_status_enable = FALSE;
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qspi_cmd_struct->write_data_enable = TRUE;
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}
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/**
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* @brief esmt32m cmd wren config
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* @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter
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* @retval none
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*/
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void esmt32m_cmd_wren_config(qspi_cmd_type *qspi_cmd_struct)
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{
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qspi_cmd_struct->pe_mode_enable = FALSE;
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qspi_cmd_struct->pe_mode_operate_code = 0;
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qspi_cmd_struct->instruction_code = 0x06;
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qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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qspi_cmd_struct->address_code = 0;
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qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_0_BYTE;
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qspi_cmd_struct->data_counter = 0;
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qspi_cmd_struct->second_dummy_cycle_num = 0;
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qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_111;
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qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
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qspi_cmd_struct->read_status_enable = FALSE;
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qspi_cmd_struct->write_data_enable = TRUE;
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}
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/**
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* @brief esmt32m cmd rdsr config
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* @param qspi_cmd_struct: the pointer for qspi_cmd_type parameter
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* @retval none
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*/
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void esmt32m_cmd_rdsr_config(qspi_cmd_type *qspi_cmd_struct)
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{
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qspi_cmd_struct->pe_mode_enable = FALSE;
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qspi_cmd_struct->pe_mode_operate_code = 0;
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qspi_cmd_struct->instruction_code = 0x05;
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qspi_cmd_struct->instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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qspi_cmd_struct->address_code = 0;
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qspi_cmd_struct->address_length = QSPI_CMD_ADRLEN_0_BYTE;
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qspi_cmd_struct->data_counter = 0;
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qspi_cmd_struct->second_dummy_cycle_num = 0;
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qspi_cmd_struct->operation_mode = QSPI_OPERATE_MODE_111;
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qspi_cmd_struct->read_status_config = QSPI_RSTSC_HW_AUTO;
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qspi_cmd_struct->read_status_enable = TRUE;
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qspi_cmd_struct->write_data_enable = FALSE;
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}
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/**
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* @brief qspi read data
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* @param addr: the address for read
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* @param total_len: the length for read
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* @param buf: the pointer for read data
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* @retval none
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*/
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void qspi_data_read(uint32_t addr, uint32_t total_len, uint8_t* buf)
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{
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uint32_t i, len = total_len;
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esmt32m_cmd_read_config(&esmt32m_cmd_config, addr, total_len);
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qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);
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/* read data */
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do
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{
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if(total_len >= QSPI_FIFO_DEPTH)
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{
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len = QSPI_FIFO_DEPTH;
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}
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else
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{
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len = total_len;
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}
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while(qspi_flag_get(QSPI1, QSPI_RXFIFORDY_FLAG) == RESET);
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for(i = 0; i < len; ++i)
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{
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*buf++ = qspi_byte_read(QSPI1);
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}
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total_len -= len;
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}while(total_len);
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/* wait command completed */
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while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);
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}
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/**
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* @brief qspi write data
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* @param addr: the address for write
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* @param total_len: the length for write
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* @param buf: the pointer for write data
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* @retval none
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*/
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void qspi_data_write(uint32_t addr, uint32_t total_len, uint8_t* buf)
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{
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uint32_t i, len = total_len;
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do
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{
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qspi_write_enable();
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if(total_len >= FLASH_PAGE_PROGRAM_SIZE)
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{
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len = FLASH_PAGE_PROGRAM_SIZE;
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}
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else
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{
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len = total_len;
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}
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esmt32m_cmd_write_config(&esmt32m_cmd_config, addr, len);
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qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);
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for(i = 0; i < len; ++i)
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{
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while(qspi_flag_get(QSPI1, QSPI_TXFIFORDY_FLAG) == RESET);
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qspi_byte_write(QSPI1, *buf++);
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}
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total_len -= len;
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addr += len;
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/* wait command completed */
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while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);
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qspi_busy_check();
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}while(total_len);
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}
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/**
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* @brief qspi erase data
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* @param sec_addr: the sector address for erase
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* @retval none
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*/
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void qspi_erase(uint32_t sec_addr)
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{
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qspi_write_enable();
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esmt32m_cmd_erase_config(&esmt32m_cmd_config, sec_addr);
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qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);
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/* wait command completed */
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while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);
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qspi_busy_check();
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}
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/**
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* @brief qspi check busy
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* @param none
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* @retval none
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*/
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void qspi_busy_check(void)
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{
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esmt32m_cmd_rdsr_config(&esmt32m_cmd_config);
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qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);
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/* wait command completed */
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while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);
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}
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/**
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* @brief qspi write enable
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* @param none
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* @retval none
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*/
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void qspi_write_enable(void)
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{
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esmt32m_cmd_wren_config(&esmt32m_cmd_config);
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qspi_cmd_operation_kick(QSPI1, &esmt32m_cmd_config);
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/* wait command completed */
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while(qspi_flag_get(QSPI1, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(QSPI1, QSPI_CMDSTS_FLAG);
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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