Переход в новую организацию
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/*!
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\file gd32f4xx.h
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\brief general definitions for GD32F4xx
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_H
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#define GD32F4XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define GD32F4xx */
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#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
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#define GD32F450
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/* #define GD32F405 */
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/* #define GD32F407 */
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/* #define GD32F470 */
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/* #define GD32F425 */
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/* #define GD32F427 */
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#endif /* define GD32F4xx */
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#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
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#error "Please select the target GD32F4xx device in gd32f4xx.h file"
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#endif /* undefine GD32F4xx tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)25000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
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#if !defined (IRC16M_VALUE)
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#define IRC16M_VALUE ((uint32_t)16000000)
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#endif /* internal 16MHz RC oscillator value */
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/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
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#if !defined (IRC16M_STARTUP_TIMEOUT)
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#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 16MHz RC oscillator startup timeout */
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/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
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#if !defined (IRC32K_VALUE)
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#define IRC32K_VALUE ((uint32_t)32000)
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#endif /* internal 32KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* I2S external clock in selection */
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//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
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/* GD32F4xx firmware library version number V1.0 */
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#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F4xx_STDPERIPH_VERSION_RC))
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/* configuration of the cortex-M4 processor and core peripherals */
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#define __CM4_REV 0x0001 /*!< core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
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#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
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#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* cortex-M4 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
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RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
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FMC_IRQn = 4, /*!< FMC interrupt */
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RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
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DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
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DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
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DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
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DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
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DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
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DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
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ADC_IRQn = 18, /*!< ADC interrupt */
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CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
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CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
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TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
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TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
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USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
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TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
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TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
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TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
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TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
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DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
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#if defined (GD32F450) || defined (GD32F470)
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EXMC_IRQn = 48, /*!< EXMC interrupt */
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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ENET_IRQn = 61, /*!< ENET interrupt */
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ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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UART6_IRQn = 82, /*!< UART6 interrupt */
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UART7_IRQn = 83, /*!< UART7 interrupt */
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SPI3_IRQn = 84, /*!< SPI3 interrupt */
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SPI4_IRQn = 85, /*!< SPI4 interrupt */
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SPI5_IRQn = 86, /*!< SPI5 interrupt */
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TLI_IRQn = 88, /*!< TLI interrupt */
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TLI_ER_IRQn = 89, /*!< TLI error interrupt */
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IPA_IRQn = 90, /*!< IPA interrupt */
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#endif /* GD32F450 and GD32F470 */
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#if defined (GD32F405) || defined (GD32F425)
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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#endif /* GD32F405 and GD32F425 */
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#if defined (GD32F407) || defined (GD32F427)
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EXMC_IRQn = 48, /*!< EXMC interrupt */
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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ENET_IRQn = 61, /*!< ENET interrupt */
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ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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#endif /* GD32F407 and GD32F427 */
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} IRQn_Type;
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/* includes */
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#include "core_cm4.h"
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#include "system_gd32f4xx.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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|
|
||||||
|
/* bit operations */
|
||||||
|
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||||
|
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||||
|
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||||
|
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||||
|
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||||
|
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||||
|
|
||||||
|
/* main flash and SRAM memory map */
|
||||||
|
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||||
|
#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
|
||||||
|
#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
|
||||||
|
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||||
|
|
||||||
|
/* peripheral memory map */
|
||||||
|
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||||
|
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||||
|
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||||
|
#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
|
||||||
|
|
||||||
|
/* EXMC memory map */
|
||||||
|
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||||
|
|
||||||
|
/* advanced peripheral bus 1 memory map */
|
||||||
|
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||||
|
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||||
|
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||||
|
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||||
|
#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
|
||||||
|
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||||
|
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||||
|
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||||
|
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||||
|
#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
|
||||||
|
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||||
|
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||||
|
#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
|
||||||
|
|
||||||
|
/* advanced peripheral bus 2 memory map */
|
||||||
|
#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
|
||||||
|
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
|
||||||
|
#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
|
||||||
|
#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
|
||||||
|
#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
|
||||||
|
/* advanced high performance bus 1 memory map */
|
||||||
|
#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||||
|
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||||
|
#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
|
||||||
|
#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
|
||||||
|
#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
|
||||||
|
#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
|
||||||
|
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||||||
|
#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
|
||||||
|
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||||||
|
|
||||||
|
/* advanced high performance bus 2 memory map */
|
||||||
|
#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
|
||||||
|
#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
|
||||||
|
#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
|
||||||
|
/* option byte and debug memory map */
|
||||||
|
#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
|
||||||
|
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||||
|
|
||||||
|
/* define marco USE_STDPERIPH_DRIVER */
|
||||||
|
#if !defined USE_STDPERIPH_DRIVER
|
||||||
|
#define USE_STDPERIPH_DRIVER
|
||||||
|
#endif
|
||||||
|
#ifdef USE_STDPERIPH_DRIVER
|
||||||
|
#include "gd32f4xx_libopt.h"
|
||||||
|
#endif /* USE_STDPERIPH_DRIVER */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,11 @@
|
||||||
|
{
|
||||||
|
"cmake": {
|
||||||
|
"inc_dirs": [
|
||||||
|
"./"
|
||||||
|
],
|
||||||
|
"srcs": [
|
||||||
|
"./**.c",
|
||||||
|
"./**.s"
|
||||||
|
]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,409 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_at32f415.s
|
||||||
|
* @version v2.0.7
|
||||||
|
* @date 2022-08-16
|
||||||
|
* @brief at32f415xx devices vector table for gcc toolchain.
|
||||||
|
* this module performs:
|
||||||
|
* - set the initial sp
|
||||||
|
* - set the initial pc == reset_handler,
|
||||||
|
* - set the vector table entries with the exceptions isr address
|
||||||
|
* - configure the clock system and the external sram to
|
||||||
|
* be used as data memory (optional, to be enabled by user)
|
||||||
|
* - branches to main in the c library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* after reset the cortex-m4 processor is in thread mode,
|
||||||
|
* priority is privileged, and the stack is set to main.
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/********************************USART0_IRQHandler**********************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDT_IRQHandler /* Window Watchdog Timer */
|
||||||
|
.word PVM_IRQHandler /* PVM through EXINT Line detect */
|
||||||
|
.word TAMPER_IRQHandler /* Tamper */
|
||||||
|
.word ERTC_IRQHandler /* ERTC */
|
||||||
|
.word FLASH_IRQHandler /* Flash */
|
||||||
|
.word CRM_IRQHandler /* CRM */
|
||||||
|
.word EXINT0_IRQHandler /* EXINT Line 0 */
|
||||||
|
.word EXINT1_IRQHandler /* EXINT Line 1 */
|
||||||
|
.word EXINT2_IRQHandler /* EXINT Line 2 */
|
||||||
|
.word EXINT3_IRQHandler /* EXINT Line 3 */
|
||||||
|
.word EXINT4_IRQHandler /* EXINT Line 4 */
|
||||||
|
.word DMA0_Channel0_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.word DMA0_Channel1_IRQHandler /* DMA1 Channel 2 */
|
||||||
|
.word DMA0_Channel2_IRQHandler /* DMA1 Channel 3 */
|
||||||
|
.word DMA0_Channel3_IRQHandler /* DMA1 Channel 4 */
|
||||||
|
.word DMA0_Channel4_IRQHandler /* DMA1 Channel 5 */
|
||||||
|
.word DMA0_Channel5_IRQHandler /* DMA1 Channel 6 */
|
||||||
|
.word DMA0_Channel6_IRQHandler /* DMA1 Channel 7 */
|
||||||
|
.word ADC1_IRQHandler /* ADC1 */
|
||||||
|
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||||
|
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
|
.word CAN1_SE_IRQHandler /* CAN1 SE */
|
||||||
|
.word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
|
||||||
|
.word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
|
||||||
|
.word TMR1_OVF_TMR10_IRQHandler /* TMR1 overflow and TMR10 */
|
||||||
|
.word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
|
||||||
|
.word TMR1_CH_IRQHandler /* TMR1 channel */
|
||||||
|
.word TMR2_GLOBAL_IRQHandler /* TMR2 */
|
||||||
|
.word TMR3_GLOBAL_IRQHandler /* TMR3 */
|
||||||
|
.word TMR4_GLOBAL_IRQHandler /* TMR4 */
|
||||||
|
.word I2C1_EVT_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ERR_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EVT_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ERR_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART0_IRQHandler /* USART0 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
|
||||||
|
.word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */
|
||||||
|
.word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDIO1_IRQHandler /* SDIO1 */
|
||||||
|
.word TMR5_GLOBAL_IRQHandler /* TMR5 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA1_Channel0_IRQHandler /* DMA2 Channel1 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* DMA2 Channel2 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* DMA2 Channel3 */
|
||||||
|
.word DMA1_Channel3_5_IRQHandler /* DMA2 Channel4 & Channel5 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word OTGFS1_IRQHandler /* OTGFS1 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word CMP1_IRQHandler /* CMP1 */
|
||||||
|
.word CMP2_IRQHandler /* CMP2 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDT_IRQHandler
|
||||||
|
.thumb_set WWDT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVM_IRQHandler
|
||||||
|
.thumb_set PVM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_IRQHandler
|
||||||
|
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ERTC_IRQHandler
|
||||||
|
.thumb_set ERTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRM_IRQHandler
|
||||||
|
.thumb_set CRM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT0_IRQHandler
|
||||||
|
.thumb_set EXINT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT1_IRQHandler
|
||||||
|
.thumb_set EXINT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT2_IRQHandler
|
||||||
|
.thumb_set EXINT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT3_IRQHandler
|
||||||
|
.thumb_set EXINT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT4_IRQHandler
|
||||||
|
.thumb_set EXINT4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_IRQHandler
|
||||||
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SE_IRQHandler
|
||||||
|
.thumb_set CAN1_SE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT9_5_IRQHandler
|
||||||
|
.thumb_set EXINT9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR1_BRK_TMR9_IRQHandler
|
||||||
|
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR1_OVF_TMR10_IRQHandler
|
||||||
|
.thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR1_TRG_HALL_TMR11_IRQHandler
|
||||||
|
.thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR1_CH_IRQHandler
|
||||||
|
.thumb_set TMR1_CH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR2_GLOBAL_IRQHandler
|
||||||
|
.thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR3_GLOBAL_IRQHandler
|
||||||
|
.thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR4_GLOBAL_IRQHandler
|
||||||
|
.thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EVT_IRQHandler
|
||||||
|
.thumb_set I2C1_EVT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ERR_IRQHandler
|
||||||
|
.thumb_set I2C1_ERR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EVT_IRQHandler
|
||||||
|
.thumb_set I2C2_EVT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ERR_IRQHandler
|
||||||
|
.thumb_set I2C2_ERR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART0_IRQHandler
|
||||||
|
.thumb_set USART0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXINT15_10_IRQHandler
|
||||||
|
.thumb_set EXINT15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ERTCAlarm_IRQHandler
|
||||||
|
.thumb_set ERTCAlarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTGFS1_WKUP_IRQHandler
|
||||||
|
.thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO1_IRQHandler
|
||||||
|
.thumb_set SDIO1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TMR5_GLOBAL_IRQHandler
|
||||||
|
.thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTGFS1_IRQHandler
|
||||||
|
.thumb_set OTGFS1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CMP1_IRQHandler
|
||||||
|
.thumb_set CMP1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CMP2_IRQHandler
|
||||||
|
.thumb_set CMP2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel6_7_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
|
||||||
|
|
@ -0,0 +1,454 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
DCD UART6_IRQHandler ; 98:UART6
|
||||||
|
DCD UART7_IRQHandler ; 99:UART7
|
||||||
|
DCD SPI3_IRQHandler ; 100:SPI3
|
||||||
|
DCD SPI4_IRQHandler ; 101:SPI4
|
||||||
|
DCD SPI5_IRQHandler ; 102:SPI5
|
||||||
|
DCD 0 ; 103:Reserved
|
||||||
|
DCD TLI_IRQHandler ; 104:TLI
|
||||||
|
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||||
|
DCD IPA_IRQHandler ; 106:IPA
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT EXMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART6_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT IPA_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
EXMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
ENET_IRQHandler
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART6_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
TLI_IRQHandler
|
||||||
|
TLI_ER_IRQHandler
|
||||||
|
IPA_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,58 @@
|
||||||
|
/*!
|
||||||
|
\file system_gd32f4xx.h
|
||||||
|
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||||
|
GD32F4xx Device Series
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
#ifndef SYSTEM_GD32F4XX_H
|
||||||
|
#define SYSTEM_GD32F4XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* system clock frequency (core clock) */
|
||||||
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialize the system and update the SystemCoreClock variable */
|
||||||
|
extern void SystemInit (void);
|
||||||
|
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||||
|
extern void SystemCoreClockUpdate (void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* SYSTEM_GD32F4XX_H */
|
||||||
Loading…
Reference in New Issue