562 lines
17 KiB
C
562 lines
17 KiB
C
/**
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**************************************************************************
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* @file at32_emac.c
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* @version v2.0.4
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* @date 2021-12-31
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* @brief emac config program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* includes ------------------------------------------------------------------*/
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#include "at32_emac.h"
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#include "SystemDelayInterface.h"
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/** @addtogroup AT32F437_periph_examples
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* @{
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*/
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/** @addtogroup 437_EMAC_tcp_server
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* @{
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*/
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/**
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* @brief enable emac clock and gpio clock
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* @param none
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* @retval success or error
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*/
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error_status emac_system_init(void)
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{
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error_status status;
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emac_nvic_configuration();
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/* emac periph clock enable */
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crm_periph_clock_enable(CRM_EMAC_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_EMACTX_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_EMACRX_PERIPH_CLOCK, TRUE);
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emac_pins_configuration();
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status = emac_layer2_configuration();
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return status;
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}
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error_status emac_system_init_eth(void) {
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nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
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error_status status = emac_system_init();
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return status;
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}
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/**
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* @brief configures emac irq channel.
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* @param none
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* @retval none
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*/
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void emac_nvic_configuration(void)
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{
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nvic_irq_enable(EMAC_IRQn, 1, 0);
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NVIC_SetPriority((IRQn_Type)EMAC_IRQn, 0);
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}
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/**
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* @brief configures emac required pins.
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* @param none
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* @retval none
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*/
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void emac_pins_configuration(void)
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{
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gpio_init_type gpio_init_struct = {0};
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/* emac pins clock enable */
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOH_PERIPH_CLOCK, TRUE);
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/* pa2 -> mdio */
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE2, GPIO_MUX_11);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pins = GPIO_PINS_2;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init(GPIOA, &gpio_init_struct);
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/* pc1 -> mdc */
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE1, GPIO_MUX_11);
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gpio_init_struct.gpio_pins = GPIO_PINS_1;
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gpio_init(GPIOC, &gpio_init_struct);
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#ifdef MII_MODE
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/*
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pg13 -> tx_d0
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pg14 -> tx_d1
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pc2 -> tx_d2
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pb8 -> tx_d3
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pb11 -> tx_en
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pc3 -> tx_clk
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*/
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gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE13, GPIO_MUX_11); // pg13 -> tx_d0
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gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE14, GPIO_MUX_11); // pg14 -> tx_d1
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gpio_init_struct.gpio_pins = GPIO_PINS_13 | GPIO_PINS_14;
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gpio_init(GPIOG, &gpio_init_struct);
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE2, GPIO_MUX_11); // pc2 -> tx_d2
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE3, GPIO_MUX_11); // pc3 -> tx_clk
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gpio_init_struct.gpio_pins = GPIO_PINS_2 | GPIO_PINS_3;
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gpio_init(GPIOC, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE8, GPIO_MUX_11); // pb8 -> tx_d3
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_11); // pb11 -> tx_en
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gpio_init_struct.gpio_pins = GPIO_PINS_8 | GPIO_PINS_11;
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gpio_init(GPIOB, &gpio_init_struct);
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/*
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pa7 -> rx_dv
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pc4 -> rx_d0
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pc5 -> rx_d1
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pb0 -> rx_d2
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pb1 -> rx_d3
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*/
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE7, GPIO_MUX_11); // pa7 -> rx_dv
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gpio_init_struct.gpio_pins = GPIO_PINS_7;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE4, GPIO_MUX_11); // pc4 -> rx_d0
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE5, GPIO_MUX_11); // pc5 -> rx_d1
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gpio_init_struct.gpio_pins = GPIO_PINS_4 | GPIO_PINS_5;
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gpio_init(GPIOC, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE0, GPIO_MUX_11); // pb0 -> rx_d2
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE1, GPIO_MUX_11); // pb1 -> rx_d3
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gpio_init_struct.gpio_pins = GPIO_PINS_0 | GPIO_PINS_1;
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gpio_init(GPIOB, &gpio_init_struct);
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/*
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pa1 -> rx_clk
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pa0 -> crs
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pa3 -> col
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pb10 -> rx_er
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*/
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE1, GPIO_MUX_11); // pa1 -> rx_clk
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE0, GPIO_MUX_11); // pa0 -> crs
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE3, GPIO_MUX_11); // pa3 -> col
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gpio_init_struct.gpio_pins = GPIO_PINS_1 | GPIO_PINS_0 | GPIO_PINS_3;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_11); // pb10 -> rx_er
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gpio_init_struct.gpio_pins = GPIO_PINS_10;
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gpio_init(GPIOB, &gpio_init_struct);
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#endif /* MII_MODE */
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#ifdef RMII_MODE
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/*
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pb12 -> tx_d0
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pb13 -> tx_d1
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pb11 -> tx_en
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*/
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gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE11, GPIO_MUX_11);
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gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE13, GPIO_MUX_11);
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gpio_pin_mux_config(GPIOG, GPIO_PINS_SOURCE14, GPIO_MUX_11);
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gpio_init_struct.gpio_pins = GPIO_PINS_11 | GPIO_PINS_13 | GPIO_PINS_14;
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gpio_init(GPIOG, &gpio_init_struct);
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/*
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pd8 -> rx_dv
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pd9 -> rx_d0
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pd10 -> rx_d1
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*/
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gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE8, GPIO_MUX_11);
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gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE9, GPIO_MUX_11);
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gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE10, GPIO_MUX_11);
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gpio_init_struct.gpio_pins = GPIO_PINS_8 | GPIO_PINS_9 | GPIO_PINS_10;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init(GPIOD, &gpio_init_struct);
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#endif /* RMII_MODE */
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/*
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pa1 -> ref_clk
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*/
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE1, GPIO_MUX_11);
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gpio_init_struct.gpio_pins = GPIO_PINS_1;
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gpio_init(GPIOA, &gpio_init_struct);
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#if !CRYSTAL_ON_PHY
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_0);
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init(GPIOA, &gpio_init_struct);
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#endif
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}
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/**
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* @brief configures emac layer2
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* @param none
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* @retval error or success
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*/
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error_status emac_layer2_configuration(void)
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{
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emac_control_config_type mac_control_para;
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emac_dma_config_type dma_control_para;
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crm_periph_clock_enable(CRM_SCFG_PERIPH_CLOCK, TRUE);
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#ifdef MII_MODE
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scfg_emac_interface_set(SCFG_EMAC_SELECT_MII);
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#elif defined RMII_MODE
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scfg_emac_interface_set(SCFG_EMAC_SELECT_RMII);
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#endif
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// crm_clock_out1_set(CRM_CLKOUT1_PLL);
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// crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_5, CRM_CLKOUT_DIV2_2);
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crm_clock_out1_set(CRM_CLKOUT1_HEXT);
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crm_clkout_div_set(CRM_CLKOUT_INDEX_1, CRM_CLKOUT_DIV1_1, CRM_CLKOUT_DIV2_1);
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/* reset phy */
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reset_phy();
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/* reset emac ahb bus */
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emac_reset();
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/* software reset emac dma */
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emac_dma_software_reset_set();
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while(emac_dma_software_reset_get() == SET);
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emac_control_para_init(&mac_control_para);
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// mac_control_para.duplex_mode = EMAC_FULL_DUPLEX;
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// mac_control_para.fast_ethernet_speed = EMAC_SPEED_10MBPS;
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/*
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mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_OFF;
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mac_control_para.fast_ethernet_speed = EMAC_SPEED_100MBPS;
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mac_control_para.duplex_mode = EMAC_FULL_DUPLEX;
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*/
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//mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_OFF;
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//mac_control_para.fast_ethernet_speed = PHY_FULL_DUPLEX_100MBPS_BIT;
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//mac_control_para.duplex_mode = EMAC_FULL_DUPLEX;
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// mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_ON;
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mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_OFF;
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mac_control_para.fast_ethernet_speed = EMAC_SPEED_100MBPS;
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mac_control_para.duplex_mode = EMAC_FULL_DUPLEX;
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if(emac_phy_init(&mac_control_para) == ERROR)
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{
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return ERROR;
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}
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emac_dma_para_init(&dma_control_para);
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dma_control_para.rsf_enable = TRUE;
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dma_control_para.tsf_enable = TRUE;
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dma_control_para.osf_enable = TRUE;
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dma_control_para.aab_enable = TRUE;
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dma_control_para.usp_enable = TRUE;
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dma_control_para.fb_enable = TRUE;
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dma_control_para.flush_rx_disable = TRUE;
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dma_control_para.rx_dma_pal = EMAC_DMA_PBL_32;
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dma_control_para.tx_dma_pal = EMAC_DMA_PBL_32;
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dma_control_para.priority_ratio = EMAC_DMA_2_RX_1_TX;
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emac_dma_config(&dma_control_para);
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_NORMAL_SUMMARY, TRUE);
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX, TRUE);
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX, TRUE); /*!< transmit interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX_STOP, TRUE); /*!< transmit process stopped interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX_UNAVAILABLE, TRUE); /*!< transmit buffer unavailable interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX_JABBER, TRUE); /*!< transmit jabber timeout interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX_OVERFLOW, TRUE); /*!< receive overflow interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX_UNDERFLOW, TRUE); /*!< transmit underflow interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX, TRUE); /*!< receive interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX_UNAVAILABLE, TRUE); /*!< receive buffer unavailable interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX_STOP, TRUE); /*!< receive process stopped interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX_TIMEOUT, TRUE); /*!< receive watchdog timeout interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_TX_EARLY, TRUE); /*!< early transmit interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR, TRUE); /*!< fatal bus error interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX_EARLY, TRUE); /*!< early receive interrupt */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY, TRUE); /*!< abnormal interrupt summary */
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// emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_NORMAL_SUMMARY, TRUE); /*!< normal interrupt summary */
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return SUCCESS;
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}
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/**
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* @brief reset layer 1
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* @param none
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* @retval none
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*/
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void static reset_phy(void)
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{
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gpio_init_type gpio_init_struct = {0};
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crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pins = GPIO_PINS_12;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init(GPIOG, &gpio_init_struct);
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gpio_bits_reset(GPIOG, GPIO_PINS_12);
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SystemDelayMs(2);
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// delay_ms(2);
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gpio_bits_set(GPIOG, GPIO_PINS_12);
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SystemDelayMs(2);
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// delay_ms(2);
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/*
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gpio_init_type gpio_init_struct = {0};
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crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pins = GPIO_PINS_15;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init(GPIOE, &gpio_init_struct);
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gpio_init_struct.gpio_pins = GPIO_PINS_15;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init(GPIOG, &gpio_init_struct);
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gpio_bits_reset(GPIOG, GPIO_PINS_15);
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gpio_bits_reset(GPIOE, GPIO_PINS_15);
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SystemDelayMs(2);
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// delay_ms(2);
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gpio_bits_set(GPIOE, GPIO_PINS_15);
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SystemDelayMs(2);
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// delay_ms(2);
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*/
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}
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/**
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* @brief reset phy register
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* @param none
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* @retval SUCCESS or ERROR
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*/
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error_status emac_phy_register_reset(void)
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{
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uint16_t data = 0;
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uint32_t timeout = 0;
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uint32_t i = 0;
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if(emac_phy_register_write(PHY_ADDRESS, PHY_CONTROL_REG, PHY_RESET_BIT) == ERROR)
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{
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return ERROR;
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}
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for(i = 0; i < 0x000FFFFF; i++);
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do
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{
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timeout++;
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if(emac_phy_register_read(PHY_ADDRESS, PHY_CONTROL_REG, &data) == ERROR)
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{
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return ERROR;
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}
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} while((data & PHY_RESET_BIT) && (timeout < PHY_TIMEOUT));
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for(i = 0; i < 0x00FFFFF; i++);
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if(timeout == PHY_TIMEOUT)
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{
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return ERROR;
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}
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return SUCCESS;
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}
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/**
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* @brief set mac speed related parameters
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* @param nego: auto negotiation on or off.
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* this parameter can be one of the following values:
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* - EMAC_AUTO_NEGOTIATION_OFF
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* - EMAC_AUTO_NEGOTIATION_ON.
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* @param mode: half-duplex or full-duplex.
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* this parameter can be one of the following values:
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* - EMAC_HALF_DUPLEX
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* - EMAC_FULL_DUPLEX.
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* @param speed: 10 mbps or 100 mbps
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* this parameter can be one of the following values:
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* - EMAC_SPEED_10MBPS
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* - EMAC_SPEED_100MBPS.
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* @retval none
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*/
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error_status emac_speed_config(emac_auto_negotiation_type nego, emac_duplex_type mode, emac_speed_type speed)
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{
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uint16_t data = 0;
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uint32_t timeout = 0;
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if(nego == EMAC_AUTO_NEGOTIATION_ON)
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{
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do
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{
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timeout++;
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if(emac_phy_register_read(PHY_ADDRESS, PHY_STATUS_REG, &data) == ERROR)
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{
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return ERROR;
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}
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} while(!(data & PHY_LINKED_STATUS_BIT) && (timeout < PHY_TIMEOUT));
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if(timeout == PHY_TIMEOUT)
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{
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return ERROR;
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|
}
|
|
|
|
timeout = 0;
|
|
|
|
if(emac_phy_register_write(PHY_ADDRESS, PHY_CONTROL_REG, PHY_AUTO_NEGOTIATION_BIT) == ERROR)
|
|
{
|
|
return ERROR;
|
|
}
|
|
|
|
|
|
do
|
|
{
|
|
timeout++;
|
|
if(emac_phy_register_read(PHY_ADDRESS, PHY_STATUS_REG, &data) == ERROR)
|
|
{
|
|
return ERROR;
|
|
}
|
|
} while(!(data & PHY_NEGO_COMPLETE_BIT) && (timeout < PHY_TIMEOUT));
|
|
|
|
if(timeout == PHY_TIMEOUT)
|
|
{
|
|
return ERROR;
|
|
}
|
|
|
|
// if(emac_phy_register_read(PHY_ADDRESS, PHY_SPECIFIED_CS_REG, &data) == ERROR)
|
|
// {
|
|
// return ERROR;
|
|
// }
|
|
|
|
if (emac_phy_register_read(PHY_ADDRESS, PHY_AUTO_NEG_REG, &data) == ERROR) {
|
|
return ERROR;
|
|
}
|
|
|
|
#ifdef DM9162
|
|
if(data & PHY_FULL_DUPLEX_100MBPS_BIT)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_100MBPS);
|
|
emac_duplex_mode_set(EMAC_FULL_DUPLEX);
|
|
}
|
|
else if(data & PHY_HALF_DUPLEX_100MBPS_BIT)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_100MBPS);
|
|
emac_duplex_mode_set(EMAC_HALF_DUPLEX);
|
|
}
|
|
else if(data & PHY_FULL_DUPLEX_10MBPS_BIT)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_10MBPS);
|
|
emac_duplex_mode_set(EMAC_FULL_DUPLEX);
|
|
}
|
|
else if(data & PHY_HALF_DUPLEX_10MBPS_BIT)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_10MBPS);
|
|
emac_duplex_mode_set(EMAC_HALF_DUPLEX);
|
|
}
|
|
#else
|
|
if(data & PHY_DUPLEX_MODE)
|
|
{
|
|
emac_duplex_mode_set(EMAC_FULL_DUPLEX);
|
|
}
|
|
else
|
|
{
|
|
emac_duplex_mode_set(EMAC_HALF_DUPLEX);
|
|
}
|
|
if(data & PHY_SPEED_MODE)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_10MBPS);
|
|
}
|
|
else
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_100MBPS);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
if(emac_phy_register_write(PHY_ADDRESS, PHY_CONTROL_REG, (uint16_t)((mode << 8) | (speed << 13))) == ERROR)
|
|
{
|
|
return ERROR;
|
|
}
|
|
if(speed == EMAC_SPEED_100MBPS)
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_100MBPS);
|
|
}
|
|
else
|
|
{
|
|
emac_fast_speed_set(EMAC_SPEED_10MBPS);
|
|
}
|
|
if(mode == EMAC_FULL_DUPLEX)
|
|
{
|
|
emac_duplex_mode_set(EMAC_FULL_DUPLEX);
|
|
}
|
|
else
|
|
{
|
|
emac_duplex_mode_set(EMAC_HALF_DUPLEX);
|
|
}
|
|
}
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief initialize emac phy
|
|
* @param none
|
|
* @retval SUCCESS or ERROR
|
|
*/
|
|
error_status emac_phy_init(emac_control_config_type *control_para)
|
|
{
|
|
emac_clock_range_set();
|
|
if(emac_phy_register_reset() == ERROR)
|
|
{
|
|
return ERROR;
|
|
}
|
|
if(emac_speed_config(control_para->auto_nego, control_para->duplex_mode, control_para->fast_ethernet_speed) == ERROR)
|
|
{
|
|
return ERROR;
|
|
}
|
|
|
|
emac_control_config(control_para);
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|