121 lines
5.0 KiB
C
121 lines
5.0 KiB
C
/**
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**************************************************************************
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* @file at32_emac.h
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* @version v2.0.4
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* @date 2021-12-31
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* @brief header file of emac config program.
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32_EMAC_H
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#define __AT32_EMAC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F437_periph_examples
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* @{
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*/
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/** @addtogroup 437_EMAC_tcp_server
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* @{
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*/
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#define RX_REMAP (1)
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#define CRYSTAL_ON_PHY (0)
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#define MII_MODE
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//#define RMII_MODE
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#define DM9162
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//#define DP83848
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#if defined (DM9162)
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#define PHY_ADDRESS (0x03) /*!< relative to at32 board */
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x11) /*!< specified configuration and status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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#define PHY_AUTO_NEG_REG (0x05) /*!< Auto-Negotiation Link Partner Ability Register */
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/* phy specified control/status register */
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// #define PHY_FULL_DUPLEX_100MBPS_BIT (0x8000) /*!< full duplex 100 mbps */
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// #define PHY_HALF_DUPLEX_100MBPS_BIT (0x4000) /*!< half duplex 100 mbps */
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// #define PHY_FULL_DUPLEX_10MBPS_BIT (0x2000) /*!< full duplex 10 mbps */
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// #define PHY_HALF_DUPLEX_10MBPS_BIT (0x1000) /*!< half duplex 10 mbps */
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#define PHY_FULL_DUPLEX_100MBPS_BIT (0x0100) /*!< full duplex 100 mbps */
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#define PHY_HALF_DUPLEX_100MBPS_BIT (0x0080) /*!< half duplex 100 mbps */
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#define PHY_FULL_DUPLEX_10MBPS_BIT (0x0040) /*!< full duplex 10 mbps */
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#define PHY_HALF_DUPLEX_10MBPS_BIT (0x0020) /*!< half duplex 10 mbps */
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#elif defined (DP83848)
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#define PHY_ADDRESS (0x01) /*!< relative to at32 board */
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#define PHY_CONTROL_REG (0x00) /*!< basic mode control register */
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#define PHY_STATUS_REG (0x01) /*!< basic mode status register */
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#define PHY_SPECIFIED_CS_REG (0x10) /*!< phy status register */
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/* phy control register */
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#define PHY_AUTO_NEGOTIATION_BIT (0x1000) /*!< enable auto negotiation */
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#define PHY_LOOPBACK_BIT (0x4000) /*!< enable loopback */
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#define PHY_RESET_BIT (0x8000) /*!< reset phy */
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/* phy status register */
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#define PHY_LINKED_STATUS_BIT (0x0004) /*!< link status */
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#define PHY_NEGO_COMPLETE_BIT (0x0020) /*!< auto negotiation complete */
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#define PHY_DUPLEX_MODE (0x0004) /*!< full duplex mode */
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#define PHY_SPEED_MODE (0x0002) /*!< 10 mbps */
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#endif
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error_status emac_system_init(void);
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error_status emac_system_init_eth(void);
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void emac_nvic_configuration(void);
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void emac_pins_configuration(void);
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error_status emac_layer2_configuration(void);
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void static reset_phy(void);
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error_status emac_phy_register_reset(void);
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error_status emac_speed_config(emac_auto_negotiation_type nego, emac_duplex_type mode, emac_speed_type speed);
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error_status emac_phy_init(emac_control_config_type *control_para);
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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